CN114203128B - Display panel driving method and circuit and display device - Google Patents

Abstract

The invention discloses a display panel driving method, circuit and display device, wherein the method includes: for each clock signal line, determining the current target pixel row to be refreshed; Target signal slope; the signal slope indicates the speed at which the clock signal transitions between high level and low level, and the slope comparison table includes the corresponding relationship between each pixel row of the display panel and the signal slope of the clock signal; based on the target signal slope, output the target pixel Line scan drive signal. The method of the invention can effectively suppress the defect of horizontal stripes of the display screen.

Description

A display panel driving method, circuit and display device

technical field

The present invention relates to the field of display technology, in particular to a display panel driving method, circuit and display device.

Background technique

Currently, with the development of LCD (Liquid Crystal Display, liquid crystal display) technology, products generally require high resolution, large size, and high refresh rate. However, during the development process, especially panels with high resolution, large size, and high refresh rate are prone to periodic horizontal stripes.

Therefore, there is an urgent need for a method or device capable of improving the periodic horizontal stripe defect of the display panel.

Contents of the invention

In view of the above problems, the present invention proposes a display panel driving method, circuit and display device, which can realize independent control of the driving capabilities between different clock signal lines, and control based on the slope comparison table of test calibration, which can effectively reduce The difference in Gout Timing falling (Gout Tf) of the row gate voltage of each pixel row effectively suppresses the defect of horizontal stripes of the display screen.

In the first aspect, the present application provides the following technical solutions through an embodiment:

A method for driving a display panel, comprising:

For each clock signal line, determine the current target pixel row to be refreshed; obtain the target signal slope matching the target pixel row in the slope comparison table; the signal slope indicates that the clock signal is between high level and low level The conversion speed, the slope comparison table includes the corresponding relationship between each pixel row of the display panel and the signal slope of the clock signal; based on the target signal slope, output the scan driving signal of the target pixel row.

Optionally, the outputting the scanning driving signal of the target pixel row based on the slope of the target signal includes:

Controlling the first level shifting unit matching the current clock signal line to output the scan driving signal with a driving capability matching the slope of the target signal; wherein each clock signal line corresponds to a first level shifting unit.

Optionally, the control of the first level shift unit matching the current clock signal line to output the scanning driving signal with a driving capability matching the slope of the target signal includes:

In response to the change of the target signal slope relative to the signal slope of the previous historical refresh pixel row, the control bit in the register is increased or decreased by a preset value to obtain the target control bit; the preset value is compared with the slope Control bit difference values of two adjacent signal slopes corresponding to the same clock signal line in the table; control the first level shift unit matching the current clock signal line to output the scan driving signal based on the target control bit.

Optionally, the outputting the scanning driving signal of the target pixel row based on the slope of the target signal includes:

Based on the slope of the target signal, determine the target voltage from the scan-off voltage interval; wherein, the upper limit of the scan-off voltage interval is the pixel row turn-off holding voltage, and the lower limit is the pixel row turn-off voltage; control the second level The displacement unit outputs the scan driving signal based on the target voltage.

Optionally, the determining the current target pixel row to be refreshed includes:

A trigger signal is received; a counting unit is initialized based on the trigger signal to obtain an initial count value; and the target pixel row is obtained based on a scanning driving signal of historically refreshed pixel rows and the initial count value.

Optionally, the obtaining the target pixel row based on the historically refreshed scan driving signal of the pixel row and the initial count value includes:

The target pixel row is obtained by adding one to the initial count value based on the scan driving signal of each historical refresh pixel row; wherein each count value corresponds to at least one row of pixels.

Optionally, the trigger signal includes:

Pre-frame reset signal and/or pre-frame pulse trigger signal.

In the second aspect, based on the same inventive concept, this application provides the following technical solution through an embodiment:

A display panel drive circuit, comprising: a counting circuit, a change judgment circuit, and a drive capability control circuit, the count circuit is connected to the change judgment circuit, and the change judgment circuit is connected to the drive capability control circuit;

For each clock signal line, the counting circuit is configured to determine the current target pixel row to be refreshed; the change judgment circuit is configured to obtain the target signal slope matched by the target pixel row from the slope comparison table; The signal slope indicates the speed at which the clock signal transitions between high level and low level, and the slope comparison table includes the corresponding relationship between each pixel row of the display panel and the signal slope of the clock signal; the driving capability control circuit is controlled by configured to output a scan driving signal of the target pixel row based on the target signal slope.

Optionally, the drive capability control circuit includes a first level shift subcircuit, and each clock signal line matches a first level shift subcircuit;

The first level shifting sub-circuit is configured to output the scan driving signal with a driving capability matching the slope of the target signal.

Optionally, the drive capability control circuit further includes a control bit change subcircuit, and a register connected to the control bit change subcircuit;

The control bit changing subcircuit is configured to increase or decrease the control bit in the register by a preset value in response to the change of the target signal slope relative to the signal slope of the last historically refreshed pixel row to obtain the target Control bit; the preset value is the control bit difference between two adjacent signal slopes corresponding to the same clock signal line in the slope comparison table; the first level shift unit is also configured to, based on the target control bit and outputting the scan driving signal.

Optionally, the driving capability control circuit includes a voltage divider subcircuit and a second level shift subcircuit connected to the voltage divider subcircuit;

The voltage dividing sub-circuit is configured to determine the target voltage from the scan-off voltage interval based on the target signal slope; wherein, the upper limit of the scan-off voltage interval is the pixel row off-hold voltage, and the lower limit is the pixel row off-hold voltage. Row off voltage; the second level shifting sub-circuit configured to output the scan driving signal based on the target voltage.

Optionally, the counting circuit includes an initialization subcircuit and a counting subcircuit connected to the initialization subcircuit;

The initialization subcircuit is configured to initialize the counting subcircuit based on the received trigger signal to obtain an initial count value; the counting subcircuit is configured to refresh the scanning driving signal of the pixel row based on history and the initial counting value, to obtain the target pixel row.

Optionally, the counting subcircuit is further configured to add one to the initial count value based on the scan driving signal of each historical refresh pixel row to obtain the target pixel row; wherein each count value corresponds to At least one row of pixels.

Optionally, the trigger signal includes:

Pre-frame reset signal and/or pre-frame pulse trigger signal.

In the third aspect, based on the same inventive concept, this application provides the following technical solutions through an embodiment:

A display device, comprising the display panel drive circuit described in any one of the above second aspects.

In a display panel driving method in an embodiment of the present invention, for each clock signal line, count the current target pixel row to be refreshed to determine the row number of the target pixel row; read the slope comparison table and judge the target A signal slope corresponding to the pixel row; outputting a corresponding scanning driving signal based on the signal slope. In this way, the same clock signal line can independently control the signal slopes driving different pixel rows, and independent control can also be realized between different clock signal lines. The control is based on the slope comparison table of the test calibration, which can effectively reduce the slew rate of each pixel row. The G _out Tf difference effectively suppresses the horizontal stripes of the display screen.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the specific embodiments of the present invention are enumerated below.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort. In the attached picture:

FIG. 1 is a schematic diagram showing a time-consuming comparison of row gate voltage drop for each pixel row of a conventional display panel;

FIG. 2 is a schematic diagram showing a time-consuming comparison of row gate voltage drop of each pixel row in another existing display panel;

FIG. 3 shows a flowchart of a method for driving a display panel in an embodiment of the present invention;

FIG. 4 shows a schematic diagram of waveforms corresponding to clock signals corresponding to different signal slopes in an embodiment of the present invention;

FIG. 5 shows a schematic structural diagram of a display panel driving circuit in an embodiment of the present invention;

FIG. 6 shows a schematic structural diagram of yet another specific display panel driving circuit in an embodiment of the present invention;

FIG. 7 shows a schematic structural diagram of yet another specific display panel driving circuit in an embodiment of the present invention.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

Through testing and analysis, the applicant found that in a display panel with high resolution, large size and high refresh rate, the charging time of each row of pixels decreases exponentially. Therefore, in a very short charging time, the picture quality displayed on the panel is extremely sensitive to external interference and charging differences caused by large size. For example, the periodic clock signal will be crosstalked by other signals, which will cause the charging rate of the pixels controlled by one of the periodic clock signals to change, and the entire row will be bright or dark.

Please refer to Figure 1-2. Figure 1 shows the time-consuming (G out Timing falling, G _out Timing falling, G _out Tf) Schematic diagram of comparison; FIG. 2 is a schematic diagram of the time-consuming comparison of the row gate voltage drop of each pixel row when periodic horizontal stripes appear on another 75-inch 4K resolution 144HZ refresh rate display panel. In the display panel corresponding to Figure 1 and Figure 2, the resistance of the clock signal line before entering the pixel row is 10Ω, and the row gate drive corresponds to 6 sets of clock cycle signals (6CLK); the abscissa m in Figure 1 and Figure 2 is The row number of the pixel row, and the ordinate t is the time-consuming for the row gate voltage to drop. Through the tests in Figure 1 and Figure 2, it can be found that for the same clock signal at different locations, there will be differences in G _out Tf due to external interference and wiring factors. For example, there is a time difference between line D2130 and line D2160; at the same time, there will be a more obvious G _out Tf difference between different clock signals, for example, there is also a G _out Tf of each line between line D2155 and line D2160 More obvious differences; thus easily lead to more obvious bad stripes. And the overall appearance is that the DP side is inconsistent with the DPO side (usually the side where the active driver is installed is called the DP side, and the DPO side is the side opposite to the DP side). At present, the clock signal is improved by matching different resistors in the GOA (Gate Driver on Array, array substrate gate drive) unit, but this improvement method is not operable, the implementation efficiency is low, and it cannot take into account the middle and upper and lower sides of the screen , the improvement effect is not obvious.

Therefore, in an embodiment of the present invention, a method for driving a display panel, a display panel driving circuit capable of implementing the method for driving the display panel, and a display device to which the method for driving the display panel and the driving circuit for the display panel can be applied are proposed in an embodiment of the present invention. In order to overcome display defects such as horizontal lines caused by differences in G _out Tf in existing LCD display panels. The specific concept of the present invention will be described in detail below through specific embodiments.

Please refer to FIG. 3 . FIG. 3 shows a flowchart of a method for driving a display panel provided in an embodiment of the present invention. The display panel driving method includes:

Step S10: For each clock signal line, determine the current target pixel row to be refreshed;

Step S20: Obtain the target signal slope matching the target pixel row in the slope comparison table; the signal slope indicates the speed at which the clock signal transitions between high level and low level, and the slope comparison table includes the The corresponding relationship between each pixel row and the signal slope of the clock signal;

Step S30: Based on the slope of the target signal, output the scanning driving signal of the target pixel row.

In this embodiment, during the progressive scanning of the display panel through steps S10-S30, for each clock signal line, when refreshing a certain row of target pixel rows, the corresponding signal slope (slew rate) is searched in the slope comparison table , so as to output the scan driving signal of the target pixel row based on the found slope of the target signal. In this way, independent control of the scanning driving signals of different pixel rows can be realized, thereby adjusting the scanning driving signals of each pixel row separately to compensate for the G _out Tf of each pixel row being affected by the outside world, that is, to realize the charging of each pixel row The adjustment of the ratio can reduce the G _out Tf difference of each pixel row, effectively suppressing the horizontal stripes of the display screen; and the operability of the realization is strong. The specific possible implementation of each step of this embodiment will be described and illustrated in more detail below.

Step S10: For each clock signal line, determine the current target pixel row to be refreshed.

In step S10 , it can be understood that for each clock signal line, various steps can be performed according to the method of this embodiment to realize independent adjustment of the scanning driving signal in different pixel rows.

When determining the current target pixel row to be refreshed, it can be counted and obtained in the following manner; specifically, each time a frame is refreshed, it can be counted from an initial count value; each time a pixel row is refreshed, based on the initial count value Increment a value, and the number of counts will be increased when the row is refreshed, so as to ensure real-time positioning of the current target pixel row to be refreshed.

For example, the counting unit can be initialized based on the received trigger signal; the trigger signal can be a pre-frame reset signal and/or a pre-frame pulse trigger signal, and the pre-frame reset signal is transmitted by the reset signal line to reset the GOA unit The signal (STV0) before the frame, the pulse trigger signal before the frame is the signal (STV1) that triggers the GOA unit to output the driving pulse; the reset signal before the frame and/or the pulse trigger signal before the frame can come from TCON (Timer Control Register, timing controller). Then, the counting unit is initialized based on the trigger signal to obtain an initial counting value; the counting unit can use an existing counting circuit to realize the counting function without limitation. Then, the target pixel row is obtained based on the scanning driving signal and the initial count value of the historical refresh pixel row. In some implementations, the initial count value can be increased by one based on the scan driving signal of each historically refreshed pixel row, that is, the count value can be increased by one every time a clock cycle passes to obtain the target pixel row; Each rising edge is used to trigger counting; each count value corresponds to at least one row of pixels; when more than two rows are refreshed at the same time, one count value can correspond to more than two rows of pixels.

For ease of understanding, an example of a 6CLK clock signal is used for illustration. For the clock signal CLK1, the initial count value is 0 (corresponding to the first row of pixels of the display panel at this time), and the count value can be stored in a memory. ; then every refresh the pixel row corresponding to 1 row CLK1, then the count value in the memory can be added by 1; , the initial count value in the memory is increased by 1 and stored as 2; when the pixel row corresponding to the third row CLK1 is refreshed (corresponding to the 13th row of pixels of the display panel at this time), the count value in the memory is increased by 1 , stored as 3; and so on. In a 4K resolution display panel, the total number of counts of CLK1 is 360; the clock signals CLK2, CLK3, CLK4, CLK5, and CLK6 can be implemented with reference to the clock signal CLK1, and this example will continue to be used for illustration. In other implementation manners, the number of clock signal lines is not limited, for example, it may be 4CLK, 12CLK, 16CLK and so on.

Through the above counting method, the current pixel row to be refreshed can be accurately located, which is a prerequisite for realizing independent control of the scanning driving signal of each row.

Step S20: Obtain the target signal slope matching the target pixel row in the slope comparison table; the signal slope indicates the speed at which the clock signal transitions between high level and low level, and the slope comparison table includes the The corresponding relationship between each pixel row and the signal slope of the clock signal.

In step S20, the slope comparison table may include the corresponding relationship between each pixel row corresponding to a clock signal line and the signal slope; it may also include the corresponding relationship between each pixel row corresponding to a plurality of clock signal lines and the signal slope, without limitation . The corresponding relationship can be that the identification code of the target pixel row corresponds to the signal slope or its identification code; the target signal slope can be indexed in the slope comparison table based on the target pixel row, and the data structure of the slope comparison table is not limited; the slope comparison table can be preset Stored in a memory, when the step is executed, the slope comparison table is invoked or read by the processor or circuit executing the step.

It should be noted that the signal slope can be a rising slope, that is, the speed (slope) at which the clock signal changes from low level to high level; it can also be a falling slope, that is, the speed at which the clock signal changes from high level to low level (slope).

Since the GOA RC loading (resistance-capacitance load) is different in display panels of different sizes and different processes, the corresponding slope comparison tables for different display panels will also be different. In this embodiment, the signal slope corresponding to the pixel row can be determined by means of test calibration, for example, during the test, adjust the signal slope of each area of the display panel, and observe or test whether there is a bad horizontal stripe on the display screen; based on To meet the image quality requirements, find the optimal or better set of signal slopes. The signal slope changes stepwise to avoid excessive control gears and improve operability; for example, the signal slope of the first 100 lines of the clock signal CLK1 is the same, the signal slope of the middle 200 lines is the same, and the signal slope of the last 60 lines is the same. Different signal slopes correspond to different signal waveforms, thereby realizing the adjustment of G _out Tf, as shown in FIG. 4 . Figure 4 shows the signal waveforms of the clock signals of a 75-inch 4K resolution 144hz refresh rate display panel at the signal slopes of C1 (1000V/us), R2 (400V/us), and R1 (100V/us). .

Step S30: Based on the slope of the target signal, output the scanning driving signal of the target pixel row.

In step S30, the determined target signal slope can be achieved through one or more implementation methods, so as to output a scan driving signal matching the target signal slope, and realize the adjustment of G _out Tf. At least two implementation manners are provided in this embodiment.

1. Control the driving capability of the scanning signal by controlling the output current of each clock signal line channel.

The driving capability of the respective clock signals corresponding to different pixel rows can be set according to needs, so as to realize the debugging of the signal slope. In this method, all the current clock signal lines share the same drive capability setting, and each clock signal line uses a separate drive capability setting, so each clock signal line is connected with its matching level. displacement unit.

Specifically, this method can use multiple level shift units (in order to facilitate the distinction of the level shift unit in this implementation, named as the first level shift unit) to achieve different driving capabilities, each clock signal line corresponds to a The first level shift unit. Then, the first level shift unit matching the current clock signal line can be controlled to output a scanning driving signal with a driving capability matching the slope of the target signal. In order to facilitate control, a register is set to store the driving capability of the first level shift unit and the corresponding control bits. The circuit implementation of the level shifting unit can adopt the existing implementation manner, and will not be described in detail.

For example, continue to take the aforementioned 75-inch 4K resolution 144hz refresh rate display panel as an example for illustration. After testing, the clock signal corresponding to each clock signal line can be set to 4 gears, and each gear can use the first A level shift unit is implemented, respectively: 100% driving ability, 80% driving ability, 40% driving ability and 10% driving ability; 2 bits can be used to control the changes between these 4 gears. For the clock signal CLK1, the corresponding relationship between the control bit and the drive capacity gear can be: 00 (100% drive capacity), 01 (80% drive capacity), 10 (40% drive capacity), 11 (10% drive capacity) Drive capability).

Further, when step S30 is implemented, the first level shift unit matching the current clock signal line can be controlled to output a scanning driving signal with a driving capability matching the slope of the target signal; for example, when a driving capability of 100% is required to achieve The target signal slope controls the first level shift unit to adjust the output current based on the control bit being 00, so as to output a scanning driving signal with 100% driving capability, and so on. The scanning driving signal also needs to be processed by the GOA unit of the display panel, and finally the gate driving signal for driving the pixel row is obtained; for example, it is shifted by a shift unit (shift register).

When adjusting the driving capability of the output scanning driving signal, it can be as follows:

In response to the fact that the slope of the target signal does not change relative to the last historically refreshed pixel row, the original driving capability remains unchanged, and the value of the control bit in the register remains unchanged.

Powering on the display panel as needed can initialize the driving capability of the clock signal corresponding to all clock signal lines, and then change the driving capability of the clock signal according to the determined target signal slope; since the general panel transitions uniformly from the DP side to the DPO side, the same The driving capabilities of adjacent pixel rows corresponding to the clock signal will not jump.

Therefore, when the target signal slope changes relative to the signal slope of the previous historical refresh pixel row, the control bit in the register is increased or decreased by a preset value to obtain the target control bit; the preset value is the same clock in the slope comparison table The control bit difference value of two adjacent signal slopes corresponding to the signal line. Next, control the first level shift unit matching with the current clock signal line to output the scan driving signal based on the target control bit. Taking the aforementioned example of 2bit controlling 4 gears as an example, the value of the control bit in the register can be added or subtracted by 1 to realize the continuous adjustment of the driving ability of the first level shift unit; in addition, based on the number of gears Differently, the bit width of the control bits can also be adjusted correspondingly without limitation.

2. Adjusting and realizing the target signal slope by controlling the magnitude of the pixel row off-holding voltage (VGL).

In this implementation manner, a voltage dividing unit can be added to adjust the off-hold voltage of the pixel row, and the circuit implementation of the voltage dividing unit will be described in subsequent device embodiments. Specifically, the implementation process can be as follows:

First, based on the slope of the target signal, determine the target voltage from the scan-off voltage interval; wherein, the upper limit of the scan-off voltage interval is the pixel row turn-off holding voltage, and the lower limit is the pixel row turn-off voltage (LVGL); the pixel row turn-off The hold voltage is the voltage of the GOA unit in the off-hold stage; the pixel row off voltage is the voltage when the GOA unit is turned off. Similarly, in order to provide operability, multiple control gears can be set; that is, multiple voltage value points are determined in the scan-off voltage interval, and each voltage value point corresponds to a control gear. For example, when setting 4 gears, V1, V2, V3 and V4 can be set. The 4 voltages correspond to different signal slopes. The target voltage will be input to the level shift unit (in order to facilitate the distinction, the level shift unit is recorded as the second level shift unit), and then the second level shift unit is controlled to output the scanning drive signal based on the target voltage to realize the signal of the clock signal Slope adjustment reduces the G _out Tf difference and effectively suppresses the horizontal stripes of the display screen.

Therefore, in this embodiment, independent control of the scan driving signals of different pixel rows can be achieved through the above two methods, and the signal slopes of the clock signals of the pixel rows in different regions of the display panel can be flexibly adjusted to test the calibration slope comparison table Based on the control, it can effectively reduce the G _out Tf difference of each pixel row, and effectively suppress the horizontal stripe defect of the display screen.

Please refer to FIG. 5 , based on the same inventive concept, a display panel drive circuit 300 is also provided in another embodiment of the present invention, including: a counting circuit 31 , a change judgment circuit 32 and a driving capability control circuit 33 , and the counting circuit 31 It is connected with the change judgment circuit 32, and the change judgment circuit 32 is connected with the driving ability control circuit 33; for each clock signal line, each circuit structure in this embodiment can perform the following functions.

The counting circuit 31 is configured to determine the current target pixel row to be refreshed.

In some practicable implementations, the counting circuit 31 includes an initialization subcircuit and a counting subcircuit connected to the initialization subcircuit. Wherein, the initialization subcircuit is configured to initialize the counting subcircuit based on the received trigger signal to obtain an initial count value; the counting subcircuit is configured to obtain the target pixel row based on the scanning drive signal and the initial count value of the historically refreshed pixel row . The trigger signal may include: a pre-frame reset signal and/or a pre-frame pulse trigger signal.

Further, the counting sub-circuit is further configured to add one to the initial count value based on the scanning driving signal of each historically refreshed pixel row to obtain a target pixel row; wherein each count value corresponds to at least one row of pixels.

The change judgment circuit 32 is configured to obtain the target signal slope matching the target pixel row in the slope comparison table; the signal slope indicates the speed at which the clock signal is switched between high level and low level, and the slope comparison table includes each of the display panel. The corresponding relationship between the pixel row and the signal slope of the clock signal. The slope comparison table can be pre-stored in a memory.

The driving ability control circuit 33 is configured to output the scanning driving signal of the target pixel row based on the slope of the target signal.

The scanning driving signal is a signal output by the shift unit, and further processing is required to obtain the gate driving signal of the pixel row; for example, it needs to be shifted by a shift register.

The drive signal input circuit includes at least two specific implementation methods:

1. By controlling the magnitude of the output current of the first level shifting sub-circuit 331a, the scanning driving signals with different signal slopes are output; and each clock signal line is matched with a first level shifting sub-circuit to realize different clock signal lines for independent control.

Please refer to FIG. 6 , in this optional implementation manner, the driving capability control circuit 33 includes a first level shift subcircuit 331a; the first level shift subcircuit 331a is configured to output a signal that matches the slope of the target signal Drive capability scan drive signal. Specifically, after the display panel is powered on, the first level shift sub-circuit 331a initializes the driving capability corresponding to the clock line, and subsequently changes the driving capability according to the signal received from the change determination circuit 32 .

Further, the drive capability control circuit 33 also includes a control bit change subcircuit, and a register (not shown) connected to the control bit change subcircuit; the control bit change subcircuit is configured to: respond to the target signal slope relative to When the signal slope of the previous historical refresh pixel row changes, increase or decrease the preset value of the control bit in the register to obtain the target control bit; the preset value is two adjacent signals corresponding to the same clock signal line in the slope comparison table The control bit difference value of the slope; the first level shift unit 331a is further configured to output a scan driving signal based on the target control bit.

2. Divide the off-hold voltage of the pixel row through the voltage dividing sub-circuit 330b, so as to realize the output of scanning driving signals with different signal slopes.

Please refer to FIG. 7 , in this optional implementation manner, the driving capability control circuit 33 includes a voltage divider subcircuit 330b and a second level shift subcircuit 333b connected to the voltage divider subcircuit 330b; the voltage divider subcircuit 330b is It is configured to determine the target voltage from the scan-off voltage interval based on the target signal slope; wherein, the upper limit of the scan-off voltage interval is the pixel row-off holding voltage (VGL), and the lower limit is the pixel row-off voltage (LVGL); The second level shifting sub-circuit 333b is configured to output the scan driving signal based on the target voltage.

Wherein, the voltage divider sub-circuit 330b can be composed of a controller 331b and a digital-to-analog converter (DAC) 332b, and the controller 331b can receive the signal representing the slope of the signal or the change of the slope of the signal transmitted by the change judgment circuit 32, and then drive the DAC to turn off The off-hold voltage is processed to output a target voltage (VGLx) located in the scan-off voltage interval, that is, the target voltage is less than or equal to the pixel row off-hold voltage, and greater than or equal to the pixel row off-voltage; then, the second level shift The sub-circuit 333b receives the target voltage, and outputs a scan driving signal according to the target voltage and the original turn-on voltage (VGH). The controller 331b and the digital-to-analog converter 332b can be realized by using existing devices or circuit structures, without limitation.

If there are adjacent rows with signal slope changes in the display panel, the change mode is continuous change instead of jumping, then the change judgment circuit 32 can determine the target signal slope relative to the previous pixel after the change judgment circuit 32 has determined the target signal slope. Whether the slope of the signal corresponding to the line changes. If there is a change, the change judgment circuit 32 outputs a signal indicating that there is a change to the controller 331b, so that the controller 331b drives the digital-to-analog converter 332b to output the target voltage; if there is no change, the change judgment circuit 32 can output a representative signal slope The signal that has not changed is sent to the level shift sub-circuit to keep the scanning driving signal output by the driving capability control circuit 33 unchanged, and does not need to be processed by the controller 331b at this time.

It should be noted that, in this implementation manner, since the voltage dividing sub-circuit 330b is used to divide the off-hold voltage of the pixel row, multiple clock signal lines can share the second level shifting sub-circuit 333b.

In the display panel driving circuit 300 in this embodiment, for each clock signal line, the counting circuit 31 can count the current target pixel row to be refreshed to determine the row number of the target pixel row; then, by changing the judgment The circuit 32 reads the slope comparison table and determines the signal slope corresponding to the target pixel row; finally, the driving capability control circuit 33 outputs the corresponding scanning driving signal based on the signal slope. As a result, the same clock signal line can independently control the signal slopes driving different pixel rows, and independent control can also be achieved between different clock signal lines. The control is based on the test calibration slope comparison table, which can effectively reduce the pixel row. The difference in G _out Tf effectively suppresses the horizontal stripes of the display screen.

It should be noted that, in this embodiment, among multiple clock signal lines, the counting circuit 31 and the change judgment circuit 32 can be shared, and the signal processing of different clock signal lines can be distinguished through different signal marks; in addition, Independent counting circuits 31 and change judging circuits 32 can also be designed for different clock signal lines, without limitation.

It should also be noted that the display panel drive circuit 300 provided in this embodiment can be used to implement each processing step in the foregoing method embodiments; therefore, the specific realization of each function of each circuit and sub-circuit structure in this embodiment Reference may be made to the foregoing method embodiments, and details are not described in this embodiment. The specific hardware implementation of each circuit or sub-circuit structure not mentioned in this embodiment can adopt the existing common implementation method, and will not be described in this embodiment.

Based on the same inventive concept, another embodiment of the present invention further provides a display device, including any display panel driving circuit in the foregoing embodiments.

It should be noted that the display device provided by the embodiment of the present invention adopts the display panel driving circuit of the foregoing embodiment, and its specific implementation and technical effects are the same as those of the foregoing method embodiment. For the relevant parts, reference may be made to the corresponding content in the foregoing embodiments.

The term "and/or" appearing in this article is just an association relationship describing associated objects, indicating that there may be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, There are three cases of B alone. In addition, the character "/" in this article generally means that the related objects are an "or" relationship; the word "comprising" does not exclude the existence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

Those skilled in the art should understand that the embodiments of the present invention may be provided as methods, systems, or computer program products. Accordingly, the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

While preferred embodiments of the invention have been described, additional changes and modifications to these embodiments can be made by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be construed to cover the preferred embodiment as well as all changes and modifications which fall within the scope of the invention.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (15)

1. A display panel driving method, comprising:

determining a current target pixel row to be refreshed aiming at each clock signal line;

acquiring a target signal slope matched with the target pixel row from a slope comparison table; the signal slope represents the speed of the clock signal switching between a high level and a low level, and the slope comparison table comprises the corresponding relation between each pixel row of the display panel and the signal slope of the clock signal;

and outputting the scanning driving signal of the target pixel row based on the target signal slope.

2. The method of claim 1, wherein outputting the scan driving signal for the target pixel row based on the target signal slope comprises:

controlling a first level shift unit matched with a current clock signal line to output the scanning driving signal with the driving capability matched with the target signal slope; each clock signal line corresponds to a first level shift unit.

3. The method of claim 2, wherein the controlling the first level shift unit matched to the current clock signal line to output the scan driving signal with a driving capability matched to the target signal slope comprises:

when the target signal slope is changed relative to the signal slope of the last historical refresh pixel row, increasing or decreasing the control bit in the register by a preset value to obtain a target control bit; the preset value is a control bit difference value of two adjacent signal slopes corresponding to the same clock signal line in the slope comparison table;

and controlling a first level shift unit matched with the current clock signal line to output the scanning driving signal based on the target control bit.

4. The method of claim 1, wherein outputting the scan drive signal for the target row of pixels based on the target signal slope comprises:

determining a target voltage from a scan-off voltage interval based on the target signal slope; the upper limit of the scanning turn-off voltage interval is the pixel row turn-off holding voltage, and the lower limit of the scanning turn-off voltage interval is the pixel row turn-off voltage;

and controlling a second level shift unit to output the scanning driving signal based on the target voltage.

5. The method of claim 1, wherein determining the target row of pixels to be refreshed currently comprises:

receiving a trigger signal;

initializing a counting unit based on the trigger signal to obtain an initial counting value;

and obtaining the target pixel row based on the scanning driving signal of the historical refreshing pixel row and the initial counting value.

6. The method of claim 5, wherein obtaining the target row of pixels based on the initial count value and the scan drive signal to refresh the row of pixels based on the history comprises:

adding one to the initial count value based on the scanning driving signal of each historical refreshing pixel row to obtain the target pixel row; wherein each count value corresponds to at least one row of pixels.

7. The method of claim 5, wherein the trigger signal comprises:

a pre-frame reset signal and/or a pre-frame pulse trigger signal.

8. A display panel driving circuit, comprising: the counting circuit is connected with the change judging circuit, and the change judging circuit is connected with the driving capability control circuit;

for each clock signal line, the counting circuit is configured to determine a target pixel row to be refreshed currently;

the change judging circuit is configured to acquire a target signal slope matched with the target pixel row in a slope comparison table; the signal slope represents the speed of the clock signal switching between a high level and a low level, and the slope comparison table comprises the corresponding relation between each pixel row of the display panel and the signal slope of the clock signal;

the driving capability control circuit is configured to output a scan driving signal of the target pixel row based on the target signal slope.

9. The display panel driving circuit according to claim 8, wherein the driving capability control circuit comprises a first level shift sub-circuit, each clock signal line matching a first level shift sub-circuit;

the first level shift sub-circuit is configured to output the scan driving signal of a driving capability matched with the target signal slope.

10. The display panel driving circuit according to claim 9, wherein the driving capability control circuit further comprises a control bit changing sub-circuit, and a register connected to the control bit changing sub-circuit;

the control bit changing sub-circuit is configured to increase or decrease the control bit in the register by a preset value in response to a change of the target signal slope relative to the signal slope of the last historical refresh pixel row, so as to obtain a target control bit; the preset value is a control bit difference value of two adjacent signal slopes corresponding to the same clock signal line in the slope comparison table;

the first level shift unit is further configured to output the scan driving signal based on the target control bit.

11. The display panel driving circuit according to claim 8, wherein the driving capability control circuit comprises a voltage divider sub-circuit and a second level shift sub-circuit connected to the voltage divider sub-circuit;

the voltage divider sub-circuit is configured to determine a target voltage from a scan-off voltage interval based on the target signal slope; the upper limit of the scanning turn-off voltage interval is the pixel row turn-off holding voltage, and the lower limit of the scanning turn-off voltage interval is the pixel row turn-off voltage;

the second level shift sub-circuit configured to output the scan driving signal based on the target voltage.

12. The display panel driving circuit according to claim 8, wherein the counting circuit comprises an initialization sub-circuit and a counting sub-circuit connected to the initialization sub-circuit;

the initialization sub-circuit is configured to initialize the counting sub-circuit based on the received trigger signal to obtain an initial count value;

the counting sub-circuit is configured to obtain the target pixel row based on a scan driving signal of a history refresh pixel row and the initial count value.

13. The display panel drive circuit according to claim 12, wherein the count sub-circuit is further configured to obtain the target pixel row by adding one to the initial count value based on a scan drive signal for each of the history refresh pixel rows; wherein each count value corresponds to at least one row of pixels.

14. The display panel driving circuit according to claim 12, wherein the trigger signal comprises:

a pre-frame reset signal and/or a pre-frame pulse trigger signal.

15. A display device comprising the display panel drive circuit according to any one of claims 8 to 14.

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