CN114141283B

CN114141283B - Memory, memory control method and system

Info

Publication number: CN114141283B
Application number: CN202111160079.0A
Authority: CN
Inventors: 张君敬; 陈立刚; 刘江
Original assignee: Zhaoyi Innovation Technology Group Co ltd; Xi'an Geyi Anchuang Integrated Circuit Co ltd; GigaDevice Semiconductor Beijing Inc
Current assignee: Zhaoyi Innovation Technology Group Co ltd; Xi'an Geyi Anchuang Integrated Circuit Co ltd; GigaDevice Semiconductor Beijing Inc
Priority date: 2021-09-30
Filing date: 2021-09-30
Publication date: 2025-09-05
Anticipated expiration: 2041-09-30
Also published as: CN114141283A

Abstract

Disclosed are a memory, a memory control method, and a corresponding system. The memory includes: a memory cell array; and a memory cell array operation module, including: a read operation module, enabled in response to the memory receiving a memory cell array read instruction, and used to read the memory cell array; an erase operation module, enabled in response to the memory receiving a memory cell array erase instruction, and used to erase the memory cell array; and a program operation module, enabled in response to the memory receiving a memory cell array program instruction, and used to program the memory cell array. By independently setting up the read operation, program operation, and erase operation control modules, and enabling them only when the corresponding instructions are received and executed, the present invention can reduce the number of logic control circuits that need to be enabled when executing memory array operation instructions, thereby reducing the overall power consumption of the memory.

Description

Memory, memory control method and system

Technical Field

The present disclosure relates to the field of memories, and in particular, to a memory, a memory control method, and a corresponding system.

Background

Flash memory (Flash) is becoming more widely used today due to its high memory density, high reliability and low power consumption. Flash memory includes NAND flash memory and NOR flash memory. NOR flash memory, which may also be referred to as code-type memory, is commonly used with microcontrollers, supports on-chip execution (XIP, eXecute In Place), and has wide application in the direction of automotive electronics, wearable devices, smart appliances, home medical devices, and the like. NAND flash memory is widely used in various large-capacity devices such as memory cards, U-discs, SSDs, emmcs, and the like. With the improvement of device performance and integration level, and the characteristics of distributed applications, the replacement of batteries or frequent charging can cause a number of inconveniences. Therefore, how to extend battery life and reduce device power consumption is an important challenge for flash memory applications.

Disclosure of Invention

One technical problem to be solved by the present disclosure is to provide an improved memory, a memory control method and a corresponding system. The memory of the present invention may include independently set read, program and erase operation modules, and each operation module is enabled only upon receipt of a corresponding instruction. Thereby reducing the amount of logic control circuitry that needs to be enabled when executing memory array operation instructions, thereby reducing the overall power consumption of the memory.

According to a first aspect of the present disclosure, there is provided a memory including a memory cell array, and a memory cell array operation module including a read operation module enabled in response to the memory receiving a memory cell array read instruction and for performing a read operation on the memory cell array, an erase operation module enabled in response to the memory receiving a memory cell array erase instruction and for performing an erase operation on the memory cell array, and a program operation module enabled in response to the memory receiving a memory cell array program instruction and for performing a program operation on the memory cell array.

Optionally, the read operation module is disabled in response to the read operation execution completion, the erase operation module is disabled in response to the erase operation execution completion, and the program operation module is disabled in response to the program operation execution completion.

Optionally, the read operation module comprises a read voltage pump for generating a voltage required to be used in a read operation, and a read control circuit for controlling a data read operation of the memory cell array.

Optionally, the read control circuit comprises a read operation enabling signal circuit for enabling control of a voltage used in a read operation.

Optionally, the read voltage pump is enabled in a verify sub-operation of an erase operation and/or a program operation.

Optionally, the programming operation module comprises a programming voltage pump for generating voltages required to be used in the programming operation, and a programming control circuit for controlling the data programming operation of the memory cell array.

Optionally, the erasing operation module comprises an erasing voltage pump for generating a voltage required to be used in the erasing operation and an erasing control circuit for controlling the data erasing operation of the memory cell array.

Optionally, the program voltage pump is enabled in a soft programming sub-operation of the erase operation.

Optionally, the memory further comprises a power manager, and an instruction decoder,

The power manager can supply power to the instruction decoder in a standby state, responds to the storage unit array reading instruction to supply power to the reading operation module, responds to the storage unit array programming instruction to supply power to the programming operation module, and responds to the storage unit array erasing instruction to supply power to the erasing operation module.

Optionally, the power manager is configured to stop power supply to the instruction decoder to enter a low power consumption state in response to receiving a low power consumption state instruction, and resume power supply to the instruction decoder to return to the standby state in response to receiving a chip strobe signal.

According to a second aspect of the present disclosure, there is provided a memory control method including enabling a read operation module in a memory cell array operation module after a memory receives a memory cell array read instruction, the read operation module performing a read operation on the memory cell array, enabling a program operation module in the memory cell array control module after the memory receives a memory cell array program instruction, the program operation module performing a program operation on the memory cell array, and enabling an erase operation module in the memory cell array control module after the memory receives a memory cell array erase instruction, the erase operation module performing an erase operation on the memory cell array.

According to a third aspect of the present disclosure there is provided a system comprising a host controller, an interface bus, and a memory according to the first aspect, coupled to the host controller by the interface bus.

Therefore, the memory of the invention reduces the circuit size which needs to be participated when each memory array operation instruction is executed by using the read, programming and erasing operation modules which are independently arranged and can be independently enabled and disabled, thereby further reducing the overall power consumption of the memory chip.

Drawings

The foregoing and other objects, features and advantages of the disclosure will be apparent from the following more particular descriptions of exemplary embodiments of the disclosure as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout exemplary embodiments of the disclosure.

FIG. 1 shows a simplified schematic diagram of a system including a memory according to one embodiment of the invention.

Fig. 2 shows a schematic diagram of the composition of a related art memory.

Fig. 3 shows a schematic diagram of the composition of a memory according to an embodiment of the invention.

Fig. 4 shows a state switching diagram of a memory according to an embodiment of the invention.

Fig. 5 shows a timing diagram for entering a read state from a standby state according to one embodiment of the invention.

Detailed Description

Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

Various embodiments will be described in more detail with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the present disclosure, like reference numerals denote like parts throughout the various figures and embodiments of the present invention.

It is noted that the drawings are simplified schematic diagrams and are not necessarily drawn to scale. In some instances, various portions of the drawings may have been exaggerated in order to more clearly illustrate certain features of the illustrated embodiments.

It is further noted that in the following description, specific details are set forth in order to provide an understanding of the invention, however, the invention may be practiced without some of these specific details. In addition, it is noted that well-known structures and/or processes may be described only briefly or not at all in order to avoid obscuring the present disclosure with unnecessary well-known details.

It should also be noted that in some cases, it will be apparent to those skilled in the relevant art that elements (also referred to as features) associated with one embodiment described may be used alone or in combination with other elements of another embodiment unless specifically stated otherwise.

Various embodiments of the present invention will be described in detail below with reference to the accompanying drawings, and for ease of understanding, an application environment of the present invention will be described first with reference to fig. 1.

FIG. 1 shows a simplified schematic diagram of a system including a non-volatile memory according to one embodiment of the invention. The system 10 may be implemented as an electronic device, and the device 10 may include a host 200 and a memory 300 as shown and communicate via a bus 100.

Here, the host 200 refers to a portion that performs a key function of the device 10, i.e., a main portion of the device 10, and the host 200 (or the device 10) may be any suitable electronic device. In one embodiment, the apparatus 10 may be an electronic device, including but not limited to, for example, portable electronic devices such as mobile phones, tablet computers, wearable devices (e.g., TWS headphones), and laptop computers, or non-portable electronic devices such as desktop computers, gaming machines, televisions, set-top boxes, and projectors, and even industrial Internet of things devices such as independently disposed sensors. At this time, the memory 300 may be a device that provides a storage service for the independent electronic device.

In other embodiments, the apparatus 10 may also be electronic devices with relatively independent functions (these are typically key devices that make up an electronic device), such as a smart screen, a host chip, a camera assembly, etc. that are sold separately. These electronics often need to be assembled, e.g., a smart screen is assembled to a cell phone, to provide services to a consumer (e.g., a user purchasing the cell phone). At this time, the memory 300 may be a device that provides necessary storage services for the electronic device.

Here, the host 200 may be implemented as or include a microcontroller, a microprocessor, an Application Specific Integrated Circuit (ASIC), or an Application Specific Standard Product (ASSP), and is coupled to the memory 300 as a slave device via the bus 100 as shown. The bus 100 may be implemented here, for example, as a Serial Peripheral Interface (SPI) bus and includes a plurality of connection lines 101-104 as shown to enable the transfer of instructions, addresses and data to read and execute code stored in the memory 300 and to erase and write if necessary, such as for firmware over the air upgrades.

In the illustrated example, the bus 100 may include at least a data input line 101, a data output line 102, a clock line 103, and a chip gate line 104. In which data signals generated by the host 200 and received by the memory 300, which may include sequences of instructions and addresses, etc., are transmitted on the data input line 101. The data output line 102 then transmits signals generated by the memory 300 and received by the host 200, e.g., data read from the memory 300, e.g., code executable on the host 200. The clock line 103 is used to send the clock signal generated by the host 200 into the memory 300, thereby implementing the synchronous data transmission between the two parties. When data transfer is required between the host 200 and the memory 300, the chip gate signal on the chip gate line 104 is set to an active level, e.g., a low level. When the transfer of data is completed, the chip gate signal on the chip gate line 104 is set to an inactive level, for example, a high level. Although not shown, it should be understood that bus 100 may also enable connection of host 200 to other slave or peripheral devices, which may be provided with other chip strobe lines.

Host 200 and memory 300 may each include pins for making the connections as described above. In a preferred embodiment, memory 300 may be implemented as a flash memory device having an SPI interface, particularly NOR flash and NAND flash, enabling sequential access of data via a serial interface (pin) and suitable for many applications such as voice, image, program code, and data storage. In particular, the memory 300 is capable of being enabled (e.g., a prescribed valid "assert" signal) by a chip strobe signal received on a Chip Strobe (CS) pin, and is capable of enabling data access via a data input (SI) pin, a data output (SO) pin, and a Clock (CLK) pin.

The memory circuit 300 may include input-output interfaces connected to the outside, the input-output interfaces including a data input interface, a data output interface, a clock interface, and a chip strobe interface, and the input-output interfaces may be generally implemented as pins including an SI pin, an SO pin, a CLK pin, and a CS pin, wherein the SI pin corresponds to the data input interface, the SO pin corresponds to the data output interface, the CLK pin corresponds to the clock interface, and the CS pin corresponds to the chip strobe pin/interface. The pins may exchange data with the outside, for example, with a host, respectively, using the data input line 101, the data output line 102, the clock line 103, and the chip strobe line 104 included in the bus 100 shown in fig. 1, and particularly, the SPI bus, so as to implement data reading, erasing, or writing under the control of the host.

It will be appreciated that while the SI pin, SO pin, CLK pin, and CS pin are collectively referred to as input-output interfaces, in actual operation the SI pin, CLK pin, and CS pin may be designated for acquiring external signals, and the SO pin may be designated for outputting data externally, such as program code read from the memory 300, or status signals registered in registers within the memory 300, etc. Further, the SI pin, the CLK pin, and the CS pin are each used to acquire signals of different properties from the outside. Specifically, the instruction sent by the host 200 to the memory 300 may be an operator, which includes a plurality of bits (e.g., 8 bits), and SI pin sequential fetch operators. The SI pin fetched instructions are typically not directly used for control of the memory, but need to be translated into control instructions identifiable in the memory via decoding by a decoding means, e.g. via instruction decoder 331 in fig. 2. The CLK pin is used to receive a clock signal (e.g., clock pulses of a particular frequency) from the host for synchronous transfer of data, e.g., on a rising edge of the clock signal, the host 200 sends data and the memory 300 receives data. The CS pin then acquires a chip strobe signal from the host 200, which may be a strobe or an active level that lasts for a predetermined time (e.g., when the chip strobe signal is low, the memory 300 is able to receive clock and data from the host 200, when the chip strobe signal is high, the memory 300 ignores the clock and data on the clock line 103 and the data input line 101), and generally the operation inside the memory may be altered directly based on the chip strobe signal.

Fig. 2 shows a schematic diagram of the composition of a related art memory. The memory 300 includes an input-output buffer 211, a power manager 221, a voltage pump 222, an ID register 251, an instruction decoder 231, a controller 232, a memory array 241, a column decoder 242, a row decoder 243, and a readout circuit 245. The memory array 241 includes a plurality of memory cells arranged in an array and addressable by word lines and bit lines. The memory cell may be a transistor having a floating gate or an insulating layer capable of trapping charge. The memory cell further includes a substrate, a source, a drain, and a control gate. The floating gate and the substrate are separated by a tunneling insulating layer, and the floating gate and the control gate are separated by an insulating layer. The threshold voltage of a transistor is related to the amount of charge trapped in the floating gate. When more charge is trapped in the floating gate, the memory cell stores a logic 0, and when no charge is trapped in the floating gate, the memory cell stores a logic 1. The row decoder 243 is used to select a word line according to an address. Column decoder 242 is used to select bit lines according to addresses. The sensing circuit 245 is used to perform read operations and verify operations of the memory array 241. The power manager 221 is configured to power the voltage pump 222, the instruction decoder 231, the controller 232, the memory array 241, the column decoder 242, the row decoder 243, and the readout circuit 245. The ID register 251 is used to store information such as a memory ID and a manufacturer ID of the memory. The memory 300 also includes an internal clock for providing a clock signal for the operation of the memory array 241. Accordingly, the clock signal on clock line 103 may be referred to as an external clock. The charge pump 222 is used to provide a voltage for the operation of the memory array 241. The charge pump 222 may include a plurality of charge pump circuits for generating voltages required for a read operation, a program operation and an erase operation, respectively.

With further miniaturization of portable and wearable devices, and the popularity of distributed devices such as internet of things applications, it is desirable for the memory to be able to further reduce power consumption. Common memories (e.g., low power NOR flash) utilize the same controller to execute all memory array operation instructions, including read instructions, program instructions, and erase instructions. The control module is implemented as a logic control circuit including a large number of devices because of the need to have the ability to control read, program and erase operations simultaneously. When the logic control circuit is executing instruction operation, the device contained in the circuit still has a certain leakage current even if not gated, thereby causing the power consumption of the memory to become large.

To this end, the present invention proposes a memory including independently set read, program and erase operation control modules. These modules may be enabled only when the corresponding instruction is received, and disabled for other periods. Thereby reducing the amount of logic control circuitry that needs to be enabled when executing memory array operation instructions, thereby reducing the overall power consumption of the memory.

Fig. 3 shows a schematic diagram of the composition of a memory according to an embodiment of the invention. The memory 300 shown in fig. 3 includes an input-output buffer 311, a power manager 321, an operation module, an ID register 351, an instruction decoder 331, a memory array 341, a column decoder 342, a row decoder 343, and a readout circuit 345. But unlike fig. 2, in the memory shown in fig. 3, the operation modules include a read operation module, an erase operation module, and a program operation module, which are provided for a read operation, an erase operation, and a program operation, respectively, and which may function as the controller 332 and the voltage pump 322 shown in fig. 2 as a whole, for example, and may each include a control circuit portion and a voltage pump portion.

The memory array 341 includes a plurality of memory cells arranged in an array and addressable by word lines and bit lines. The row decoder 343 is used for selecting word lines according to an address. The column decoder 342 is used to select bit lines according to an address. The readout circuit 345 is used to perform read operations and verify operations of the memory array 341. Data acquired from the input-output interface may be temporarily stored in the input-output buffer 311 and further transferred to the instruction decoder 331. The data input line 101 and the data output line 102 support a serial protocol. For example, in a read operation, data received via the data input line 101 to be written into the memory array 341 is first stored in the shift register of the input-output buffer 311, and then moved to the data register. The instruction received via the data input line 101 is first stored in the shift register of the input-output buffer 311 and then supplied to the instruction decoder 331.

In some embodiments, signals taken from the SI, CLK, and CS pins may be buffered in data input buffers, clock buffers, and chip strobe signal buffers, respectively, in input-output buffer 311. Accordingly, the input/output buffer 311 may further include a data output buffer for buffering data to be output via the SO pin.

The instruction decoder 331 is configured to read an instruction signal received by the SI pin from the data input buffer of the input/output buffer 311, and decode the instruction signal into an internal instruction that can be executed by the memory. The internal command sends a control signal to the power manager 321, and the power manager 321 may supply power to the read operation module, the erase operation module, and the program operation module in response to the control signal.

Although not shown in the drawings, the memory 300 may include a power interface for receiving an external power source, such as a pin receiving an external voltage VCC (e.g., a first voltage), which is obtained from, for example, a power supply device of a system (e.g., the electronic apparatus 10), and further, the memory 300 may further include a pin connected to a system ground. The input-output interface of the memory 300 may typically operate directly at an external voltage VCC, while the operating block, the command decoder 331, the memory array 341, the column decoder 342, the row decoder 343, the sense circuit 345, etc. typically operate at a voltage different from VCC (i.e., the operating voltage VDD of the memory, e.g., the second voltage), and VDD is typically lower than VCC, thus requiring the power manager 321 to provide the operating voltage VDD to the components in the memory. In other embodiments, the external voltage VCC may be the same as the memory operating voltage VDD. The power manager 321 may be used to power the various components operating at the VDD voltage.

As shown in fig. 3, the read operation module may perform a read operation on the memory cell array (the memory module in fig. 3) based on the memory cell array read instruction, for example, with the help of the column decoder 342, the row decoder 343, and the readout circuit 345 of the memory module, to achieve data readout from a designated location of the memory array 341.

The read operation module may include a read control circuit 3321 and a read voltage pump 3221. The read control circuit 3321 may be used to control data read operations of the memory cell array. Specifically, in a read operation, when a voltage is applied, when the application is stopped, and timing of the voltage need enable signal control. For this purpose, the read control circuit 3321 may include a read operation enable signal circuit for enabling control of voltages used in the read operation, i.e., providing these enable signals. Further, the read control circuit 3321 includes a state machine that implements logic control for the various steps of the read operation. Further, in the read operation, parameters such as the data read rate are also required to be configured. To this end, the read control circuit 3321 may also include a read operation parameter selection circuit for parameter configuration of the read operation.

The read voltage pump 3221 may then be used to generate the voltages that need to be used in a read operation. For example, the read voltage pump 3221 may generate a read voltage applied to a selected word line, a turn-on voltage applied to a non-selected word line (for NAND flash memory), or a negative voltage (for NOR flash memory).

The program operation module may perform a program operation on the memory cell array (the memory module in fig. 3) based on the memory cell array program instruction, for example, with the help of the column decoder 342 and the row decoder 343 of the memory module, to implement data writing to a designated location of the memory array 341.

The program operation module may include a program control circuit 3322 and a program voltage pump 3222. The program control circuit 3322 may be used to control data write operations of the memory cell array. Specifically, in the programming operation, the magnitude and timing of the applied voltage also need to be controlled by the enable signal. To this end, the program control circuit 3322 may include a program operation enable signal circuit for enabling control of voltages used in the program operation. Further, the program control circuit 3322 also includes a state machine that implements logic control for each step of the programming operation. Further, in the programming operation, parameters such as programming several bytes at a time may also be configured. The program control circuit 3322 may also include a program operation parameter selection circuit for parameter configuration of the program operation.

The programming voltage pump 3222 may then be used to generate the voltages that need to be used in the programming operation. More specifically, programming a memory cell also involves the participation of multiple voltages. For example, in a NOR flash programming operation, a word line programming voltage is applied to a selected word line and a bit line programming voltage is applied to a selected bit line, thereby achieving a 0 write of a target memory cell. In a programming operation of the NAND flash memory, a program voltage is applied to a word line (selected word line) corresponding to a target page, that is, a positive voltage (e.g., 20V) is applied to control gates of all transistors of the page, and a program on voltage is applied to unselected word lines. Accordingly, according to the distributions of the target data 0 and 1, a program enable voltage (e.g., a ground voltage) and a program inhibit voltage (e.g., a positive voltage of 2.5V) are applied to the selected bit line and the unselected bit line, respectively. After the programming enable voltage is applied to the bit line corresponding to the memory cell, electrons enter the floating gate through the insulating layer under the attraction of the positive voltage applied to the control gate, and the writing of the memory cell 0 is completed. In both NOR and NAND implementations, the program voltage pump 3222 may be used only to generate word line program voltages, bit line program voltages, program on voltages, program inhibit voltages. In some embodiments, the programming operation further includes a verify sub-operation after the programming voltage applying step, e.g., reading the programmed memory cells to verify that the data is properly stored. In this case, read charge pump 3221 is also called to generate the voltages required on the selected word line and the unselected word lines, thereby completing the verify sub-operations involved in the programming operation.

The operation module further includes an erase operation module, which can perform an erase operation on the memory cell array based on the memory cell array erase command, for example, with the help of the column decoder 342 and the row decoder 343 of the memory module, to erase data at a designated location of the memory array 341.

The erase operation module may include an erase control circuit 3323 and an erase voltage pump 3223. The erase control circuit 3323 may be used to control a data erase operation of the memory cell array. In particular, the selection of the magnitude and application time of the erase voltage and the setting of the relevant parameters are likewise involved in the erase operation. For this purpose, the erase control circuit 3323 may include an erase operation enable signal circuit for enabling control of a voltage used in an erase operation, and an erase operation parameter selection circuit for parameter configuration of the erase operation. Further, the erase control circuit 3323 also includes a state machine that implements logic control for each step of the erase operation.

The erase voltage pump 3223 may then be used to generate the voltages that need to be used in an erase operation. For example, for a NAND flash memory, the erase voltage pump 3223 is used to generate a positive voltage up to 20V applied to the substrate, and for a NOR flash memory, the erase voltage pump 3223 includes a positive voltage pump for generating a positive voltage applied to the substrate and a negative voltage pump for generating a negative voltage applied to the word line. In some embodiments, the erase operation further includes a verify sub-operation after the erase voltage applying step, for example, reading the erased memory cells to verify whether the memory cells are in an erased state. In this case, read charge pump 3221 is also called to generate the voltages required on the selected word line and the unselected word lines, thereby completing the verify sub-operations involved in the programming operation. Further, in some NOR flash implementations, the erase operation also needs to verify whether the memory cell is over-erased, i.e., whether the threshold voltage of the memory cell is less than 0, and if the threshold voltage of the memory cell is less than 0, the threshold voltage needs to be raised to be greater than 0 by soft programming. For this reason, soft programming sub-operations may also be included in the erase operation of the NOR flash memory. At this time, the program charge pump 3222 also needs to be invoked to generate a desired voltage, such as a word line program voltage.

The read control circuit 3321, the program control circuit 3322, and the erase control circuit 3323 shown in fig. 3 can realize the same functions as the controller shown in fig. 2, and the read voltage pump 3221, the program voltage pump 3222, and the erase voltage pump 3223 can realize the same functions as the charge pump shown in fig. 2, but are different in that the above-described circuits/voltage pumps are each independently provided, in other words, they may not be simultaneously enabled. Thus, the memory can only enable the corresponding module to operate according to the specific instruction received from the outside, and leakage current caused by enabling unnecessary circuits is avoided, thereby reducing the power consumption level of the memory chip.

It is to be appreciated that the read control circuit 3321, program control circuit 3322, and erase control circuit 3323 may be general purpose processors, DSP, ASIC, FPGA or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

Fig. 4 shows a state switching diagram of a memory according to an embodiment of the invention. As shown, the operating states of the memory 300 may include a standby state (standby), a low power consumption state (PWD), and three respective independent active states, a READ state (READ), a program state (PGM), and an ERASE state (ERASE).

The following table lists the enabling and disabling situations for various states for the various components in memory 300.

TABLE 1

"Enable" refers to a component being in a state that allows use. "disabled" refers to a component being in a state that does not allow use. For example, the component is placed in a state where use is permitted by supplying power, and the component is placed in a state where use is not permitted by stopping the power supply.

In the standby state, the memory 300 can recognize any instruction of the host 200. In the standby state, if there is no data transfer between the host 200 and the memory 300, the chip strobe signal is maintained at an inactive level. Compared with the prior art, the memory of the invention has fewer modules which are enabled in the standby state, and the voltage pump and the control circuit (such as the read, program and erase control modules shown in fig. 3) can be in the disabled state, so that only the power supply of the instruction decoder, the input-output buffer and the ID register is reserved. Some instructions that do not require memory array involvement, such as READID instructions for retrieving information from an ID register, may be executed directly in standby.

When the memory further receives an operation instruction for the memory cell array in the standby state, a corresponding READ state (READ), program state (PGM), and ERASE state (ERASE) may be entered according to the type of the received instruction.

When the host 200 needs to transmit an operation instruction of the memory cell array to the memory 300, the host 200 sets a chip strobe signal to an active level, the memory 300 receives the instruction or data through a data input line SI and sets a busy signal to be active, and according to a decoding result of the instruction decoder 331, the power manager 321 enables a corresponding operation module, thereby entering one of a READ state (READ), a program state (PGM) and an ERASE state (ERASE).

The various states and state transitions involved in the memory of the present invention will be described below in conjunction with fig. 3-4, and subsequent state transition timing diagrams.

As previously shown in connection with table 1, in the standby state, the read operation module (read control circuit 3321 and read charge pump 3221), the program operation module (program control circuit 3322 and program charge pump 3222), and the erase operation module (erase control circuit 3323 and erase charge pump 3223) are all disabled.

In the standby state, when the chip strobe signal is active (e.g., pulled low) and an instruction for the memory cell array is received on the data input pin, the memory may enter a corresponding operating state from the standby state to perform an operation for the memory cell array.

Fig. 5 shows a timing diagram for entering a read state from a standby state according to one embodiment of the invention. First, a low level chip strobe signal is received on the CS pin of the memory and then an 8 bit input command is received on the SI pin. The instruction is buffered by the input/output buffer 311 and then sent to the instruction decoder 331. The instruction decoder 331 then decodes the received 8-bit instruction, recognizes that the input instruction is a read_cmd for performing a read operation of the memory cell array, and sends the recognition result to the power manager 321. The power manager 321 decides to enable the memory module, the read control circuit 3321, and the read charge pump 3221 based on the identification result and supplies power thereto. As shown in fig. 5, after the processing time of t _R has elapsed, the read control circuit 3321 and the read charge pump 3221 enter an operable state, whereby the memory enters a read state, and the current flowing into the memory changes from I _CC1 in the standby state to I _CC3 in the read state. Subsequently, the read control circuit 3321 and the read charge pump 3221 control the memory array 341, the column decoder 342, the row decoder 343 and the readout circuit 345 to perform corresponding operations according to the above-described read instruction (and the subsequent related instructions, if any), thereby realizing the reading of the target memory contents. After completion of execution of the above instruction, the memory returns to standby mode, the read control circuit 3321 and read charge pump 3221 are disabled again, and current also drops from I _CC3 back to I _CC1.

Similarly, after the memory receives the memory cell array programming instruction, the program operation module (program control circuit 3322 and program charge pump 3222) is enabled under the control of the power manager 321 based on the decoding identification result, whereby the memory enters a programmed state, and the current flowing into the memory changes from I _CC1 in a standby state to I _CC4 in a programmed state. The enabled program control circuit 3322 and program charge pump 3222 are used to perform programming operations on the array of memory cells. As previously described, the programming operation may involve a verify sub-operation. In this verify sub-operation, the read voltage pump 3221 may be enabled alone for generating the corresponding voltage. Thus in table 1, the read voltage pump 3221 is shown enabled in a programmed state. The above-described enabling may be the enabling in the entire programming operation, but is preferably only the enabling in the corresponding verify sub-operation. After all programming operations are completed, the memory returns to standby mode and the programming control circuit 3322 and programming charge pump 3222 (and optionally the enabled read voltage pump 3221) are re-disabled.

The erase operation module (the erase control circuit 3323 and the erase charge pump 3223) is enabled under the control of the power manager 321 based on the decoding identification result after the memory receives the memory cell array erase instruction, whereby the memory enters an erased state, and the current flowing into the memory changes from I _CC1 in a standby state to I _CC5 in an erased state. The enabled erase control circuit 3323 and erase charge pump 3223 are used to perform erase operations on the memory cell array. As previously described, the erase operation may involve a verify sub-operation. In this verify sub-operation, the read voltage pump 3221 may be enabled alone for generating the corresponding voltage. Further, in an application scenario of the NOR flash memory, the erase operation may involve a soft programming sub-operation. In this soft programming sub-operation, the programming voltage pump 3222 may be enabled alone for generating the corresponding voltage. Thus in table 1, read voltage pump 3221 and program voltage pump 3222 are shown enabled in an erased state. The above-described enabling may be enabling in the entire erase operation, but is preferably only enabling in various corresponding verify sub-operations and soft program sub-operations. After all erase operations are completed, the memory returns to standby mode and the erase control circuit 3323 and erase charge pump 3223 (and optionally the enabled read voltage pump 3221 and program voltage pump 3222) are re-disabled.

Further, as shown in FIG. 4, in the standby state, the memory 300 can directly enter the low power state according to the low power state instruction PWD_cmd. In a low power state, the power manager 321 may disable the memory modules, i.e., the memory array 341, the column decoder 342, the row decoder 343, and the sense circuits 345 (and page buffers, etc., in some embodiments), thereby reducing the power consumption of the memory chip and the current flowing into the memory changes from I _CC1 in the standby state to a lower I _CC2 in the low power state.

After transition to the low power state, any signal on the SI pin is ignored. When a valid chip strobe signal is received on the CS pin, such as when a low level valid signal is received (i.e., CS is pulled low), the memory in the low power state may react to the chip strobe signal, thereby causing the memory to leave the low power state and return to the standby state.

While each of the operational modules is shown in fig. 3 as including both control circuitry and a voltage pump, it should be understood that in some embodiments, only the logic control circuitry may be partitioned while still using a combined charge pump, e.g., the read operational module includes only the read control circuitry and no separate read charge pump, and such variations remain within the scope of the present invention.

The invention can also be realized as a memory control method, which comprises enabling a read operation module in a memory cell array operation module after the memory receives a memory cell array read instruction, enabling a program operation module in the memory cell array control module after the memory receives a memory cell array program instruction, enabling a program operation module in the memory cell array control module to perform program operation on the memory cell array, and enabling an erase operation module in the memory cell array control module after the memory receives a memory cell array erase instruction, wherein the erase operation module performs erase operation on the memory cell array.

Further, the present invention may also be implemented as a system, such as the electronic device shown in fig. 1, including a host, an interface bus, and a memory as described above. The memory is coupled to the host through its input-output interface (e.g., SPI interface) to the interface bus described above.

The memory, the memory control method and the system according to the present invention have been described in detail above with reference to the accompanying drawings.

The present disclosure updates the internal structure of a memory circuit (especially a flash memory chip) from the viewpoint of reducing power consumption, and divides a control circuit based on instruction types. For different instructions, only specific circuits required for completing the instructions are started, other operation circuits are disabled, unnecessary circuit starting of a memory operation device is avoided, and memory leakage current and power consumption in a working state are reduced. Further, the detailed division of the active state avoids the need for turning on the charge pump and the control circuit in the standby state, thereby further reducing standby power consumption and increasing battery life.

The foregoing description of embodiments of the invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A memory, comprising:

Memory cell array, and

A memory cell array operation module, the operation module comprising:

A read operation module enabled in response to the memory receiving a memory cell array read instruction and for performing a read operation on the memory cell array;

a program operation module enabled in response to the memory receiving a memory cell array program instruction and for performing a program operation on the memory cell array, and

An erase operation module enabled in response to the memory receiving a memory cell array erase instruction and configured to perform an erase operation on the memory cell array,

Wherein disabling the read operation module is completed in response to the read operation execution,

Disabling the program operation module in response to the program operation execution completion, and

And completing disabling of the erase operation module in response to the erase operation execution.

2. The memory of claim 1, wherein the read operation module comprises:

A read voltage pump for generating a voltage required for use in a read operation, and

And the read control circuit is used for controlling the data reading operation of the memory cell array.

3. The memory of claim 2, wherein the read control circuit comprises:

And a read operation enable signal circuit for enabling control of a voltage used in the read operation.

4. The memory of claim 2, wherein the read voltage pump is enabled in a verify sub-operation of an erase operation and/or a program operation.

5. The memory of claim 1, wherein the programming operation module comprises:

a programming voltage pump for generating a voltage required for a programming operation, and

And the programming control circuit is used for controlling the data programming operation of the memory cell array.

6. The memory of claim 5, wherein the program voltage pump is enabled in a soft programming sub-operation of an erase operation.

7. The memory of claim 1, wherein the erase operation module comprises:

An erase voltage pump for generating a voltage required for an erase operation, and

And the erasure control circuit is used for controlling the data erasure operation of the memory cell array.

8. The memory of claim 1, further comprising:

Power manager

The instruction decoder is configured to decode the instruction,

9. The memory of claim 8, wherein the power manager is to:

in response to receiving a low power state instruction, stopping power to the instruction decoder to enter a low power state, and

And in response to receiving a chip strobe signal, restoring power to the instruction decoder to return to the standby state.

10. A memory control method, comprising:

enabling a read operation module in a memory cell array operation module after the memory receives a memory cell array read instruction, wherein the read operation module performs read operation on the memory cell array;

Enabling a programming operation module in the memory cell array control module after the memory receives a memory cell array programming instruction, the programming operation module performing a programming operation on the memory cell array, and

Enabling an erase operation module in the memory cell array control module after the memory receives a memory cell array erase command, the erase operation module performing an erase operation on the memory cell array,

And the method further comprises:

Disabling the read operation module in response to the read operation execution completion,

11. A system, comprising:

A host controller;

Interface bus, and

The memory of claims 1-9, coupled to a host controller through the interface bus.