CN114138340A - A method, device and medium for realizing extended instructions of RISC-V processor - Google Patents
A method, device and medium for realizing extended instructions of RISC-V processor Download PDFInfo
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- CN114138340A CN114138340A CN202111401769.0A CN202111401769A CN114138340A CN 114138340 A CN114138340 A CN 114138340A CN 202111401769 A CN202111401769 A CN 202111401769A CN 114138340 A CN114138340 A CN 114138340A
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Abstract
A method of implementing RISC-V processor expand instructions, comprising: marking the instruction according to the type of the instruction and/or the type of the used register; the instructions are allocated to different pipeline executions based on the tags. By the method provided by the invention, the modular expansion of the user-defined instruction decoding unit and the execution unit is realized in the analysis of the instruction, so that the instruction expansion and optimization are facilitated; the method has the advantages that the instructions are tracked and processed according to the register type separation, so that the processing of various instructions is relatively independent, the method is convenient and fast, meanwhile, the occupied influence of the instructions with longer execution time on a pipeline is reduced, and the instruction execution efficiency is improved.
Description
Technical Field
The invention relates to a method, equipment and medium for realizing RISC-V processor extended instruction.
Background
RISC-V, the new instruction set that establishes on instruction constantly develops and ripe basis, has possessed the after-developed advantage, and the structure is clear and simple, and modular design can arrange as required at will, and is nimble convenient, and expansibility is strong, possesses complete tool chain to because the opening of its BSD agreement, more and more countries and enterprises put into the research in RISC-V field, and RISC-V instruction set based processor design is also more and more.
RISC-V is currently based on the basic instruction set, with extended instructions being developed and specified. RISC-V provides the interface of the self-defining instruction extension, the present instruction extension mode is more, it realizes mostly following the traditional instruction processing assembly line, for the instruction extension application of different grade type, it is deficient in flexibility and execution efficiency to a certain extent.
Therefore, a need exists for a method of addressing the problem of extended instructions implemented by customization that block pipeline execution due to long processing times.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method for implementing an extended instruction of a RISC-V processor, comprising:
marking the instruction according to the type of the instruction and/or the type of the used register;
the instructions are allocated to different pipeline executions based on the tags.
In some embodiments of the invention, marking the instruction according to the type of the instruction and/or the type of register used comprises:
marking the instruction with the instruction type of an extended instruction and a used register of a general register as a first extended instruction, and setting the value of a first preset position of the first extended instruction as a first preset value;
the instruction of which the instruction type is an extended instruction and the used register is an extended register is marked as a second extended instruction, and the value of the first preset position of the second extended instruction is set as a second preset value.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tags comprises:
assigning the first extended instruction and the generic instruction to a first Scoreboard, the first Scoreboard sending the first extended instruction and the generic instruction to a first transmitter;
assigning the second extended instruction to a second Scoreboard, the second Scoreboard sending the second extended instruction to a second transmitter.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
the first transmitter sends a first extended instruction to the second transmitter.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
in response to the second transmitter receiving a first extended instruction sent by the first transmitter and/or a second Scoreboard, determining whether a register used by the first extended instruction is occupied;
sending the first extended instruction to the second Scoreboard in response to the register used by the first extended instruction being occupied.
In some embodiments of the present invention, marking the instruction according to the type of the instruction and/or the type of register used further comprises:
counting and recording the sequence of the first extended instruction in a pipeline, and writing the sequence of the first extended instruction into a second preset position of the first extended instruction; and
in response to the second extended instruction being resolved, writing a final value of the order of the first extended instruction into a second predetermined position of the second extended instruction, and clearing the order of the first extended instruction.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
the second transmitter records the value of a second preset position of the transmitted first extended instruction through a shift register;
in response to the second transmitter receiving a second extended instruction, the second transmitter comparing a value of a second predetermined location of the second extended instruction with a value in the shift register;
in response to the value of the second predetermined position of the second extended instruction being less than the value of the shift register, shifting the second extended instruction to read the value of the next shift register or to wait for a new shift register.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
the second transmitter records the value of a second preset position of the transmitted first extension instruction in a cumulative manner through corresponding positions of a queue;
in response to the second transmitter receiving a second spread instruction, the second transmitter comparing a factorization of a value of a second predetermined location of the second spread instruction to a value of a corresponding location in the queue;
in response to the factoring of the value of the second predetermined position of the second extended instruction being greater than the value of the corresponding position of the queue, shifting the second extended instruction to read a next value of the shift register or to wait for a new value of the shift register.
In another aspect, the present invention further provides a processor, wherein hardware logic in the processor implements the steps of the method in any one of the above embodiments.
In yet another aspect, the present invention further provides a computer, which has the processor described in the foregoing embodiment, and the hardware logic of the processor implements the steps of the method described in any one of the foregoing embodiments.
By the method provided by the invention, the modular expansion of the user-defined instruction decoding unit and the execution unit is realized in the analysis of the instruction, so that the instruction expansion and optimization are facilitated; the method has the advantages that the instructions are tracked and processed according to the register type separation, so that the processing of various instructions is relatively independent, the method is convenient and fast, meanwhile, the occupied influence of the instructions with longer execution time on a pipeline is reduced, and the instruction execution efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flowchart of a method for implementing an embodiment of a method for expanding instructions for a RISC-V processor according to the present invention;
FIG. 2 is a diagram illustrating an extended instruction structure of an embodiment of a method for implementing an extended instruction of a RISC-V processor according to the present invention;
FIG. 3 is a block diagram of a processor with a method for implementing RISC-V processor extended instructions according to an embodiment of the present invention;
FIG. 4 is a block diagram of a computer with a processor implementing a method for expanding instructions for a RISC-V processor according to an embodiment of the present invention;
FIG. 5 is a block diagram of the hardware logic structure of an embodiment of the method for implementing an extended instruction of a RISC-V processor according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
As shown in fig. 1, a first aspect of the embodiment of the present invention provides a method for implementing an extended instruction of a RISC-V processor, including:
step S1, marking the instruction according to the type of the instruction and/or the register type used;
step S2, assigning the instruction to different pipeline execution based on the tag.
In the embodiment of the invention, the method for realizing the expanded instruction of the RISC-V processor, which is provided by the invention, solves the blocking of other instructions in the execution process of the expanded instruction in the RISC-V processor by implanting a special mark into the special position of the expanded instruction in the RISC-V and distributing the expanded instruction to different pipelines for execution according to the special mark.
Specifically, in step S1, the present invention tags the instruction on the pipeline of the processor according to the type of the instruction and the register type for distinguishing the extended instruction from the general-purpose instruction. Specifically, the expansion instruction is marked by self-definition, the expansion instruction of the RISC-V is 32 bits generally, and the invention expands the idle bit in the 32 bits to realize the self-defining function.
In step S2, corresponding processing logic is executed according to the above-described implementation, with the value of the corresponding bit in the 32bit of the RISC-V instruction as the determination condition.
In some embodiments of the invention, marking the instruction according to the type of the instruction and/or the type of register used comprises:
marking the instruction with the instruction type of an extended instruction and a used register of a general register as a first extended instruction, and setting the value of a first preset position of the first extended instruction as a first preset value;
the instruction of which the instruction type is an extended instruction and the used register is an extended register is marked as a second extended instruction, and the value of the first preset position of the second extended instruction is set as a second preset value.
In this embodiment, as shown in fig. 2, fig. 2 shows a structure of a decoder for decoding output information of an extended instruction according to an implementation manner of RISC-V instruction extension, in the structure content shown in fig. 2, a reg _ flags field is newly added in the present invention, the reg _ flags field corresponds to a 3-bit space of an extended instruction of RISC-V, the 3-bit respectively corresponds to register types of three registers rs1, rs2 and rd of the RISC-V extended instruction, when a used register in the three registers is an extended register, the corresponding position is 1, and an extended instruction in which the three registers are general registers is named as a KG-type instruction, that is, the KG-type instruction is also an extended instruction, and only the used register type is a general register; the corresponding position of the instruction containing the extension register in the three register types is set to be 0, and the instruction is named as a KK type instruction, namely the KK type instruction represents an extension instruction using the extension register.
It should be noted that the extended registers in the present invention are meant to include vector registers or other custom non-standard registers, as well as registers other than general purpose registers that are used to distinguish standards according to design requirements.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tags comprises:
assigning the first extended instruction and the generic instruction to a first Scoreboard, the first Scoreboard sending the first extended instruction and the generic instruction to a first transmitter;
assigning the second extended instruction to a second Scoreboard, the second Scoreboard sending the second extended instruction to a second transmitter.
As shown in fig. 5, in this embodiment, two scoreboards are provided, and when the decoder implemented according to the method of the present invention decodes the instruction, the decoder sends the KG-type instruction and the generic instruction to the first Scoreboard, and sends the KK-type instruction to the second Scoreboard. The first emitter exclusive to the first Scoreboard, the KG type instruction in the first Scoreboard and the general instruction are sent to the first emitter in the order of the instructions in the pipeline. The second Scoreboard also has an exclusive second transmitter, and the KK instructions in the second Scoreboard also send the KK instructions to the second transmitter in the order of the instructions in the pipeline.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
the first transmitter sends a first extended instruction to the second transmitter.
In this embodiment, the first transmitter further processes the KG instruction sent from the first Scoreboard, that is, by determining the type of the instruction sent by the first Scoreboard, the KG-type extended instruction is forwarded to the second transmitter for execution, and the first transmitter only transmits the general instruction.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
in response to the second transmitter receiving a first extended instruction sent by the first transmitter and/or a second Scoreboard, determining whether a register used by the first extended instruction is occupied;
sending the first extended instruction to the second Scoreboard in response to the register used by the first extended instruction being occupied.
In this embodiment, the second transmitter reads the address of the register of the KG-type instruction received from the first transmitter, i.e. determines whether the register used by the KG-type instruction is occupied according to the values of rs1, rs2 and rd in fig. 2, and if the register is occupied, the KG-type instruction is transmitted to the second Scoreboard and classified before the corresponding KK instruction.
It should be noted that the expansion instructions KG and KK in the present invention are usually grouped, that is, the KG type instruction is followed by the KK type instruction, and the KG type instruction is usually a pre-execution instruction for executing the KK type instruction. That is, the second Scoreboard implements the corresponding logic to associate the matched set of KG and KK type instructions.
In some embodiments of the present invention, marking the instruction according to the type of the instruction and/or the type of register used further comprises:
counting and recording the sequence of the first extended instruction in a pipeline, and writing the sequence of the first extended instruction into a second preset position of the first extended instruction; and
in response to the second extended instruction being resolved, writing a final value of the order of the first extended instruction into a second predetermined position of the second extended instruction, and clearing the order of the first extended instruction.
In this embodiment, as shown in fig. 2, a set _ num flag is set in 32 bits of an instruction of the RISC-V processor to flag the packet matching of the KG-type instruction and the KK-type instruction, and in the above, the KG-type instruction and the KK-type instruction are matched and associated in the second Scoreboard. If the KK instruction is resolved, the value of the counter register is written to the bit corresponding to set _ num of the KK instruction, and the counter register is set to 0, that is, started from 0.
Specifically, taking 3 KG-type instructions and 1 KK-type instruction as an example, the order of the instructions input to the processor is KG1, KG2, KG3, KK, after the first KG-type instruction is resolved, the value of the count register is incremented by 1, and the value of the count register is written into the set _ num of the first KG-type instruction, that is, the set _ num of KG1 is set to 1; when the second KG-type instruction is resolved, the value of the count register is incremented by 1 again, and the value of the count register is written into the set _ num flag of the second KG-type instruction KG2 again, that is, the set _ num value of KG2 is 2, and so on, the set _ num value of KG3 is 3; when the KK instruction is resolved, the value of the count register is written into the set _ num flag of the KK instruction and the count register is cleared, that is, the set _ num value of the KK instruction is also 3, and the value of the count register is set to 0. When the KG type instruction is encountered, the above-mentioned procedure is followed.
In addition, as previously described, KG type commands are sent to a first Scoreboard, while KK type commands are sent to a second Scoreboard. And the KG type instruction sent to the first Scoreboard is forwarded to the second transmitter through the first transmitter, if the second transmitter cannot transmit because the relevant register is occupied, the KG type instruction is sent to the second Scoreboard, after the KG type instruction is sent to the second Scoreboard, the second Scoreboard matches the KG type instruction and the KK type instruction in the same group, and when the KG type instruction is transmitted by the second transmitter, the set _ num value of the transmitted instruction is sent to the Scoreboard. Since the order of the KK type instructions and the KG type instructions at the time of decoding has been determined, the KG type instructions and the KK type instructions can be matched in the order of the instructions when the set _ num value of the KG type instructions transmitted by the second transmitter and the KG type instructions which cannot be transmitted are received.
Specifically, taking two groups of KG and KK type instructions as an example, for example, the first group of KG and KK type instructions has two KG type instructions and 1 KK type instruction, and assuming that the registers of the first KG type instruction and the second KG type instruction are not occupied, the first KG type instruction and the second KG type instruction are directly transmitted, the second transmitter transmits two set _ num values, i.e. 1 and 2, to the second Scoreboard in sequence, and the KK type instruction of the first group is also 2, it is considered that KG1 and KG2 of the KK type instruction have been transmitted and executed, and if the KK instruction can be transmitted, the KK type instruction is directly transmitted to the execution unit for execution. If the transmission is not possible, the waiting is continued, if in the process, the second group of 3 KG type instructions are simultaneously sent to the second transmitter, and KG1 and KG2 of the second group of KG type instructions cannot be sent due to register occupation and are forwarded to the second Scoreboard, in this case, when the Scoreboard processes the two KG instructions, the Scoreboard marks the corresponding KK type instructions in the second Scoreboard through the set _ num value, and if the set _ num value is smaller than the set _ num value of the corresponding KK type instructions, the two KG type instructions are matched with the corresponding KK type instructions. Thus, since the first set of KG and KK-type instructions have been authenticated, no comparison is made with the value of set _ num for the first set of KK-type instructions, even if KG1 of the second set is less than the value of set _ num for the first set of KK. This allows for a clear instruction issue sequence.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
the second transmitter records the value of a second preset position of the transmitted first extended instruction through a shift register;
in response to the second transmitter receiving a second extended instruction, the second transmitter comparing a value of a second predetermined location of the second extended instruction with a value in the shift register;
in response to the value of the second predetermined position of the second extended instruction being less than the value of the shift register, shifting the second extended instruction to read the value of the next shift register or to wait for a new shift register.
In this embodiment, when the second transmitter transmits the KK instruction in the second Scoreboard, the value of set _ num of the transmitted KG instruction needs to be stored by the shift register. As in the case of the KG and KK type instructions in the above example, if KG1 issues, the value 1 of set _ num of KG1 is written into the shift register, if the second KG type instruction KG2 cannot issue because of the register, the entire second transmitter blocks the execution of the KK type instruction waiting for the current processor (only the KK type extension instruction will use the extension register, and therefore it is common that the KK type instruction will affect the subsequent issue of the KG type instruction when executed), whereas when the KK type instruction issues, in order to prevent an issue error, it is necessary to verify whether all of the KG type instructions issue, and therefore, by comparing the value of set _ num of the KK type instruction with the value in the current shift register, that is, comparing the value of set _ num of the issued KG type instruction with the value of set _ num of the issued KK type instruction, if the value of the shift register is smaller than the value of set _ num of the KK type instruction, it is not declared that the issue of the KG type instruction is completed, and at the moment, the KK type instruction is blocked and waits, the second transmitter transmits the corresponding KG type instruction, the set _ num value of the transmitted KG type instruction is recorded to the shift register, whether the set _ num value of the KK type instruction to be transmitted is equal to the value of the shift register is judged, the KK type instruction is transmitted if the set _ num value of the KK type instruction to be transmitted is equal to the value of the shift register, and the KK type instruction is continuously blocked and waits for transmitting the KG type instruction if the set _ num value of the KK type instruction to be transmitted is not equal to the value of the shift register.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
the second transmitter records the value of a second preset position of the transmitted first extension instruction in a cumulative manner through corresponding positions of a queue;
in response to the second transmitter receiving a second spread instruction, the second transmitter comparing a factorization of a value of a second predetermined location of the second spread instruction to a value of a corresponding location in the queue;
in response to the factoring of the value of the second predetermined position of the second extended instruction being greater than the value of the corresponding position of the queue, shifting the second extended instruction to read a next value of the shift register or to wait for a new value of the shift register.
In this embodiment, the present invention provides a solution for out-of-order transmission of KG-type instructions, wherein the above-mentioned set _ num flag is also used for performing the determination, and different from the above-mentioned implementation manner, the shift register is replaced with a storage structure of another queue type, when a group of KG and KK type instructions are transmitted, set _ num of the transmitted KG-type instructions in the same group is written into a position of a corresponding sequence of the queue in a multiplicative manner, when the KK type instructions are transmitted, the value of the multiplicative of the KK type instructions set _ num is calculated and compared with the cumulative value of the transmitted KG-type instructions in the corresponding sequence position in the queue, if the multiplicative of the KK type instructions is smaller than the cumulative value of the transmitted KG-type instructions, it is determined that the KG-type instructions are not completely transmitted, the KK type instructions need to be continuously transmitted, and if the two are equal, the KK type instructions can be directly transmitted. Through this mechanism, can realize the out-of-order transmission of KG type instruction, also as long as the extension register that KG type instruction used does not occupy, the second transmitter can directly transmit the KG type instruction that first transmitter forwarded, need not to block the waiting through shift register, the all-round period that the waiting emission of KG type instruction was wasted that can significantly reduce.
By the method provided by the invention, the modular expansion of the user-defined instruction decoding unit and the execution unit is realized in the analysis of the instruction, so that the instruction expansion and optimization are facilitated; the method has the advantages that the instructions are tracked and processed according to the register type separation, so that the processing of various instructions is relatively independent, the method is convenient and fast, meanwhile, the occupied influence of the instructions with longer execution time on a pipeline is reduced, and the instruction execution efficiency is improved.
As shown in FIG. 3, another aspect of the present invention also provides a processor 21, wherein hardware logic 22 implements a method for implementing RISC-V processor extended instructions, comprising:
marking the instruction according to the type of the instruction and/or the type of the used register;
the instructions are allocated to different pipeline executions based on the tags.
In some embodiments of the invention, marking the instruction according to the type of the instruction and/or the type of register used comprises:
marking the instruction with the instruction type of an extended instruction and a used register of a general register as a first extended instruction, and setting the value of a first preset position of the first extended instruction as a first preset value;
the instruction of which the instruction type is an extended instruction and the used register is an extended register is marked as a second extended instruction, and the value of the first preset position of the second extended instruction is set as a second preset value.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tags comprises:
assigning the first extended instruction and the generic instruction to a first Scoreboard, the first Scoreboard sending the first extended instruction and the generic instruction to a first transmitter;
assigning the second extended instruction to a second Scoreboard, the second Scoreboard sending the second extended instruction to a second transmitter.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
the first transmitter sends a first extended instruction to the second transmitter.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
in response to the second transmitter receiving a first extended instruction sent by the first transmitter and/or a second Scoreboard, determining whether a register used by the first extended instruction is occupied;
sending the first extended instruction to the second Scoreboard in response to the register used by the first extended instruction being occupied.
In some embodiments of the present invention, marking the instruction according to the type of the instruction and/or the type of register used further comprises:
counting and recording the sequence of the first extended instruction in a pipeline, and writing the sequence of the first extended instruction into a second preset position of the first extended instruction; and
in response to the second extended instruction being resolved, writing a final value of the order of the first extended instruction into a second predetermined position of the second extended instruction, and clearing the order of the first extended instruction.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
the second transmitter records the value of a second preset position of the transmitted first extended instruction through a shift register;
in response to the second transmitter receiving a second extended instruction, the second transmitter comparing a value of a second predetermined location of the second extended instruction with a value in the shift register;
in response to the value of the second predetermined position of the second extended instruction being less than the value of the shift register, shifting the second extended instruction to read the value of the next shift register or to wait for a new shift register.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
the second transmitter records the value of a second preset position of the transmitted first extension instruction in a cumulative manner through corresponding positions of a queue;
in response to the second transmitter receiving a second spread instruction, the second transmitter comparing a factorization of a value of a second predetermined location of the second spread instruction to a value of a corresponding location in the queue;
in response to the factoring of the value of the second predetermined position of the second extended instruction being greater than the value of the corresponding position of the queue, shifting the second extended instruction to read a next value of the shift register or to wait for a new value of the shift register.
As shown in fig. 4, a further aspect of the present invention further provides a computer 31, where the computer 41 is provided with the processor 42 described in the foregoing embodiment, and the processor implements a method for implementing an extended instruction of a RISC-V processor, including:
marking the instruction according to the type of the instruction and/or the type of the used register;
the instructions are allocated to different pipeline executions based on the tags.
In some embodiments of the invention, marking the instruction according to the type of the instruction and/or the type of register used comprises:
marking the instruction with the instruction type of an extended instruction and a used register of a general register as a first extended instruction, and setting the value of a first preset position of the first extended instruction as a first preset value;
the instruction of which the instruction type is an extended instruction and the used register is an extended register is marked as a second extended instruction, and the value of the first preset position of the second extended instruction is set as a second preset value.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tags comprises:
assigning the first extended instruction and the generic instruction to a first Scoreboard, the first Scoreboard sending the first extended instruction and the generic instruction to a first transmitter;
assigning the second extended instruction to a second Scoreboard, the second Scoreboard sending the second extended instruction to a second transmitter.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
the first transmitter sends a first extended instruction to the second transmitter.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
in response to the second transmitter receiving a first extended instruction sent by the first transmitter and/or a second Scoreboard, determining whether a register used by the first extended instruction is occupied;
sending the first extended instruction to the second Scoreboard in response to the register used by the first extended instruction being occupied.
In some embodiments of the present invention, marking the instruction according to the type of the instruction and/or the type of register used further comprises:
counting and recording the sequence of the first extended instruction in a pipeline, and writing the sequence of the first extended instruction into a second preset position of the first extended instruction; and
in response to the second extended instruction being resolved, writing a final value of the order of the first extended instruction into a second predetermined position of the second extended instruction, and clearing the order of the first extended instruction.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
the second transmitter records the value of a second preset position of the transmitted first extended instruction through a shift register;
in response to the second transmitter receiving a second extended instruction, the second transmitter comparing a value of a second predetermined location of the second extended instruction with a value in the shift register;
in response to the value of the second predetermined position of the second extended instruction being less than the value of the shift register, shifting the second extended instruction to read the value of the next shift register or to wait for a new shift register.
In some embodiments of the invention, assigning the instructions to different pipeline executions based on the tag further comprises:
the second transmitter records the value of a second preset position of the transmitted first extension instruction in a cumulative manner through corresponding positions of a queue;
in response to the second transmitter receiving a second spread instruction, the second transmitter comparing a factorization of a value of a second predetermined location of the second spread instruction to a value of a corresponding location in the queue;
in response to the factoring of the value of the second predetermined position of the second extended instruction being greater than the value of the corresponding position of the queue, shifting the second extended instruction to read a next value of the shift register or to wait for a new value of the shift register.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
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