CN114039562B

CN114039562B - Low-cost over-frequency high-speed trans-impedance amplifier

Info

Publication number: CN114039562B
Application number: CN202111351836.2A
Authority: CN
Inventors: 赵欣; 王睿; 蔡之骏; 雷春桃; 陶蕤; 毛毅
Original assignee: Chengdu Mingyi Electronic Technology Co ltd
Current assignee: Chengdu Mingyi Electronic Technology Co ltd
Priority date: 2021-11-16
Filing date: 2021-11-16
Publication date: 2022-08-30
Anticipated expiration: 2041-11-16
Also published as: CN114039562A

Abstract

The invention provides a low-cost ultra-frequency high-speed transimpedance amplifier which comprises a high-speed communication link, a low-speed control circuit and a power supply management unit; the high-speed communication link unit comprises a pre-transimpedance amplifier, a continuous time equalizer, a limiting amplifier and an output buffer; the low-speed control circuit comprises a direct current offset eliminator and an automatic gain controller; the pre-transimpedance amplifier comprises a feedforward amplifier unit and a feedback resistance unit; the feedback resistance unit is lapped between the output end and the input end of the feedforward amplifier unit. The invention not only extends the system bandwidth combined with the low-speed photodiode through the arrangement, thereby ensuring the possibility of overclocking; simultaneously, the associated problem caused by the limitation of the process performance is solved, and the sensitivity and the dynamic range of the system are ensured; and the adopted components are conventional circuit components, so that a low-cost scheme becomes possible, and the practical production and popularization of products are facilitated.

Description

Low-cost over-frequency high-speed trans-impedance amplifier

Technical Field

The invention belongs to the technical field of communication, and particularly relates to a low-cost super-frequency high-speed trans-impedance amplifier.

Background

Reducing the cost of optical communications on the premise of increasing communication speeds and guaranteeing transmission quality is a key to the market competition of modern companies. In the field of 10G PON optical communications, it is first necessary to start with an optical device that occupies a large cost factor in order to further reduce the communication cost. On the front end side of the optical receiver, a product for changing the avalanche type photodiode APD adapted to the transimpedance amplifier TIA from a high bandwidth to a lower bandwidth is one of the starting directions, for example, a photodiode with an original bandwidth of about 7GHz is changed to a photodiode with a bandwidth of 3.5GHz or lower.

The width of the 3.5GHz photodiode is far lower than that of the 7GHz photodiode, so that on the premise of ensuring that the performance is not changed, the problem that how to overcome the reduction of the bandwidth caused by adopting the low-bandwidth photodiode and avoid the influence of intersymbol interference on the sensitivity caused by the reduction of the bandwidth of a system combining the photodiode and the transimpedance amplifier becomes a difficult problem.

In addition, the process selection of the transimpedance amplifier itself must avoid expensive special processes such as SiGe and cannot be better than the process of CMOS which is currently designed for the transmission rate, otherwise the cost saving goal is violated. Therefore, due to the limitation of process performance, the transimpedance amplifier needs to overcome the accompanying problems of increased noise, increased group delay variation, reduced dynamic range and increased power consumption while increasing the bandwidth.

Disclosure of Invention

Aiming at the requirements and the defects in the prior art, the invention provides a low-cost super-frequency high-speed transimpedance amplifier, which comprises a high-speed communication link, a low-speed control circuit and a power supply management unit; the high-speed communication link unit comprises a preposed transimpedance amplifier, a continuous time equalizer, a limiting amplifier and an output buffer; the low-speed control circuit comprises a direct current offset eliminator and an automatic gain controller; the pre-transimpedance amplifier comprises a feedforward amplifier unit and a feedback resistance unit; the feedback resistance unit is lapped between the output end and the input end of the feedforward amplifier unit. The invention increases the bandwidth of the preposed trans-impedance amplifier by the direct current offset eliminator and the automatic gain controller in the low-speed control circuit and the cooperation of the continuous time equalizer and the limiting amplifier. The invention not only extends the system bandwidth combined with the input low-speed photodiode through the arrangement, ensures the possibility of over-frequency, but also solves the associated problem caused by the limitation of the process performance, ensures the sensitivity and the dynamic range of the system, adopts conventional circuit components, makes the low-cost scheme possible, and is beneficial to the actual production, popularization and application of products.

The specific implementation content of the invention is as follows:

the invention provides a low-cost super-frequency high-speed trans-impedance amplifier, which is connected with a photodiode and used for receiving a current signal Iin sent by the photodiode, wherein the current signal Iin comprises a direct current component and an alternating current component; the over-frequency high-speed trans-impedance amplifier comprises a high-speed communication link, a low-speed control circuit and a power supply management unit;

the high-speed communication link unit comprises a pre-transimpedance amplifier, a continuous time equalizer, a limiting amplifier and an output buffer; the low-speed control circuit comprises a direct current offset eliminator and an automatic gain controller;

the pre-transimpedance amplifier comprises a feedforward amplifier unit and a feedback resistance unit; the feedback resistance unit is lapped between the output end and the input end of the feedforward amplifier unit;

the input end of the feedforward amplifier unit is connected with the photodiode, receives a current signal Iin sent by the photodiode, and the output end of the feedforward amplifier unit is connected with the continuous time equalizer, the limiting amplifier and the output buffer link; the output end of the output buffer is the output end of the over-frequency high-speed transimpedance amplifier;

the direct current offset canceller is connected to the input end and the output end of the feedforward amplifier unit;

the input end of the automatic gain controller is respectively connected with the output end of the continuous time equalizer and the output end of the limiting amplifier, and the output end of the automatic gain controller is connected with the feedback resistance unit and the feedforward amplifier unit;

the power management unit is respectively connected with the pre-transimpedance amplifier, the continuous time equalizer, the limiting amplifier, the output buffer, the direct current offset eliminator and the automatic gain controller.

In order to better implement the present invention, further, the feed forward amplifier unit includes a current processing unit, an inverter unit, and a current mirror unit;

the input end of the current processing unit is connected with a current signal Iin, and the output end of the current processing unit is connected with the inverter unit;

the feedback resistance unit is lapped on the input end and the output end of the phase inverter unit;

the current mirror unit is connected with the inverter unit;

the output end of the inverter unit is the output end of the pre-transimpedance amplifier connected with the continuous time equalizer;

the direct current offset eliminator and the automatic gain controller are connected with the current processing unit.

In order to better implement the present invention, further, the inverter unit includes three sets of inverter combinations, which are a first inverter, a second inverter, and a third inverter;

the first phase inverter comprises a first PMOS tube and a first NMOS tube; the grid electrodes of the first PMOS tube and the first NMOS tube are used as the input end of the first phase inverter; the drain electrodes of the first PMOS tube and the first NMOS tube are used as the output end of the first phase inverter; the source electrode of the first PMOS tube is connected with the current mirror unit, and the source electrode of the first NMOS tube is grounded;

the second phase inverter comprises a second PMOS tube and a second NMOS tube; the grid electrodes of the second PMOS tube and the second NMOS tube are used as the input end of the second phase inverter; the drain electrodes of the second PMOS tube and the second NMOS tube are used as the output end of the second phase inverter; the source electrode of the second PMOS tube is connected with the current mirror unit, and the source electrode of the second NMOS tube is grounded;

the third phase inverter comprises a third PMOS tube and a third NMOS tube; the grid electrodes of the third PMOS tube and the third NMOS tube are used as the input end of the third phase inverter; the drain electrodes of the third PMOS tube and the third NMOS tube are used as the output end of the third phase inverter; the source electrode of the third PMOS tube is connected with the current mirror unit, and the source electrode of the third NMOS tube is grounded;

the three groups of inverters are sequentially connected in a link manner, the input end of the first inverter is a pole A, the output end of the first inverter and the input end of the second inverter are a pole B, the output end of the second inverter and the input end of the third inverter are a pole C, and the output end of the third inverter is a pole D; the pole C and the pole D are output ends of the pre-transimpedance amplifier and the continuous time equalizer;

the feedback resistance unit is lapped on the pole A and the pole D;

and the pole A is a connecting end of the inverter unit and the current processing unit.

In order to better implement the present invention, the inverter unit further includes a resistor R1, one end of the resistor R1 is overlapped between the gates of the second PMOS transistor and the second NMOS transistor, and the other end of the resistor R1 is overlapped between the drains of the second PMOS transistor and the second NMOS transistor.

In order to better implement the present invention, further, the current processing unit includes an inductor L1, a fifth NMOS transistor, and a sixth NMOS transistor;

the input end of the inductor L1 is connected with a current signal Iin sent by the photodiode, and the output end of the inductor L1 is connected with the input end of the first inverter;

the fifth NMOS tube is grounded and then lapped at the output end of the inductor L1, and the sixth NMOS tube is grounded and then lapped at the input end of the first inverter.

In order to better implement the present invention, further, the current processing unit further includes a capacitor C4 and a resistor R5;

the capacitor C4 and the resistor R5 are connected in series and then grounded through the resistor R5, and the sixth NMOS tube is connected with the capacitor C4.

In order to better implement the present invention, further, the feedback resistance unit includes a resistor R2, a resistor R3, and a resistor R4 connected in series; the device also comprises a fourth NMOS tube;

the source and the drain of the fourth NMOS tube are respectively lapped at two ends of the resistor R3, and the grid of the fourth NMOS tube is connected with the output end of the automatic gain controller; the resistor R2 and the resistor R4 are correspondingly connected with the pole A and the pole D or the resistor R2 and the resistor R4 are correspondingly connected with the pole D and the pole A.

In order to better implement the present invention, further, the current mirror unit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a clamp OP 1;

the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube and serves as a voltage point F, and the drain electrode of the fifth PMOS tube and the grid electrode of the fourth PMOS tube are grounded;

the grid electrode of the fifth PMOS tube is connected with the output end of a clamp operational amplifier OP1, the negative input end of the clamp operational amplifier OP1 is lapped at a voltage point F, and the positive input end of the clamp operational amplifier OP1 is connected with the drain electrode of the sixth PMOS tube and then serves as a voltage point E connected with the first inverter, the second inverter and the third inverter;

the source electrode of the fourth PMOS tube and the source electrode of the sixth PMOS tube are connected with a power supply input by the power supply management unit; and the grid electrode of the fourth PMOS tube and the grid electrode of the sixth PMOS tube are mutually connected.

In order to better implement the present invention, further, the current mirror unit further includes a capacitor C1, a capacitor C2; the capacitor C1 is used as a filter capacitor, one end of the capacitor C1 is lapped on the input end of the power management unit, and the other end of the capacitor C1 is lapped between the grid electrode of the fourth PMOS tube and the grid electrode of the sixth PMOS tube;

the capacitor C2 is used as a decoupling capacitor and is lapped between the source electrode of the sixth PMOS tube and the voltage point E.

To better implement the present invention, further, the current mirror unit further includes a capacitor C3;

the capacitor C3 is grounded and then connected to the output end of the clamp OP 1.

In order to better implement the present invention, further, the automatic gain controller includes two digital output control channels and an automatic gain digital controller;

one digital output control channel comprises a common-mode voltage extraction unit, a threshold voltage generator, a peak detector and a hysteresis comparator; the common-mode voltage extraction unit is lapped between the two input ends of the peak detector and is used for extracting common-mode voltage; the common-mode voltage extraction unit is also connected with the threshold voltage generator and is used for sending the extracted common-mode voltage to the threshold voltage generator and generating two paths of thresholds including a high threshold and a low threshold by setting a differential voltage; the high threshold and the low threshold represent the highest value and the lowest value after the difference between the difference voltage and the common mode voltage is obtained; the threshold voltage generator is connected with the peak detector and sends a threshold value of signal amplitude obtained by taking the difference between a high threshold value and a low threshold value to the hysteresis comparator; the hysteresis comparator is connected with the automatic gain digital controller;

one of the two digital output control channels is connected with two output ends of the continuous time equalizer through two input ends of the peak value detector, and the other digital output control channel is connected with two output ends of the limiting amplifier through two input ends of the peak value detector.

In order to better implement the present invention, further, the automatic gain digital controller includes an inverter, an and gate, a fourth inverter, and a fifth inverter;

one input end of the NOT gate is connected with the output end of a hysteresis comparator in a digital output control channel connected with the continuous time equalizer; one input end of the AND gate is connected with the output end of a hysteresis comparator in a digital output control channel connected with the limiting amplifier; the AND gate also has an input end connected with the output end of the NOT gate, and the NOT gate also has an input end connected with the output end of the AND gate;

the output end of the NOT gate is also in link connection with a fourth inverter and a fifth inverter; and the output end of the fifth inverter is the output end of the automatic gain controller connected with the feedback resistance unit and the feedforward amplifier unit.

In order to better implement the present invention, further, a capacitor Ca3 is further included in the automatic gain digital controller of the automatic gain controller; the capacitor Ca3 is grounded and then connected to the output end of the fifth inverter in a lap joint mode to serve as a filter capacitor.

In order to better implement the present invention, further, the dc offset canceller includes a resistor Rb1, a resistor Rb2, a capacitor Cb1, a capacitor Cb2, a first operational amplifier OPb1, and a second operational amplifier OPb 2;

the resistor Rb1 is lapped on the positive input end of the first operational amplifier OPb1, and the resistor Rb2 is lapped on the negative input end of the first operational amplifier OPb 2; the capacitor Cb1 is lapped between the positive input end and the negative output end of the first operational amplifier OPb 1; the capacitor Cb2 is lapped between the negative input end and the positive output end of the first operational amplifier OPb 1; the positive input end and the negative input end of the first operational amplifier OPb1 are correspondingly connected with the positive input end and the negative input end of the OPb2 of the second operational amplifier; the output end of the second operational amplifier OPb2 is connected with the current processing unit of the pre-transimpedance amplifier;

the input end of the resistor Rb1 is connected with the pole A in the inverter unit of the pre-transimpedance amplifier; the input terminal of the resistor Rb2 is connected to pole D in the inverter cell of the pre-transimpedance amplifier.

In order to better implement the present invention, the dc offset canceller further includes a capacitor Cb3, and the capacitor Cb3 is grounded and then connected to the output terminal of the second operational amplifier OPb2 as a stable capacitor.

Compared with the prior art, the invention has the following advantages and beneficial effects:

(1) according to the invention, through the arrangement, the system bandwidth combined with the input low-speed photodiode is extended, the possibility of over-frequency is ensured, the accompanying problem caused by the limitation of process performance is solved, the sensitivity and the dynamic range of the system are ensured, and conventional circuit components are adopted, so that a low-cost scheme is possible, and the practical production, popularization and application of products are facilitated;

(2) under the condition that the bandwidth of a photodiode is 3.5GHz, a preposed transimpedance amplifier formed by a traditional primary inverter is difficult to extend the bandwidth, and even if the preposed transimpedance amplifier is optimized, the current simulation is only about 3.1 GHz; the preposed transimpedance amplifier can greatly improve the fundamental frequency of 5GHz with the bandwidth exceeding 10Gbps input signals, simulate about 5.8GHz at present, and increase transimpedance gain (6 dB) more than one time to reduce input equivalent noise;

(3) because the bandwidth of the pre-transimpedance amplifier is enough, intersymbol interference is greatly reduced compared with the traditional design, and the transimpedance gain is larger than the traditional design, under the condition that the amplitudes of input current signals are the same, the eye height of an eye pattern output by the pre-transimpedance amplifier in the transient simulation is larger, an eye skin is thinner, and jitter is smaller; thus, the design cost of the continuous time equalizer and the trans-impedance amplifier of the later stage is greatly reduced;

(4) according to the patent, the automatic gain controller can ensure that the output control signal Vagc can only be turned over once under the condition that the input signal strength meets the threshold value under the reasonable control logic through the hysteresis of the comparator and the systematic hysteresis generated by different threshold values of the double detection points;

(5) when the amplitude of the signal at the detection point swings around the threshold voltage, the conventional non-hysteresis comparator generates large jitter, which causes the back-and-forth switching of the control signal Vagc, and the large jitter of the transition affects the quality of the signal by coupling the power supply and the ground to the high-speed signal link; in addition, logic misjudgment can be caused, and error codes are caused by switching back and forth near a threshold value; the hysteresis comparator avoids output jitter generated near the threshold, and the output control voltage Vagc is only switched once when the threshold requirement is met, so that logic misjudgment is avoided;

(6) reasonable hysteresis avoids the influence of signal amplitude jitter on switching; therefore, the output signal Vagc of the automatic gain controller is only switched once when the amplitude of the detection point meets the threshold requirement, so that the error code generated by switching back and forth at the switching point due to any amplitude jitter is avoided; meanwhile, the input and output signals at the two switching points are large enough, the input signals are far away from the sensitivity range, the swing amplitude of the output signals exceeds 2x100mVpp at the switching points, good signal-to-noise ratio is ensured at the switching points, and error codes are not easily caused by too low signal-to-noise ratio;

(7) when a current signal with a direct current component and an alternating current component is suddenly input into the pre-transimpedance amplifier, the voltage of a point D is reduced because the voltage of a point A is stable and the voltage of the point D is reduced because the direct current component generates voltage drop at the transimpedance position; the control voltage Vdcoc is boosted to bypass the direct-current component of the input signal by starting the work of the direct-current offset loop, so that the voltage flowing through the trans-resistance can be reduced, namely the average voltage of a point D is increased; when the average voltages at points a and D are consistent, the loop regulation is stopped and the control voltage vdc regulation is stopped and remains substantially stable.

Drawings

FIG. 1 is a schematic view of the complete structural framework of the present invention;

FIG. 2 is a simplified schematic diagram of a pre-transimpedance amplifier;

FIG. 3 is a schematic circuit diagram of a pre-transimpedance amplifier;

FIG. 4 is a diagram of the relationship of an automatic gain controller;

FIG. 5 is a block diagram of an automatic gain controller;

FIG. 6 is a digital logic diagram of an automatic gain digital controller;

FIG. 7 is a diagram of a DC offset canceller;

FIG. 8 is a schematic diagram of a circuit structure of a DC offset canceller;

FIG. 9 shows a photodiode at 10 ⁶ -10 ⁹ A frequency response simulation schematic diagram under the HZ frequency;

FIG. 10 shows a photodiode at 10 ⁹ -10 ¹⁰ A frequency response simulation schematic diagram under the HZ frequency;

FIG. 11 shows a pre-transimpedance amplifier of the present application with an inverter configuration at 10 ⁶ -10 ⁹ A frequency response simulation schematic diagram under the HZ frequency;

FIG. 12 shows a pre-transimpedance amplifier 10 with an inverter configuration according to the present application ⁹ -10 ¹⁰ A frequency response simulation schematic diagram under the HZ frequency;

FIG. 13 shows a conventional single inverter configuration pre-transimpedance amplifier at 10 ⁶ -10 ⁹ A frequency response simulation schematic diagram under the HZ frequency;

FIG. 14 shows a conventional single inverter configuration pre-transimpedance amplifier at 10 ⁹ -10 ¹⁰ A frequency response simulation schematic diagram under the HZ frequency;

FIG. 15 is a transient response simulation output eye diagram of a photodiode;

FIG. 16 is a simulated output eye diagram of the transient response of the pre-transimpedance amplifier of the inverter configuration of the present application;

FIG. 17 is a simulated output eye diagram of the transient response of a conventional single inverter architecture pre-transimpedance amplifier;

FIG. 18 is a diagram of a simulation of the Vagc output for a conventional non-hysteretic comparator operating at 0-2 us;

FIG. 19 is a diagram illustrating the simulation of the Vagc output of a conventional non-hysteresis comparator for a period of 2-3.5 us;

FIG. 20 is a simulation diagram of the output of the hysteretic comparator in the AGC of this application for 0-2 us;

FIG. 21 is a schematic diagram of an output simulation of the hysteretic comparator in the AGC of the present application for 2-3.5 us;

FIG. 22 is a simulation diagram of the output of the corresponding post-stage control voltage Vagc when the hysteresis comparator time is 0-2us in the automatic gain controller of the present application;

FIG. 23 is a simulation diagram of the output of the hysteresis comparator of the automatic gain controller of the present application with a corresponding backward control voltage Vagc time of 2-3.5 us;

FIG. 24 is a schematic diagram of a transient response simulation output of the photodiode output signal of the present application under dynamic changes in input signal amplitude;

FIG. 25 is a schematic diagram of a transient response simulated output of a transimpedance amplifier outputting a differential signal under dynamic changes in the amplitude of the input signal;

FIG. 26 is a schematic diagram of an output simulated transient response of the AGC output control voltage Vagc under dynamic changes in the input signal amplitude;

FIG. 27 is a schematic diagram illustrating a simulation of the DC offset cancellation function of the input current signal according to the present application;

FIG. 28 is a schematic diagram of a simulation of the DC offset cancellation function of the pole A voltage signal and the pole D voltage signal according to the present application;

FIG. 29 is a simulation diagram of the DC offset cancellation function of the Vdcoc control voltage signal according to the present application.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and therefore should not be considered as a limitation to the scope of protection. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Example 1:

the embodiment provides a low-cost super-frequency high-speed trans-impedance amplifier, which is connected with a photodiode and used for receiving a current signal Iin sent by the photodiode, wherein the current signal Iin comprises a direct current component and an alternating current component; as shown in fig. 1, fig. 2, and fig. 3, the over-frequency high-speed transimpedance amplifier includes a high-speed communication link, a low-speed control circuit, and a power management unit;

The working principle is as follows: the invention increases the bandwidth of the preposed trans-impedance amplifier by the direct current offset eliminator and the automatic gain controller in the low-speed control circuit and the cooperation of the continuous time equalizer and the limiting amplifier. The invention not only extends the system bandwidth combined with the input low-speed photodiode through the arrangement, ensures the possibility of over-frequency, but also solves the associated problem caused by the limitation of the process performance, ensures the sensitivity and the dynamic range of the system, adopts conventional circuit components, makes the low-cost scheme possible, and is beneficial to the actual production, popularization and application of products.

Example 2:

this embodiment is based on the above embodiment 1, and in order to better implement the present invention, further, as shown in fig. 2 and fig. 3, the feed forward amplifier unit includes a current processing unit, an inverter unit, and a current mirror unit;

the current mirror unit is connected with the inverter unit;

The working principle is as follows: the bandwidth can be increased by utilizing a high-speed communication post-stage circuit such as a continuous time equalizer source electrode degradation technology and a limiting amplifier load inductance peaking technology, but compared with the mode of increasing the bandwidth by a preposed transimpedance amplifier, more high-frequency noise influence sensitivity can be introduced, so that the scheme for greatly increasing the bandwidth to realize over-frequency is provided, and the bandwidth is expanded mainly by depending on the special structure of the preposed transimpedance amplifier of a high-speed communication link and a low-speed control circuit matched with the preposed transimpedance amplifier.

The signal transmission main circuit of the preposed trans-impedance amplifier is in a parallel shunt feedback loop structure, is negative feedback and consists of a feed-forward amplifier and a feedback resistor. The structure of a pre-transimpedance amplifier of this type is depicted in a simplified diagram in fig. 2. The gain of the feedforward amplifier is A0, the feedback resistance is Rf, the parasitic capacitance of the input point is Cin, the current signal Iin is input, and the voltage signal Vout is output.

Calculation formula of trans-impedance gain and-3 dB bandwidth

The calculation formula of (a) is as follows:

；

；

in the above formula, Rin is the input impedance, and is about equivalent to Rf/a0 when a0 is large enough, that is, the current transimpedance Rf and Cin are fixed, and the larger the feed amplifier gain a0 is, the smaller the input impedance Rin is, and the larger the bandwidth thereof will be. The pre-transimpedance amplifier described in this patent will boost bandwidth primarily by increasing its feed forward amplifier gain a0 and optimizing Cin size.

Other parts of this embodiment are the same as those of embodiment 1, and thus are not described again.

Example 3:

in this embodiment, on the basis of any one of the above embodiments 1-2, in order to better implement the present invention, as shown in fig. 3, the inverter unit includes three sets of inverter combinations, namely, a first inverter, a second inverter, and a third inverter;

the three groups of inverters are sequentially connected in a link manner, the input end of the first inverter is a pole A, the output end of the first inverter and the input end of the second inverter are poles B, the output end of the second inverter and the input end of the third inverter are poles C, and the output end of the third inverter is a pole D; the pole C and the pole D are output ends of the pre-transimpedance amplifier and the continuous time equalizer;

the feedback resistance unit is lapped on the pole A and the pole D;

The working principle is as follows: the design scheme of the pre-transimpedance amplifier is shown in fig. 3, and the input signal is a current signal Iin photoelectrically converted by a photodiode, and has direct current and alternating current components. The pre-transimpedance amplifier has the main function of bypassing the direct-current component of the current signal and amplifying the alternating-current component into a voltage signal output without distortion as much as possible.

Three groups of inverters of a feed-forward amplifier in the trans-impedance amplifier are respectively combined by PM1 and NM 1; PM2, NM2 combination; PM3, NM3 in combination, provide an open loop gain of sufficient magnitude to help reduce the input impedance of the transimpedance amplifier and increase bandwidth. When all the inverters are the same in size, the four-point direct-current voltages of A, B, C and D are basically consistent, so that the current can be evenly distributed into three groups of inverters in a dynamic range, and each group of inverters can achieve the optimal gain-bandwidth product. Therefore, the gain bandwidth product of the feedforward amplifier formed by cascading three inverters is far larger than that of the feedforward amplifier formed by only one inverter in the traditional scheme, the bandwidth of a closed-loop system after trans-impedance feedback can be greatly expanded, the problem of intersymbol interference caused by insufficient bandwidth is solved, and main help is provided for the over-frequency success of the whole system. When the gain of the feedforward amplifier is increased, the transimpedance gain can be properly increased on the premise of ensuring the bandwidth so as to reduce the size of the input equivalent noise and improve the sensitivity of the system. Finally, because the direct-current voltage of the point C is consistent with that of the point D, and the signals at the two positions are in differential complementation, the signals at the two positions C and D can be directly connected to the differential input of the next-stage high-speed circuit, compared with the traditional design, one path of reference circuit can be saved, and the capability of the circuit for resisting common-mode interference can be improved when the differential signals enter the next stage.

Except that the direct current component of the signal is removed through the direct current offset eliminator, in order to avoid distortion of an output signal of the pre-transimpedance amplifier caused by overlarge input alternating current component, the transimpedance, namely, the transimpedance gain of the pre-transimpedance amplifier needs to be reduced through the automatic gain controller after the condition is met. In addition, when the transimpedance is reduced, the direct-current gain of a feed-forward amplifier consisting of the three phase inverters is ensured to be unchanged, the input impedance of the preposed transimpedance amplifier at the point A can be correspondingly reduced, and the condition that the input voltage at the point A of the preposed transimpedance amplifier is too large and enters the states of amplitude limiting and distortion when large current is input is avoided. However, the dc gain of the tri-inverter combination is not changed, which results in the input impedance at the a point position becoming smaller in the low trans-impedance mode under the automatic gain control. This may shift the dominant pole of the a-point location towards high frequencies close to the second pole of the D-point location, causing the phase margin of the feedback system to become smaller, affecting stability and increasing jitter in the amplitude and phase of the eye diagram. Therefore, the feedback voltage Vagc of the automatic gain control is used for controlling and increasing the capacitance of the dominant pole of the input A point position of the pre-transimpedance amplifier, and the problem of stability can be effectively solved after the transimpedance is reduced. The automatic gain controller is NM6 in the access part of the pre-transimpedance amplifier.

Other parts of this embodiment are the same as any of embodiments 1-2 described above, and thus are not described again.

Example 4:

in this embodiment, on the basis of any one of the above embodiments 1 to 3, in order to better implement the present invention, as shown in fig. 3, the inverter unit further includes a resistor R1, one end of the resistor R1 is overlapped between the gates of the second PMOS transistor and the second NMOS transistor, and the other end of the resistor R1 is overlapped between the drains of the second PMOS transistor and the second NMOS transistor.

The working principle is as follows: the resistor R1 can help to greatly reduce the impedance at the output point B of the PM1, NM1 inverter and reduce the impedance at the output point C of the PM2, NM2 inverter, shifting the poles B, C to higher frequencies. This leaves the dominant poles in the loop at only a, D, thus allowing the loop to be close to a two pole system. During design, only the point A is ensured to be a main pole with lower frequency all the time under all conditions, and meanwhile, the parasitic capacitance of a secondary pole of the position of the point D is reduced as much as possible, so that the difficulty of loop stability compensation can be greatly reduced.

Other parts of this embodiment are the same as any of embodiments 1 to 3, and thus are not described again.

Example 5:

in this embodiment, on the basis of any one of the foregoing embodiments 1 to 4, in order to better implement the present invention, as shown in fig. 3, the current processing unit includes an inductor L1, a fifth NMOS transistor, and a sixth NMOS transistor;

The working principle is as follows: the input part of the signal transmission link of the pre-transimpedance amplifier is a series inductor L1, and after the series inductor is added, the parasitic capacitance of the photodiode and the input parasitic capacitance of the pre-transimpedance amplifier can be isolated to a certain degree, and partial bandwidth can be improved in advance through resonance with the two capacitors.

The feedback voltage Vagc of the automatic gain control is used for controlling and increasing the capacitance of the main pole of the input A point position of the pre-transimpedance amplifier, so that the problem of stability can be effectively solved after the transimpedance is reduced. The automatic gain controller is NM6 in the access part of the pre-transimpedance amplifier. When NM6 is turned on, a parallel compensation capacitor C4 is introduced to the main pole of the a position to ensure that the position of the main pole is unchanged. In addition, the series resistor R5 of the C4 can finely adjust the phase of the point A, so that the large change of group delay at a high frequency position is avoided when the transimpedance is reduced, and the quality is ensured.

In order to ensure that the working point of the pre-transimpedance amplifier is still normal when the intensity of the input optical signal is increased, and to avoid signal distortion caused by the change of the working point, a direct current offset canceller generally needs to be adopted to remove a direct current component of the input signal. The gate voltage Vdcoc of the input NM5 transistor is the feedback voltage of the dc offset canceller. When the direct current component of the current signal flowing into the pre-transimpedance amplifier is increased, the voltage of the Vdcoc is increased along with the adjustment of the loop, all input direct current is enabled to be completely bypassed through the NM5, the working point voltage of the pre-transimpedance amplifier cannot be influenced, and therefore distortion of the input and output signals caused by the change of the working point is avoided.

Other parts of this embodiment are the same as any of embodiments 1 to 4, and thus are not described again.

Example 6:

this embodiment is based on any of the above embodiments 1 to 5, and in order to better implement the present invention, further, as shown in fig. 3, the current processing unit further includes a capacitor C4 and a resistor R5;

The working principle is as follows: when NM6 is turned on, a parallel compensation capacitor C4 is introduced to the main pole of the a position to ensure that the position of the main pole is unchanged. In addition, the series resistor R5 of the C4 can finely adjust the phase of the point A, so that the large change of group delay at a high frequency position is avoided when the transimpedance is reduced, and the quality of an eye pattern is ensured

Other parts of this embodiment are the same as any of embodiments 1 to 5, and thus are not described again.

Example 7:

this embodiment is based on any one of the above embodiments 1 to 6, and in order to better implement the present invention, further, as shown in fig. 3, the feedback resistance unit includes a resistor R2, a resistor R3, and a resistor R4 connected in series; the device also comprises a fourth NMOS tube;

The working principle is as follows: the trans-impedance part of the trans-impedance amplifier is formed by connecting R2 in series with the parallel resistor of R3 and NM4 and then connecting R4 in series. The parallel structure of R3 to NM4 is similar to a voltage-controlled varistor, and changes with the change of the control voltage Vagc. A calibrated parallel resistance, approximately the value of R3, is obtained when the control signal Vagc input by the agc is small. The R2 and R4 are connected in parallel with the voltage-controlled varistor to isolate the influence of the parasitic capacitance of the NMOS transistor NM4 on the varistor on the input and output bandwidth of the transimpedance amplifier.

Other parts of this embodiment are the same as any of embodiments 1 to 6, and thus are not described again.

Example 8:

in this embodiment, on the basis of any one of the above embodiments 1 to 7, in order to better implement the present invention, further, as shown in fig. 3, the current mirror unit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a clamp OP 1;

the grid electrode of the fifth PMOS tube is connected with the output end of a clamp operational amplifier OP1, the negative electrode input end of the clamp operational amplifier OP1 is lapped at a voltage point F, and the positive electrode input end of the clamp operational amplifier OP1 is connected with the drain electrode of the sixth PMOS tube and then is used as a voltage point E connected with the first phase inverter, the second phase inverter and the third phase inverter;

The working principle is as follows: the PM4, the PM5, the PM6 and the guard operation amplifier OP1 form a current mirror structure to provide current for the preposed transimpedance amplifier. Theoretically, when the dc gain of the OP-amp OP1 is large enough, the voltages at point E and point F are nearly identical, which makes the mismatch of the current mirror small.

The current mirror structure provides accurate current for the preposed transimpedance amplifier, under the condition that the sizes of the PMOS and the NMOS of the phase inverter in the preposed transimpedance amplifier are determined, the PMOS and the NMOS in the three-stage amplifier can be close to the speed saturation state of the field effect triode by providing the current with the accurately calculated size, the gain bandwidth product of the open-loop three-stage amplifier can be further expanded, and the bandwidth product of the preposed transimpedance amplifier in the closed-loop mode can be further expanded equivalently

Other parts of this embodiment are the same as any of embodiments 1 to 7, and thus are not described again.

Example 9:

this embodiment is based on any of the above embodiments 1 to 8, and in order to better implement the present invention, further, as shown in fig. 3, the current mirror unit further includes a capacitor C1, a capacitor C2; the capacitor C1 is used as a filter capacitor, one end of the capacitor C1 is lapped on the input end of the power management unit, and the other end of the capacitor C1 is lapped between the grid electrode of the fourth PMOS tube and the grid electrode of the sixth PMOS tube;

The working principle is as follows: the capacitors C1 and C2 surrounding the current mirror play the roles of filtering and decoupling capacitors, so that the jitter of a power supply is small, and the performance of the pre-transimpedance amplifier is difficult to influence.

Other parts of this embodiment are the same as any of embodiments 1 to 8, and thus are not described again.

Example 10:

this embodiment is based on any of the above embodiments 1 to 9, and in order to better implement the present invention, further, as shown in fig. 3, the current mirror unit further includes a capacitor C3;

The working principle is as follows: the C3 is used as an operational amplifier high-resistance output capacitor to play a role of a dominant pole, and the stability of the clamp-guard operational amplifier loop is ensured.

Other parts of this embodiment are the same as any of embodiments 1 to 9, and thus are not described again.

Example 11:

this embodiment is based on any of the above embodiments 1 to 10, and further, as shown in fig. 4, 5, and 6, in order to better implement the present invention, the automatic gain controller includes two digital output control channels and an automatic gain digital controller;

The working principle is as follows: theoretically, the feedback voltage Vagc of the agc needs to linearly adjust the transimpedance and the input pole compensation capacitor at the same time, and when the transimpedance is reduced, the dominant pole compensation capacitance is increased, so that the transimpedance can be reduced without changing the bandwidth and stability. However, these two adjustments do not change linearly with the change in Vagc, and also produce various unknown changes with the change in process angle. If the trans-impedance is changed first, the bandwidth is too large, and the stability of the loop is poor. If the dominant pole compensation capacitance is increased first, this will result in an early reduction of bandwidth. To avoid the generation of non-linear intermediate states during analog regulation, the agc is designed to switch digitally, providing a two-step change. When the input optical signal is small, the high transimpedance mode is set, and when the input optical intensity exceeds a threshold value, the low transimpedance mode is entered. Therefore, the difficulty of automatic gain control compensation is greatly reduced, and the high consistency of the trans-impedance control of mass production chips is ensured.

In order to ensure that the pre-transimpedance amplifier has a large dynamic range, a general automatic gain controller can reduce transimpedance when the amplitude of a monitoring point signal is increased and touches a threshold voltage by acquiring the amplitude of the monitoring point signal, so that the output signal of the pre-transimpedance amplifier is not easy to distort under the large optical signal intensity.

As a result, in order to ensure that the loop of the pre-transimpedance amplifier is always stable in a large dynamic range, avoid distortion of input and output signals, and reduce intermediate states or indeterminate states existing in the agc mode, the agc is designed to perform two-stage digital output control, i.e., a high transimpedance mode (Vagc = 0) during small light input and a low transimpedance mode (Vagc =1) during large light input. The inputs of the automatic gain controller are the output signal S1 of the continuous-time equalizer and the output signal S2 of the limiting amplifier, whose output feedback signal Vagc is shown in fig. 4.

Fig. 5 is a block diagram of an automatic gain controller. The automatic gain controller detects the amplitude of the differential signal output by the high-speed circuit by adopting a peak detection circuit, compares the amplitude with a threshold voltage, and determines whether impedance switching is needed or not after logical judgment. To avoid switching back and forth across the impedance due to interference for signals with amplitudes around the threshold, the automatic gain controller employs dual probe inputs S1 and S2.

S1 is the differential signal output of the continuous-time equalizer, and the differential signal branches off directly into the input of the peak detector Ua3 to extract the signal amplitude information. The other branch of S1 is filtered by low pass filters of Ra1, Ra2 and Ca1 and then extracted to a common mode voltage Vcm1, and then in a threshold voltage generator Ua1, Vcm1 is used as an intermediate voltage, the same difference voltage is used to generate two high and low thresholds, the difference of which represents the threshold Vth1 of the signal amplitude, and the threshold amplitude information is extracted after entering Ua 3. Then the signal amplitude information and the threshold amplitude information enter the comparator CMPa1 to be compared at the same time, if the signal amplitude is larger than the threshold amplitude, the comparator CMPa1 outputs G1=1, otherwise G1= 0.

S2 is the differential signal output of the limiting amplifier, which is branched directly into the input of the peak detector Ua4 to be extracted to signal amplitude information. The other branch of S2 is filtered by low pass filters of Ra3, Ra4 and Ca2 and then extracted to a common mode voltage Vcm2, then in a threshold voltage generator Ua2, Vcm2 is used as an intermediate voltage, the same difference voltage is used to generate two high and low thresholds, the difference represents a threshold Vth2 of the signal amplitude, and after entering Ua4, the two thresholds are extracted to threshold amplitude information. Then the signal amplitude information and the threshold amplitude information enter the comparator CMPa2 to be compared at the same time, if the signal amplitude is larger than the threshold amplitude, the comparator CMPa2 outputs G2=1, otherwise G2= 0.

To prevent errors in the signal around the threshold due to noise and pattern variations from causing the comparator output to toggle creating considerable signal glitches, comparators CMPa1 and CMPa2 are designed as hysteretic comparators.

The theoretical condition of the agc is that the limiting amplifier must have gain, which ensures that as the input signal amplitude increases, the S2 output signal amplitude is always greater than the S1 output signal amplitude before the signals at S1 and S2 do not enter limiting. Therefore, when the condition two Vth1 is smaller than clip and larger than Vth2, G1 will inevitably flip from 0 to 1 after G2 when the amplitude of the input signal is small to large, and G1 will inevitably flip from 1 to 0 before G2 when the amplitude of the input signal is large to small. Therefore, the amplitude of S1 exceeding the threshold Vth1 is used as a high impedance to low impedance transition determination, and the amplitude of S2 falling below the threshold Vth2 is used as a low impedance to high impedance transition determination, thereby generating hysteresis in the system, and when the signal amplitude meets the threshold requirement, the Vagc output logic is switched. Once the handoff is complete, the change that needs to satisfy the hysteresis can again cause Vagc to flip back again.

Other parts of this embodiment are the same as any of embodiments 1 to 10 described above, and thus are not described again.

Example 12:

in this embodiment, on the basis of any one of the above embodiments 1 to 11, in order to better implement the present invention, as shown in fig. 6, the automatic gain digital controller further includes an inverter, an and gate, a fourth inverter, and a fifth inverter;

one input end of the NOT gate is connected with the output end of the hysteresis comparator in the digital output control channel connected with the continuous time equalizer; one input end of the AND gate is connected with the output end of a hysteresis comparator in a digital output control channel connected with the limiting amplifier; the AND gate also has an input end connected with the output end of the NOT gate, and the NOT gate also has an input end connected with the output end of the AND gate;

The working principle is as follows: the control logic for the automatic gain is also related to the previous state of Vagc. Because the input of the digital logic is affected by the offset voltage of the comparator after the circuit is powered on, the offset voltage can cause the initial output value of the comparator to be random. It is only ensured that the transition from high gain to low gain is effective when the previous state Vagc' =0 of Vagc. The same holds for a transition from low to high gain to be effective only when the previous state Vagc' =1 for Vagc. Table 1 describes the relationship between the various inputs and outputs of the logic portion of the agc with a truth table.

TABLE 1 AGC digital logic truth table

The formula of the above logic and the logic control Ua5 converted from the formula are as follows:

other parts of this embodiment are the same as any of embodiments 1 to 11, and thus are not described again.

Example 13:

in this embodiment, on the basis of any one of the above embodiments 1 to 12, in order to better implement the present invention, as shown in fig. 4, fig. 5, and fig. 6, the automatic gain digital controller of the automatic gain controller further includes a capacitor Ca 3; the capacitor Ca3 is grounded and then connected to the output end of the fifth inverter in a lap joint mode to serve as a filter capacitor.

The working principle is as follows: since the requirements on the switching time of the output voltage Vagc of the agc are not very high due to the continuous mode of the transimpedance amplifier, the inverter can be appropriately sized and filtered by adding the capacitor Ca 3.

Other parts of this embodiment are the same as any of embodiments 1 to 12 described above, and thus are not described again.

Example 14:

in this embodiment, on the basis of any one of the above embodiments 1 to 13, in order to better implement the present invention, as shown in fig. 7 and 8, the dc offset canceller further includes a resistor Rb1, a resistor Rb2, a capacitor Cb1, a capacitor Cb2, a first operational amplifier OPb1, and a second operational amplifier OPb 2;

The working principle is as follows: the feedback loop of the dc offset canceller is shown in fig. 7, where points a, D coincide with the points in fig. 3. The direct current offset eliminator obtains average voltage at a point D, amplifies and integrates voltage difference between the two points by taking the average voltage of the point A as reference, and then feeds back the Vdcoc voltage to control the NM5 to pull out redundant direct current components of an input signal, so that the point D is always consistent with the point A. When the voltage difference between the point a and the point D is 0, it means that the transimpedance of the pre-transimpedance amplifier has no voltage drop, i.e., no direct current flows, and the working point of the pre-transimpedance amplifier is ensured to be normal. The design can avoid the problems of power consumption increase and the like caused by adopting an extra reference circuit in the traditional design.

The structure of the dc offset canceller is shown in fig. 8. The miller capacitance generated by Rb2 and Cb2 on the operational amplifier Opb1 forms the main pole of the loop, while the low pass filter formed by the miller capacitance generated by Rb1 and Cb1 on the operational amplifier Opb1 filters the a-point reference voltage. To produce high gain to reduce the size of Cb1 and Cb2, the op amp OPb1 requires a high impedance output. The operational amplifier Opb2 continuously amplifies the integrated difference between the reference voltage at point a and the varying voltage at point D, and outputs the voltage of Vdcoc to control NM5 in the pre-transimpedance amplifier and bypass all the dc components of the input signal. It should be noted that the output of the opamp OPb2 needs a lower impedance to ensure that the jitter at the input of the pre-transimpedance amplifier is not cross-talk to the dc offset cancellation loop through the parasitic capacitance of NM5 in the pre-transimpedance amplifier.

Other parts of this embodiment are the same as any of embodiments 1 to 13 described above, and thus are not described again.

Example 15:

in this embodiment, on the basis of any one of the above embodiments 1 to 14, in order to better implement the present invention, as shown in fig. 8, the dc offset canceller further includes a capacitor Cb3, and the capacitor Cb3 is grounded and then connected to the output end of the second operational amplifier OPb2 in a lap joint manner to serve as a stabilizing capacitor.

The working principle is as follows: the addition of capacitor Cb3 at the vdc node may also greatly reduce the jitter effects of high frequency signals on the control loop. Of course, after Cb3 is increased, the frequency of the main pole of the dc offset cancellation loop needs to be decreased continuously to ensure the loop is stable.

Other parts of this embodiment are the same as any of embodiments 1 to 14 described above, and thus are not described again.

Example 16:

in this embodiment, on the basis of any one of the above embodiments 1 to 15, as shown in fig. 9, fig. 10, fig. 11, fig. 12, fig. 13, fig. 14, fig. 15, fig. 16, and fig. 17, the simulation of the pre-transimpedance amplifier is schematically illustrated:

fig. 9, fig. 10, fig. 11, fig. 12, fig. 13, and fig. 14 are comparison diagrams of bandwidth simulations of the pre-transimpedance amplifier composed of the three-level inverter described in the patent and the pre-transimpedance amplifier composed of the conventional one-level inverter. Under the condition that the bandwidth of a photodiode is 3.5GHz, a preposed transimpedance amplifier formed by a traditional primary inverter is difficult to extend the bandwidth, and even if the preposed transimpedance amplifier is optimized, the current simulation is only about 3.1 GHz. The preposed transimpedance amplifier can greatly improve the fundamental frequency of 5GHz with the bandwidth exceeding 10Gbps input signals, simulate about 5.8GHz at present, and increase the transimpedance gain (6 dB) by more than one time to reduce the input equivalent noise.

Fig. 15, 16 and 17 are eye diagrams of output transient simulation of the pre-transimpedance amplifier. Because the bandwidth of the pre-transimpedance amplifier is enough, intersymbol interference is greatly reduced compared with the traditional design, and the transimpedance gain is larger than the traditional design, under the condition that the amplitude of input current signals is the same, the eye height of an eye pattern output by the pre-transimpedance amplifier in transient simulation is larger, an eye skin is thinner, and jitter is smaller. Thus, the design cost of the continuous-time equalizer and the trans-impedance amplifier of the later stage is greatly reduced.

Other parts of this embodiment are the same as any of embodiments 1 to 15, and thus are not described again.

Example 17:

in this embodiment, on the basis of any one of the above embodiments 1 to 16, in order to better implement the present invention, further, regarding the simulation of the automatic gain control, as shown in fig. 18, fig. 19, fig. 20, fig. 21, fig. 22, fig. 23, fig. 24, fig. 25, and fig. 26:

according to the patent, the automatic gain controller ensures that the output control signal Vagc can only be turned over once under the condition that the input signal strength meets the threshold value under reasonable control logic through the hysteresis of the comparator and the systematic hysteresis generated by different threshold values of the double detection points.

The automatic gain controller of the patent can ensure that the output control signal Vagc can only be turned over once under the condition that the input signal strength meets the threshold value under reasonable control logic through the hysteresis of the comparator and the systematic hysteresis generated by different threshold values of the double detection points.

Fig. 18, 19, 20, 21, 22 and 23 are simulated as the output comparison of the hysteresis comparator and the conventional non-hysteresis comparator in the automatic gain controller described in the patent. When the amplitude of the probe signal swings around the threshold voltage, the conventional non-hysteresis comparator generates large jitter, which causes the switching of Vagc, and the large jitter of the transition affects the signal quality by coupling the power supply and the ground to the high-speed signal link. In addition, logic misjudgment may be caused, and switching back and forth near the threshold value causes error. The hysteresis comparator avoids output jitter generated near the threshold, and the output control voltage Vagc is only switched once when the threshold requirement is met, thereby avoiding logic misjudgment.

As can be seen from fig. 24, 25, and 26 by scanning the swing of the current signal of the photodiode and monitoring the swing of the differential signal output from the transimpedance amplifier and the control voltage of the automatic gain controller Vagc, there is 6dB lag between the input signal amplitude when the high transimpedance value is switched to the low transimpedance value of 2x113 uop and the input signal amplitude when the low transimpedance value is switched to the high transimpedance value of 2x55 uop. Reasonable hysteresis avoids the effect of signal amplitude jitter on switching. Therefore, Vagc switches only once when the amplitude of the detection point meets the threshold requirement, and it is ensured that no error code is generated by switching back and forth at the switching point due to any amplitude jitter. Meanwhile, the input and output signals at the two switching points are large enough, the input signals are far away from the sensitivity range, the swing amplitude of the output signals exceeds 2x100mVpp at the switching points, good signal-to-noise ratio is ensured at the switching points, and error codes caused by too low signal-to-noise ratio are not easy to generate.

Other parts of this embodiment are the same as any of embodiments 1 to 16, and thus are not described again.

Example 18:

in this embodiment, on the basis of any one of the above embodiments 1 to 17, in order to better implement the present invention, further, regarding the simulation of the dc offset canceller, as shown in fig. 27, 28, and 29:

in the above description of the dc offset canceller design in the embodiment, it is mentioned that point a is used as a reference point in the loop, and the loop adjusts and changes the output point control voltage vdc by continuously amplifying and integrating the voltage difference between point a and point D at the beginning stage, ensuring that the average voltages at point a and point D are kept consistent after adjustment.

Fig. 27, 28, and 29 show simulation results of the dc offset cancellation function. When a current signal with direct current and alternating current components is suddenly input into the pre-transimpedance amplifier, the voltage at the point D is reduced because the voltage at the point A is stable because the direct current component generates voltage drop at the transimpedance position. The dc offset loop starts to work to boost the control voltage vdc by bypassing the dc component of the input signal, which reduces the voltage across the transimpedance, i.e., increases the average voltage at point D. When the average voltages at points a and D are consistent, the loop regulation is stopped and the control voltage vdc regulation is stopped and remains substantially stable. In fig. 28, the black signal is a voltage signal at a point a, and the gray signal is a voltage signal at a point D.

By a comprehensive consideration of the above examples 1 to 18, it can be concluded that: the low-cost high-speed over-frequency trans-impedance amplifier overcomes the performance loss caused by cost reduction, enhances the competitiveness of optical module manufacturers and communication equipment manufacturers, and assists the development of 5G communication construction.

It should be noted that fig. 9-29 are computer simulation interface screenshots, which fail to perfectly demonstrate simulation due to the limitation of picture size space, but fig. 9-29 are only experimental effect demonstration graphs, which do not substantially affect the technical solution described in the present application, and at the same time, the portions clearly shown in fig. 9-29 are sufficient to draw the conclusions in the embodiments 16, 17 and 18, so the applicant requests to retain fig. 9-29 as computer screenshot effect demonstration graphs to visually demonstrate the simulation effect.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications and equivalent variations of the above embodiments according to the technical spirit of the present invention are included in the scope of the present invention.

Claims

1. A low-cost super-frequency high-speed trans-impedance amplifier is connected with a photodiode and receives a current signal Iin sent by the photodiode, wherein the current signal Iin comprises a direct current component and an alternating current component; the system is characterized by comprising a high-speed communication link, a low-speed control circuit and a power management unit;

the direct current offset eliminator is connected with the input end and the output end of the feed-forward amplifier unit;

2. The low-cost over-frequency high-speed transimpedance amplifier according to claim 1, wherein said feed forward amplifier unit comprises a current processing unit, an inverter unit, a current mirror unit;

the current mirror unit is connected with the inverter unit;

3. The low-cost ultra-frequency high-speed transimpedance amplifier according to claim 2, wherein the inverter unit comprises three sets of combinations of inverters, namely a first inverter, a second inverter and a third inverter;

the feedback resistance unit is lapped on the pole A and the pole D;

4. The low-cost, ultra-high-frequency and high-speed transimpedance amplifier according to claim 3, wherein the inverter unit further comprises a resistor R1, one end of the resistor R1 is connected between the gates of the second PMOS transistor and the second NMOS transistor, and the other end of the resistor R1 is connected between the drains of the second PMOS transistor and the second NMOS transistor.

5. The low-cost over-frequency high-speed transimpedance amplifier according to claim 3, wherein the current processing unit comprises an inductor L1, a fifth NMOS transistor, a sixth NMOS transistor;

6. The low-cost over-frequency high-speed transimpedance amplifier according to claim 5, wherein said current processing unit further comprises a capacitor C4 and a resistor R5;

7. A low cost overclocking high speed transimpedance amplifier according to claim 3, wherein said feedback resistance unit comprises a resistor R2, a resistor R3, a resistor R4; the NMOS transistor also comprises a fourth NMOS transistor;

the source and the drain of the fourth NMOS transistor are respectively lapped at two ends of the resistor R3, and the gate of the fourth NMOS transistor is connected with the output end of the automatic gain controller; the resistor R2 and the resistor R4 are correspondingly connected with the pole A and the pole D or the resistor R2 and the resistor R4 are correspondingly connected with the pole D and the pole A.

8. A low-cost over-frequency high-speed transimpedance amplifier according to claim 3, 4, 5, 6 or 7, wherein said current mirror unit comprises a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a clamp OP 1;

9. The low-cost over-frequency high-speed transimpedance amplifier according to claim 8, wherein said current mirror unit further comprises a capacitor C1, a capacitor C2; the capacitor C1 is used as a filter capacitor, one end of the capacitor C1 is lapped on the input end of the power management unit, and the other end of the capacitor C1 is lapped between the grid electrode of the fourth PMOS tube and the grid electrode of the sixth PMOS tube;

10. A low cost, ultra-high frequency, high speed transimpedance amplifier according to claim 8, wherein said current mirror unit further comprises a capacitor C3;

11. A low cost overclocking high speed transimpedance amplifier according to claim 1 or 2 or 3 or 4 or 5 or 6 or 7, wherein said automatic gain controller comprises two digital output control channels and an automatic gain digital controller;

one digital output control channel comprises a common-mode voltage extraction unit, a threshold voltage generator, a peak detector and a hysteresis comparator; the common-mode voltage extraction unit is lapped between the two input ends of the peak detector and is used for extracting common-mode voltage; the common mode voltage extraction unit is also connected with the threshold voltage generator and used for sending the extracted common mode voltage to the threshold voltage generator to generate two paths of threshold values including a high threshold value and a low threshold value by setting a difference voltage; the high threshold and the low threshold represent the highest value and the lowest value after the difference between the difference voltage and the common mode voltage is obtained; the threshold voltage generator is connected with the peak detector and sends a threshold value of signal amplitude obtained by taking the difference between a high threshold value and a low threshold value to the hysteresis comparator; the hysteresis comparator is connected with the automatic gain digital controller;

12. The low-cost, ultra-frequency high-speed transimpedance amplifier according to claim 11, wherein said automatic gain digital controller comprises a not gate, an and gate, a fourth inverter, a fifth inverter;

13. The low-cost, ultra-frequency high-speed transimpedance amplifier according to claim 12, wherein said automatic gain digital controller further comprises a capacitor Ca 3; the capacitor Ca3 is grounded and then connected to the output end of the fifth inverter in a lap joint mode to serve as a filter capacitor.

14. A low cost, ultra-high frequency, high speed transimpedance amplifier according to claim 3, 4, 5, 6 or 7, wherein said dc offset canceller comprises a resistor Rb1, a resistor Rb2, a capacitor Cb1, a capacitor Cb2, a first operational amplifier OPb1, a second operational amplifier OPb 2;

15. The low-cost, ultra-high-speed transimpedance amplifier according to claim 14, wherein the dc offset canceller further comprises a capacitor Cb3, wherein the capacitor Cb3 is grounded and then connected to the output terminal of the second operational amplifier OPb2 as a stabilizing capacitor.