CN114038754B - A method for improving FinFET backside process - Google Patents

Abstract

The invention provides a method for improving FinFET wafer back process, forming a first oxide layer on the wafer back; forming a silicon nitride cushion layer on the first oxide layer; forming a first amorphous silicon layer on the silicon nitride cushion layer; removing the first amorphous silicon layer; forming a second amorphous silicon layer on the silicon nitride cushion layer; forming a first silicon nitride layer on the second amorphous silicon layer; forming a second silicon nitride layer on the first silicon nitride layer; removing the first and second silicon nitride layers, and exposing the second amorphous silicon layer; simultaneously depositing a second oxide layer on the front surface and the back surface of the wafer; removing the second oxide layer of the back of the wafer by using the second amorphous silicon layer as an etching barrier layer; simultaneously depositing polysilicon on the front surface and the back surface of the wafer; removing the polysilicon and the second amorphous silicon layer on the back of the wafer; the second silicon nitride layer is exposed. According to the invention, the amorphous silicon and the silicon nitride are deposited on the back of the crystal, so that the back of the crystal is smoother due to the blocking of the oxide layer of the back of the crystal, and the protection of the back of the crystal in the subsequent polysilicon process is facilitated.

Description

A method for improving FinFET backside process

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a method for improving FinFET back-end process.

Background technique

In the 7nm process, the Self-aligned Quad Patterning (SAQP) process is used, that is, two layers of amorphous silicon (Amorphous Si) and sidewall spacers are used for pattern transfer to complete the design of smaller FIN critical size CD; there are more film layers involved in the SAQP process, and more furnace tube processes are added compared to traditional photolithography and etching processes, resulting in more film layers on the back of the wafer. Subsequent processes will affect the flatness of the crystal back, and even seriously damage the crystal back, thus affecting the flatness of the photolithography.

Summary of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for improving the FinFET back-end process, so as to solve the problem in the prior art that the etching of the front oxide layer of the wafer etches the oxide layer of the back end to a certain extent, thereby causing damage to the substrate in the subsequent polysilicon process.

To achieve the above objectives and other related objectives, the present invention provides a method for improving FinFET backside process, which at least comprises:

Step 1: providing a wafer, forming a first oxide layer on the back of the wafer; and forming a silicon nitride pad layer on the first oxide layer;

Step 2: forming a first amorphous silicon layer on the silicon nitride pad layer;

Step 3: removing the first amorphous silicon layer;

Step 4: forming a second amorphous silicon layer on the silicon nitride pad layer;

Step 5: forming a first silicon nitride layer on the second amorphous silicon layer;

Step six, forming a second silicon nitride layer on the first silicon nitride layer;

Step 7: removing the first and second silicon nitride layers to expose the second amorphous silicon layer;

Step 8, depositing a second oxide layer on the front side and the back side of the wafer at the same time; using the second amorphous silicon layer as an etching barrier layer to remove the second oxide layer on the back side of the wafer;

Step nine: depositing polysilicon on the front and back of the wafer simultaneously; then removing the polysilicon and the second amorphous silicon layer on the back of the wafer; exposing the second silicon nitride layer.

Preferably, an epitaxial layer is formed on the backside of the wafer in step one, and the first oxide layer is formed on the epitaxial layer.

Preferably, the first oxide layer in step one is silicon oxide.

Preferably, the second oxide layer deposited in step eight is silicon oxide.

Preferably, the method is used in a process for a 7nm technology node.

Preferably, in step one, forming the first oxide layer adopts a furnace tube process.

Preferably, in step 2, the first amorphous silicon layer is formed by a furnace tube process.

Preferably, in step 4, the second amorphous silicon layer is formed by a furnace tube process.

Preferably, the first silicon nitride layer is formed in step five and the second silicon nitride layer is formed in step six by furnace tube processes respectively.

As described above, the method of improving the FinFET back-end process of the present invention has the following beneficial effects: the present invention deposits amorphous silicon and silicon nitride on the back-end to block the etching of the oxide layer of the back-end, making the back-end smoother, which is beneficial to the protection of the back-end in the subsequent polysilicon process.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram showing a structure after a first oxide layer, a silicon nitride pad layer and a first amorphous silicon layer are formed on a wafer back in the present invention;

FIG2 is a schematic diagram showing a structure after a second amorphous silicon layer and first and second silicon nitride layers are formed on a silicon nitride pad layer in the present invention;

FIG3 is a schematic diagram showing the structure after the first and second silicon nitride layers are removed in the present invention;

FIG4 is a schematic diagram showing the structure after the polysilicon and the second amorphous silicon layer on the back of the crystal are removed in the present invention;

FIG. 5 is a flow chart showing a method for improving FinFET backside process in the present invention.

Detailed ways

The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figures 1 to 5. It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention, and the drawings only show components related to the present invention rather than the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

The present invention provides a method for improving the backside process of FinFET, as shown in FIG5 , which is a flow chart of the method for improving the backside process of FinFET in the present invention, and the method at least comprises the following steps:

Step 1: Provide a wafer, form a first oxide layer on the back of the wafer, and form a silicon nitride pad layer on the first oxide layer; as shown in FIG1 , FIG1 is a schematic diagram of the structure after forming the first oxide layer, the silicon nitride pad layer and the first amorphous silicon layer on the back of the wafer in the present invention. In this step, the first oxide layer 02 is formed on the back of the wafer, and then the silicon nitride pad layer 03 is formed on the first oxide layer 02.

In the present invention, further, an epitaxial layer 01 is formed on the back of the wafer in step 1 of this embodiment, and the first oxide layer 02 is formed on the epitaxial layer 01 , that is, the first oxide layer 02 is formed on the surface of the epitaxial layer 01 .

According to the present invention, the first oxide layer 02 in step 1 of this embodiment is silicon oxide.

According to the present invention, in step 1 of this embodiment, the first oxide layer 02 is formed by a furnace tube process.

Step 2: forming a first amorphous silicon layer on the silicon nitride pad layer; as shown in FIG. 1 , in step 2, a first amorphous silicon layer 04 is formed on the silicon nitride pad layer 03 .

In the present invention, further, in step 2 of this embodiment, the first amorphous silicon layer 04 is formed by a furnace tube process.

Step 3: removing the first amorphous silicon layer;

Step 4: forming a second amorphous silicon layer on the silicon nitride pad layer; as shown in FIG2 , FIG2 is a schematic diagram of the structure after forming the second amorphous silicon layer and the first and second silicon nitride layers on the silicon nitride pad layer in the present invention. In step 4, a second amorphous silicon layer 05 is formed on the silicon nitride pad layer 03 .

In the present invention, further, in step 4 of this embodiment, the second amorphous silicon layer 05 is formed by a furnace tube process.

Step five, forming a first silicon nitride layer on the second amorphous silicon layer; as shown in FIG. 2 , in step five, the first silicon nitride layer 06 is formed on the second amorphous silicon layer.

In the present invention, further, the first silicon nitride layer is formed in step five of this embodiment and the second silicon nitride layer is formed in step six by furnace tube processes respectively.

Step six, forming a second silicon nitride layer on the first silicon nitride layer; as shown in FIG. 2 , in step six, the second silicon nitride layer 07 is formed on the first silicon nitride layer 06 .

Step 7: remove the first and second silicon nitride layers to expose the second amorphous silicon layer; as shown in FIG3, FIG3 is a schematic diagram of the structure after removing the first and second silicon nitride layers in the present invention. In step 7, the first and second silicon nitride layers are removed to expose the second amorphous silicon layer 05.

Step 8, depositing a second oxide layer on the front and back of the wafer at the same time; using the second amorphous silicon layer as an etching barrier to remove the second oxide layer on the back of the wafer; in step 8, the second oxide layer is first deposited on the front and back of the wafer at the same time, and the present invention further states that the second oxide layer deposited in step 8 of this embodiment is silicon oxide. Then, using the second amorphous silicon layer 05 as an etching barrier, the second oxide layer on the back of the wafer is etched away.

Step nine, depositing polysilicon on the front and back of the wafer at the same time; then removing the polysilicon and the second amorphous silicon layer on the back of the wafer; exposing the second silicon nitride layer. As shown in FIG. 4, FIG. 4 is a schematic diagram of the structure after removing the polysilicon and the second amorphous silicon layer on the back of the wafer in the present invention. In step nine, polysilicon is deposited on the front and back of the wafer at the same time; then removing the polysilicon and the second amorphous silicon layer 05 on the back of the wafer; exposing the second silicon nitride layer 03.

Furthermore, the method of this embodiment is used in the process of 7nm technology node.

In summary, the present invention deposits amorphous silicon and silicon nitride on the back of the crystal to block the oxide layer of the back of the crystal from being etched, making the back of the crystal smoother, which is beneficial to the protection of the back of the crystal in the subsequent polysilicon process. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims (9)

1. A method for improving FinFET back-of-wafer processing, comprising at least:

step one, providing a wafer, and forming a first oxide layer on the wafer back of the wafer; forming a silicon nitride cushion layer on the first oxide layer;

step two, forming a first amorphous silicon layer on the silicon nitride cushion layer;

Step three, removing the first amorphous silicon layer;

Step four, forming a second amorphous silicon layer on the silicon nitride cushion layer;

step five, forming a first silicon nitride layer on the second amorphous silicon layer;

step six, forming a second silicon nitride layer on the first silicon nitride layer;

step seven, removing the first silicon nitride layer and the second silicon nitride layer, and exposing the second amorphous silicon layer;

Step eight, depositing a second oxide layer on the front surface and the back surface of the wafer at the same time; removing the second oxide layer of the back of the wafer by using the second amorphous silicon layer as an etching barrier layer;

step nine, simultaneously depositing polysilicon on the front surface and the back surface of the wafer; removing the polysilicon and the second amorphous silicon layer of the back of the wafer; exposing the second silicon nitride layer.

2. The method of claim 1, wherein the FinFET back-of-wafer process is improved by: and in the first step, an epitaxial layer is formed on the wafer back of the wafer, and the first oxide layer is formed on the epitaxial layer.

3. The method of claim 1, wherein the FinFET back-of-wafer process is improved by: the first oxide layer in the first step is silicon oxide.

4. The method of claim 1, wherein the FinFET back-of-wafer process is improved by: the second oxide layer deposited in the step eight is silicon oxide.

5. The method of claim 1, wherein the FinFET back-of-wafer process is improved by: the method is used in a 7nm technology node process.

6. The method of claim 1, wherein the FinFET back-of-wafer process is improved by: in the first step, a furnace tube process is adopted for forming the first oxide layer.

7. The method of claim 1, wherein the FinFET back-of-wafer process is improved by: and step two, forming the first amorphous silicon layer by adopting a furnace tube process.

8. The method of claim 1, wherein the FinFET back-of-wafer process is improved by: and step four, forming the second amorphous silicon layer by adopting a furnace tube process.

9. The method of claim 1, wherein the FinFET back-of-wafer process is improved by: and step five, forming the first silicon nitride layer and forming the second silicon nitride layer in step six by adopting a furnace tube process respectively.