CN114023801A

CN114023801A - Display substrate, manufacturing method thereof and display device

Info

Publication number: CN114023801A
Application number: CN202111290594.0A
Authority: CN
Inventors: 董甜
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2019-10-29
Filing date: 2019-10-29
Publication date: 2022-02-08
Anticipated expiration: 2039-10-29
Also published as: CN110690265B; CN114023801B; CN110690265A

Abstract

A display substrate, a manufacturing method thereof, and a display device. The display substrate includes: a sub-pixel, a plurality of data lines and a plurality of power supply lines; the sub-pixel includes a driving circuit; the driving circuit includes a transistor and a capacitor; the display substrate includes a base and a The active layer, the first insulating layer, the first metal layer, the second insulating layer, the second metal layer, the third insulating layer and the third metal layer on the substrate; the second metal layer includes: the second electrode plate of the capacitor The second pole plate of the capacitor is connected with the second pole plate of the capacitor in the first adjacent drive circuit in the same row; the third insulating layer includes: the first via hole and the second via hole; the third metal layer includes: power cord; the power cord includes at least three power supply parts: a first power supply part, a second power supply part, and a third power supply part; the second power supply part connects the first power supply part and the third power supply part; the third metal layer passes through the first power supply part The hole is electrically connected to the second metal layer, and the third metal layer is electrically connected to the active layer of the transistor through the second via hole.

Description

Display substrate, manufacturing method thereof and display device

The application is a divisional application of application with application date of 2019, 10 and 29, application number of 201911038883.4 and invention name of 'a display substrate and a manufacturing method thereof, and a display device'.

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display substrate, a manufacturing method thereof, and a display device.

Background

An Organic Light-Emitting diode (OLED) Display substrate is a Display substrate different from a conventional Liquid Crystal Display (LCD), and has the advantages of active Light emission, good temperature characteristics, low power consumption, fast response, flexibility, ultra-lightness and thinness, low cost, and the like. And thus has become one of the important developments of the new generation of display devices and receives increasing attention.

In order to realize high-frequency driving of the OLED display substrate, a double-data-line OLED display substrate is proposed in the related art, that is, the same column of sub-pixels is connected to two data lines. However, in the OLED display substrate in the related art, the distances between the power connection lines respectively connected to the power lines and the sub-pixels in the same row and the data lines are short, so that the load of the data lines is large, and further, the power consumption of the OLED display substrate is large and the writing time of the data signals provided by the data lines is long.

Disclosure of Invention

The application provides a display substrate, a manufacturing method thereof and a display device, which reduce the load of a data line, further reduce the power consumption of the display substrate and shorten the writing time of a data signal.

In a first aspect, the present application provides a display substrate comprising: the array-arranged sub-pixels comprise sub-pixels arranged in an array, a plurality of data lines and a plurality of power lines; at least one of the sub-pixels includes: a drive circuit; the drive circuit includes: a transistor and a capacitor; the capacitor includes: first polar plate and the second polar plate of relative setting, display substrate includes: the semiconductor device comprises a substrate, and an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer which are sequentially stacked on the substrate;

the active layer includes: an active layer of transistors in at least one driver circuit;

the first metal layer includes: a first plate of a capacitor;

the second metal layer includes: a second plate of the capacitor; the second polar plate of the capacitor in the driving circuit is connected with the second polar plate of the capacitor in the first adjacent driving circuit in the same row;

the third insulating layer includes: a first via and a second via;

the third metal layer includes: a power line; the power cord includes at least three power sections: a first power supply unit, a second power supply unit, and a third power supply unit; the second power supply part is connected with the first power supply part and the third power supply part; the data line is arranged in parallel with the extending direction of the first power supply part and the second power supply part;

the third metal layer is electrically connected with the second metal layer through the first via hole, and the third metal layer is electrically connected with the active layer of the transistor through the second via hole.

In some possible implementations, the driving circuit includes: first to seventh transistors, wherein a first pole of the fifth transistor is connected to a power supply line, and an active layer of the transistor in the at least one driving circuit includes: an active layer, an active layer protrusion, and a power supply connection part of the first to seventh transistors; the active layer of the at least one transistor comprises: the transistor comprises a channel part, a first conductor part and a second conductor part, wherein the first conductor part and the second conductor part are respectively positioned on two sides of the channel part;

for at least one driving circuit, the first conductor part of the fifth transistor is respectively connected with the active layer bump and the power supply connecting part, wherein the first conductor part, the active layer bump and the power supply connecting part of the fifth transistor are set to be written with a power supply signal, and the power supply signal is a signal of a power supply line.

In some possible implementations, for the at least one driving circuit, the active layer bump and the power supply connection part are respectively located at both sides of the first conductor part of the fifth transistor.

In some possible implementations, the active layer protrusion is located on a side of the first conductor portion of the fifth transistor away from the active layer of the sixth transistor, and the power supply connection portion is located on a side of the first conductor portion of the fifth transistor close to the active layer of the sixth transistor.

In some possible implementations, the active layer bump in at least one drive circuit is connected with an active layer bump in a second adjacent drive circuit in the same row.

In some possible implementations, the power line is electrically connected to the power connection portion through the second via.

In some possible implementations, the second metal layer further includes: connecting the electrodes; the second power supply portion is connected with the connecting electrode through a first through hole, and the third power supply portion is connected with the second plate of the capacitor through the first through hole.

In some possible implementations, the first metal layer further includes: a plurality of gate lines, a plurality of reset signal lines and a plurality of light emission control signal lines;

the orthographic projection of the first power supply part on the substrate is superposed with the orthographic projection of the initial signal line and the reset signal line on the substrate;

the orthographic projection of the second power supply part on the substrate does not have an overlapping region with the orthographic projection of the second plate of the capacitor and the orthographic projection of the grid line on the substrate, and the orthographic projection of the second power supply part on the substrate at least partially overlaps with the orthographic projection of the connecting electrode and the active layer of the first transistor on the substrate;

the orthographic projection of the third power supply part on the substrate is at least partially overlapped with the orthographic projection of the grid line, the second substrate of the capacitor and the light-emitting control signal on the substrate.

In some possible implementations, the first insulating layer, the second insulating layer, and the third insulating layer are provided with a sixth via hole exposing the first conductor portion of the active layer of the sixth transistor;

for at least one driving circuit, the dummy line of the first power supply portion passes through the sixth via.

In some possible implementations, the second metal layer further includes: the first insulating layer, the second insulating layer and the third insulating layer are further provided with a third via hole exposing the second conductor part of the active layer of the seventh transistor, and the third insulating layer is further provided with an eighth via hole exposing the initial signal line;

for at least one driving circuit, the dummy line of the third power supply portion passes through a portion of the third via and the eighth via.

In some possible implementations, an included angle between the first power supply part and the second power supply part is greater than or equal to 90 degrees and less than 180 degrees;

the included angle between the second power supply part and the third power supply part is larger than or equal to 90 degrees and smaller than 180 degrees.

In some possible implementations, a width of the first power supply portion is equal to or greater than a width of the third power supply portion;

the width of the first power supply part is greater than or equal to the width of the second power supply part.

In some possible implementations, the data line is located in the third metal layer.

In some possible implementations, the data line includes: a first sub data line and a second sub data line; the first sub data line and the second sub data line are respectively positioned at two sides of the power line;

for the ith row driving circuit, the distance between the first power supply part and the first sub data line is greater than the distance between the first power supply part and the second sub data line, and the distance between the third power supply part and the first sub data line is less than the distance between the third power supply part and the second sub data line;

for the (i + 1) th row driving circuit, the distance between the first power supply part and the first sub data line is smaller than the distance between the first power supply part and the second sub data line, and the distance between the third power supply part and the first sub data line is larger than the distance between the third power supply part and the second sub data line.

In some possible implementations, the pixel structures of the neighboring sub-pixels are symmetrically arranged along a center line of the pixel structures of the neighboring sub-pixels.

In some possible implementations, the adjacent power lines are symmetrically arranged along a center line between the adjacent power lines.

In some possible implementations, for at least one driver circuit, the second plate of the capacitor includes: a main body portion and a protrusion portion formed integrally;

the projection part is positioned on one side of the main body part, and the orthographic projection of the projection part on the substrate is at least partially overlapped with the orthographic projection of the active layer of the sixth transistor on the substrate;

the orthographic projection of the main body part on the substrate is partially overlapped with the orthographic projection of the first polar plate on the substrate, and the main body part is provided with a through hole exposing the first polar plate of the capacitor.

In some possible implementations, the connection electrode includes: the first connecting part and the second connecting part are integrally formed;

the extending direction of the first connecting part is the same as that of the data line, and the extending direction of the second connecting part is the same as that of the grid line;

an orthographic projection of the first connecting part on the substrate at least partially overlaps an orthographic projection of an active layer of the second transistor on the substrate, and the second connecting part at least partially overlaps an orthographic projection of the active layer of the first transistor on the substrate;

the dummy line of the first connection portion passes through the protrusion of the second plate of the capacitor.

In some possible implementations, the first metal layer further includes: a gate electrode of a second transistor, the gate electrode of the second transistor being integrally formed with the gate line, the gate electrode of the second transistor including: a first branch section and a second branch section connected to each other;

the extending direction of the first branch section is the same as that of the data line, and the extending direction of the second branch section is the same as that of the grid line;

the dummy line of the first branch section passes through the second connection portion of the connection electrode.

In some possible implementations, at least one driving circuit located in the ith row is connected to the first sub data line;

at least one driving circuit positioned in the (i + 1) th row is connected with the second sub data line; i is more than or equal to 1 and less than or equal to M, and i is an odd number.

In some possible implementations, the t-th power line and the t + 1-th power line include: a first sub data line of a t-th data line and a first sub data line of a t + 1-th data line, or a second sub data line of the t-th data line and a second sub data line of the t + 1-th data line.

In some possible implementation manners, a first sub data line of a jth data line is located at one side of a jth power line close to a j-1 th column of driving circuits, and a second sub data line of the jth data line is located at one side of the jth power line close to a j +1 th column of driving circuits;

the first subdata line of the (j + 1) th data line is positioned on one side of the (j + 1) th power line close to the (j + 2) th column driving circuit, the second subdata line of the (j + 1) th data line is positioned on one side of the (j + 1) th power line close to the (j + 2) th column driving circuit, j is more than or equal to 1 and is less than or equal to N, and j is an odd number.

In some possible implementations, orthographic projections of the first sub data line and the second sub data line on a substrate at least partially overlap with orthographic projections of the initial signal line, the reset signal line, the gate line and the light-emitting control signal line on the substrate.

In some possible implementations, a width of the first power supply part is greater than a width of the first sub data line and greater than a width of the second sub data line.

In some possible implementations, for at least one of the driving circuits, the active layers of all the transistors are of an integrally formed structure;

the active layer of the sixth transistor of the driving circuit positioned in the s-th row and the t-th column is connected with the active layer of the seventh transistor of the driving circuit positioned in the s + 1-th row and the t-th column; s is more than or equal to 1 and less than or equal to M, t is more than or equal to 1 and less than or equal to N, M is the row number of the driving circuit, and N is the column number of the driving circuit;

the active layer bulge of the driving circuit positioned in the ith row and the jth +1 column is connected with the active layer bulge of the driving circuit positioned in the ith row and the jth +2 column; the active layer bulge of the driving circuit positioned in the (i + 1) th row and the (j) th column is connected with the active layer bulge positioned in the (i + 1) th row and the (j + 1) th column; i is more than or equal to 1 and less than or equal to M, j is more than or equal to 1 and less than or equal to N, and i and j are odd numbers.

In some possible implementations, the first plate of the capacitor includes: a first side and a second side disposed opposite; for at least one driving circuit, the grid line and the reset signal line are positioned on the first side of the first polar plate of the capacitor, the reset signal line is positioned on one side of the grid line far away from the first polar plate of the capacitor, and the light-emitting control signal line is positioned on the second side of the first polar plate of the capacitor;

the first metal layer further includes: a gate electrode of the first transistor to a gate electrode of the seventh transistor, the gate electrode of the first transistor straddling over an active layer of the first transistor, the gate electrode of the second transistor straddling over an active layer of the second transistor, the gate electrode of the third transistor straddling over an active layer of the third transistor, the gate electrode of the fourth transistor straddling over an active layer of the fourth transistor, the gate electrode of the fifth transistor straddling over an active layer of the fifth transistor, the gate electrode of the sixth transistor straddling over an active layer of the sixth transistor, and the gate electrode of the seventh transistor straddling over an active layer of the seventh transistor;

the gate electrode of the first transistor, the gate electrode of the seventh transistor and the reset signal line are of an integrally formed structure, the gate electrode of the second transistor, the gate electrode of the fourth transistor and the gate line are of an integrally formed structure, the gate electrode of the third transistor and the first electrode plate of the capacitor are of an integrally formed structure, and the gate electrode of the fifth transistor, the gate electrode of the sixth transistor and the light-emitting control signal line are of an integrally formed structure.

In some possible implementation manners, for at least one driving circuit, the first insulating layer, the second insulating layer, and the third insulating layer are further provided with a fourth via hole and a fifth via hole, and the second insulating layer and the third insulating layer are provided with a seventh via hole;

the fourth via hole exposes the active layer of the fourth transistor, the fifth via hole exposes the active layer of the second transistor, the sixth via hole exposes the active layer of the sixth transistor, and the seventh via hole exposes the first plate of the capacitor.

In some possible implementations, the third metal layer further includes: a first pole and a second pole of the first transistor, a first pole and a second pole of the second transistor, a first pole of the fourth transistor, a second pole of the fifth transistor, a second pole of the sixth transistor, a first pole and a second pole of the seventh transistor;

for at least one driving circuit, the second pole of the first transistor and the second pole of the seventh transistor are in an integrated structure, and the orthographic projection of the second pole of the first transistor on the substrate is at least partially overlapped with the orthographic projection of the active layer of the seventh transistor, the initial signal line and the reset signal line on the substrate;

the first pole of the first transistor and the second pole of the second transistor are in an integrated structure, and the orthographic projection of the first pole of the first transistor on the substrate is at least partially overlapped with the orthographic projection of the active layer and the grid line of the second transistor on the substrate;

the second pole of the sixth transistor and the second pole of the seventh transistor are in an integrated structure, and the orthographic projection of the second pole of the sixth transistor on the substrate is at least partially overlapped with the orthographic projection of the light-emitting control signal line on the substrate;

the first electrode of the fourth transistor of the driving circuit positioned in the ith row and the first sub data line are in an integrally formed structure, the first electrode of the fourth transistor of the driving circuit positioned in the (i + 1) th row and the second sub data line are in an integrally formed structure, and the orthographic projection of the first electrode of the fourth transistor on the substrate is at least partially overlapped with the orthographic projection of the active layer of the fourth transistor on the substrate.

In some possible implementations, an orthographic projection of the dummy line of the first pole of the fourth transistor on the substrate protrudes through the active layer.

In some possible implementations, there is an overlapping area between an orthographic projection of the second pole of the second transistor on the substrate and an orthographic projection of the seventh via on the substrate;

the dummy line of the second pole of the second transistor passes through the second power supply section.

In a second aspect, the present application further provides a display device, including the above display substrate, a timing controller, a data driver, a scan driver, and a light emitting driver; the display substrate includes: data lines, gate lines and light emission control signal lines;

the time sequence controller is respectively electrically connected with the data driver, the scanning driver and the light-emitting driver;

the data driver is connected with the data lines, the scanning driver is connected with the grid lines, and the light-emitting driver is connected with the light-emitting control signal lines.

In a third aspect, the present application further provides a method for manufacturing a display substrate, for manufacturing the display substrate, the method including:

providing a substrate;

an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer are sequentially formed on a substrate.

The embodiment of the application provides a display substrate, a manufacturing method thereof and a display device, wherein the display substrate comprises: the array-arranged sub-pixels comprise sub-pixels arranged in an array, a plurality of data lines and a plurality of power lines; at least one of the sub-pixels includes: a drive circuit; the drive circuit includes: a transistor and a capacitor; the capacitor includes: first polar plate and the second polar plate of relative setting, the display substrates includes: the semiconductor device comprises a substrate, and an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer which are sequentially stacked on the substrate; the active layer includes: an active layer of transistors in at least one driver circuit; the first metal layer includes: a first plate of a capacitor; the second metal layer includes: a second plate of the capacitor; the second polar plate of the capacitor in the driving circuit is connected with the second polar plate of the capacitor in the first adjacent driving circuit in the same row; the third insulating layer includes: a first via and a second via; the third metal layer includes: a power line; the power cord includes at least three power sections: a first power supply unit, a second power supply unit, and a third power supply unit; the second power supply part is connected with the first power supply part and the third power supply part; the data line is arranged in parallel with the extending direction of the first power supply part and the second power supply part; the third metal layer is electrically connected with the second metal layer through the first via hole, and the third metal layer is electrically connected with the active layer of the transistor through the second via hole, so that the distance between a part of power lines and the data lines is increased, the load of the data lines is reduced, the power consumption of the display substrate is reduced, and the writing time of data signals is shortened.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification, claims, and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

FIG. 2 is a top view of a plurality of sub-pixels according to an embodiment of the present disclosure;

FIG. 3 is a side view of a plurality of sub-pixels provided by an embodiment of the present application;

fig. 4 is an equivalent circuit diagram of a driving circuit provided in an embodiment of the present application;

FIG. 5 is a partial top view of a subpixel in a display substrate according to embodiments of the present disclosure;

FIG. 6 is a top view of another portion of a subpixel in a display substrate according to an embodiment of the present disclosure;

FIG. 7 is a top view of a portion of a subpixel in a display substrate according to an embodiment of the present disclosure;

fig. 8 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the present disclosure;

fig. 9 is a schematic view illustrating an active layer of a display substrate according to an embodiment of the present disclosure;

fig. 10 is a schematic view illustrating a first insulating layer and a first metal layer of a display substrate according to an embodiment of the present disclosure;

fig. 11 is a schematic view illustrating a second insulating layer and a second metal layer of a display substrate according to an embodiment of the disclosure;

fig. 12 is a schematic view illustrating a third insulating layer according to an embodiment of the present disclosure.

Detailed Description

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

Unless defined otherwise, technical or scientific terms used in the disclosure of the embodiments of the present invention should have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar language in the embodiments of the present invention does not denote any order, quantity, or importance, but rather the terms "first," "second," and similar language are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The related art OLED display substrate includes a plurality of sub-pixels, power lines, and data lines. Each sub-pixel includes: the capacitor comprises a first polar plate and a second polar plate which are oppositely arranged, wherein the second polar plate of the capacitor is connected with a power line, the second polar plates of the capacitors of adjacent sub-pixels are mutually connected, and the power line and the data line are arranged on the same layer.

In the OLED display substrate in the related art, the second plates of the capacitors of all the sub-pixels in the same row are multiplexed as the power connection line, so that the power signals provided by the power lines in each sub-pixel are the same, and the display failure of the OLED display substrate is avoided. Specifically, the extending direction of the power connecting line is perpendicular to the extending direction of the data line, but because the overlapping area between the power connecting line and the data line is large, and the distance between the power connecting line and the data line is short, the load of the data line is large, and further the power consumption of the OLED display substrate is large and the writing time of the data signal provided by the data line is long.

In order to solve the above technical problem, embodiments of the present application provide a display substrate, a manufacturing method thereof, and a display device, which are specifically described as follows:

a display substrate, comprising: the array-arranged sub-pixels comprise sub-pixels arranged in an array, a plurality of data lines and a plurality of power lines; at least one of the sub-pixels includes: a drive circuit; the drive circuit includes: a transistor and a capacitor; the capacitor includes: first polar plate and the second polar plate of relative setting, display substrate includes: the semiconductor device comprises a substrate, and an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer which are sequentially stacked on the substrate;

the first metal layer includes: a first plate of a capacitor;

the third insulating layer includes: a first via and a second via;

In one exemplary embodiment, the driving circuit includes: first to seventh transistors, wherein a first pole of the fifth transistor is connected to a power supply line, and an active layer of the transistor in the at least one driving circuit includes: an active layer, an active layer protrusion, and a power supply connection part of the first to seventh transistors; the active layer of the at least one transistor comprises: the transistor comprises a channel part, a first conductor part and a second conductor part, wherein the first conductor part and the second conductor part are respectively positioned on two sides of the channel part;

In one exemplary embodiment, for the at least one driving circuit, the active layer bump and the power supply connection portion are respectively located at both sides of the first conductor portion of the fifth transistor.

In one exemplary embodiment, the active layer protrusion is located at a side of the first conductor portion of the fifth transistor, which is away from the active layer of the sixth transistor, and the power supply connection portion is located at a side of the first conductor portion of the fifth transistor, which is close to the active layer of the sixth transistor.

In one exemplary embodiment, the active layer bump in at least one drive circuit is connected with the active layer bump in a second adjacent drive circuit in the same row.

In an exemplary embodiment, the power line is electrically connected to the power connection part through the second via hole.

In one exemplary embodiment, the second metal layer further includes: connecting the electrodes; the second power supply portion is connected with the connecting electrode through a first through hole, and the third power supply portion is connected with the second plate of the capacitor through the first through hole.

In one exemplary embodiment, the first metal layer further includes: a plurality of gate lines, a plurality of reset signal lines and a plurality of light emission control signal lines;

In an exemplary embodiment, the first insulating layer, the second insulating layer and the third insulating layer are provided with a sixth via hole exposing the first conductor portion of the active layer of the sixth transistor;

In one exemplary embodiment, the second metal layer further includes: the first insulating layer, the second insulating layer and the third insulating layer are further provided with a third via hole exposing the second conductor part of the active layer of the seventh transistor, and the third insulating layer is further provided with an eighth via hole exposing the initial signal line;

In an exemplary embodiment, an included angle between the first power supply part and the second power supply part is greater than or equal to 90 degrees and less than 180 degrees;

In one exemplary embodiment, the width of the first power supply part is equal to or greater than the width of the third power supply part;

In one exemplary embodiment, the data line is located at the third metal layer.

In one exemplary embodiment, the data line includes: a first sub data line and a second sub data line; the first sub data line and the second sub data line are respectively positioned at two sides of the power line;

In one exemplary embodiment, the pixel structures of the neighboring sub-pixels are symmetrically disposed along a center line of the pixel structures of the neighboring sub-pixels.

In an exemplary embodiment, the adjacent power lines are symmetrically disposed along a center line between the adjacent power lines.

In an exemplary embodiment, for at least one driver circuit, the second plate of the capacitor comprises: a main body portion and a protrusion portion formed integrally;

In one exemplary embodiment, the connection electrode includes: the first connecting part and the second connecting part are integrally formed;

In one exemplary embodiment, the first metal layer further includes: a gate electrode of a second transistor, the gate electrode of the second transistor being integrally formed with the gate line, the gate electrode of the second transistor including: a first branch section and a second branch section connected to each other;

In one exemplary embodiment, at least one driving circuit located at the ith row is connected to the first sub data line;

In an exemplary embodiment, the t-th power line and the t + 1-th power line include therebetween: a first sub data line of a t-th data line and a first sub data line of a t + 1-th data line, or a second sub data line of the t-th data line and a second sub data line of the t + 1-th data line.

In an exemplary embodiment, a first sub data line of a jth data line is positioned on one side of a jth power line close to a j-1 th column driving circuit, and a second sub data line of the jth data line is positioned on one side of the jth power line close to a j +1 th column driving circuit;

In an exemplary embodiment, orthographic projections of the first sub data line and the second sub data line on a substrate at least partially overlap with orthographic projections of the initial signal line, the reset signal line, the gate line and the light emission control signal line on the substrate.

In one exemplary embodiment, the first power supply part has a width greater than that of the first sub data line and greater than that of the second sub data line.

In one exemplary embodiment, for at least one driving circuit, the active layers of all the transistors are of an integrally molded structure;

In one exemplary embodiment, the first plate of the capacitor includes: a first side and a second side disposed opposite; for at least one driving circuit, the grid line and the reset signal line are positioned on the first side of the first polar plate of the capacitor, the reset signal line is positioned on one side of the grid line far away from the first polar plate of the capacitor, and the light-emitting control signal line is positioned on the second side of the first polar plate of the capacitor;

the gate electrode of the first transistor, the gate electrode of the seventh transistor and the reset signal line are of an integrally formed structure, and the gate electrode of the second transistor, the gate electrode of the fourth transistor and the gate line are of an integrally formed structure. The gate electrode of the third transistor and the first plate of the capacitor are of an integrally formed structure, and the gate electrode of the fifth transistor, the gate electrode of the sixth transistor and the light-emitting control signal line are of an integrally formed structure.

In an exemplary embodiment, for at least one driving circuit, the first insulating layer, the second insulating layer and the third insulating layer are further opened with a fourth via and a fifth via, and the second insulating layer and the third insulating layer are opened with a seventh via;

In one exemplary embodiment, the third metal layer further includes: a first pole and a second pole of the first transistor, a first pole and a second pole of the second transistor, a first pole of the fourth transistor, a second pole of the fifth transistor, a second pole of the sixth transistor, a first pole and a second pole of the seventh transistor;

In one exemplary embodiment, an orthographic projection of the dummy line of the first pole of the fourth transistor on the substrate protrudes through the active layer.

In an exemplary embodiment, an overlapping region exists between an orthographic projection of the second pole of the second transistor on the substrate and an orthographic projection of the seventh via hole on the substrate;

Some embodiments of the present application provide a display substrate, fig. 1 is a schematic structural diagram of the display substrate provided in the embodiments of the present application, fig. 2 is a top view of a plurality of sub-pixels provided in the embodiments of the present application, and fig. 3 is a side view of the plurality of sub-pixels provided in the embodiments of the present application, as shown in fig. 1 to 3, the display substrate provided in the embodiments of the present application includes: the liquid crystal display device includes a substrate 10, and a plurality of sub-pixels P, a plurality of columns of power lines VDD and data lines D disposed on the same layer as the power lines VDD on the substrate 10, wherein each sub-pixel P includes: a drive circuit; the drive circuit includes: a transistor and a capacitor, the capacitor comprising: the first plate C1 and the second plate C2 are oppositely arranged, the active layer 20 of the transistor is positioned on one side of the second plate C2 of the capacitor close to the substrate 10, and the power line VDD is positioned on one side of the second plate C2 of the capacitor far away from the substrate 10.

Specifically, for each sub-pixel, the power supply line VDD is connected to the second plate C2 of the capacitor and the active layer 20 of the transistor, respectively, the second plate C2 of the capacitor of each sub-pixel is connected to the second plate C2 of the capacitor of one adjacent sub-pixel located in the same row, and the active layer 20 of the transistor of each sub-pixel is connected to the active layer 20 of the transistor of another adjacent sub-pixel located in the same row. Fig. 2 illustrates an example of 8 sub-pixels.

Specifically, as shown in fig. 1, the display substrate in this embodiment includes M rows and N columns of sub-pixels, N columns of data lines D1-DN, N columns of power lines VDD 1-VDDN, M rows of gate lines G1-GM, M-1 rows of light emission control signal lines EM 1-EMM-1, M rows of Reset signal lines Reset, and M rows of initial signal lines Vinit, and further includes: a data driver for supplying data signals to the data lines, a scan driver for supplying scan signals to the gate lines, a light emission driver for supplying light emission control signals to the light emission control signal lines, and a timing controller for supplying driving signals to the data driver, the scan driver, and the light emission driver.

Optionally, as can be seen from fig. 1 and fig. 2, the ith column of sub-pixels is connected to the ith column of data lines and the ith column of power lines, and 1 ≦ i ≦ N.

Each column of data lines includes: the first sub data line DOi and the second sub data line DEi in the ith column of data line Di are respectively located at two sides of the ith column of sub-pixels, the ith column of power supply line VDDi is located between the first sub data line DOi and the second sub data line DEi in the ith column of data line Di, and fig. 2 illustrates two rows of sub-pixels before four columns.

Specifically, as shown in fig. 1 and 2, adjacent sub-pixels in the same column are connected to different sub-data lines, that is, if the sub-pixel in the ith row and the jth column is connected to the first sub-data line DOj in the jth column data line, the sub-pixel in the (i + 1) th row and the jth column is connected to the second sub-data line DEj in the jth column data line, and if the sub-pixel in the ith row and the jth column is connected to the second sub-data line DEj in the jth column data line, the sub-pixel in the (i + 1) th row and the jth column is connected to the first sub-data line DOj in the jth column data line.

In this embodiment, the first sub data line and the second sub data line in adjacent data lines are arranged in opposite ways, that is, when the first sub data line DOi of the ith column of data line Di is located at the first side of the ith column of sub-pixels and the second sub data line DEi of the ith column of data line Di is located at the second side of the ith column of sub-pixels, the second sub data line DEi +1 of the (i + 1) th column of data line Di +1 is located at the first side of the (i + 1) th column of sub-pixels, and the first sub data line DOi +1 of the (i + 1) th column of data line Di +1 is located at the second side of the (i + 1) th column of sub-pixels; or when the first sub data line DOi of the ith column of data line Di is located at the second side of the ith column of sub-pixels, and the second sub data line DEi of the ith column of data line Di is located at the first side of the ith column of sub-pixels, the second sub data line DEi +1 of the (i + 1) th column of data line Di +1 is located at the second side of the (i + 1) th column of sub-pixels, and the first sub data line DOi +1 of the (i + 1) th column of data line Di +1 is located at the first side of the (i + 1) th column of sub-pixels.

Fig. 4 is an equivalent circuit diagram of a driving circuit provided in an embodiment of the present application, and as shown in fig. 4, fig. 4 illustrates a driving circuit included in an ith column sub-pixel and an (i + 1) th column sub-pixel as an example, the driving circuit provided in the embodiment of the present application has a 7T1C structure, and includes a first transistor T1 to a seventh transistor T7 and a capacitor C, where the capacitor C includes a first plate C1 and a second plate C2.

Specifically, the gate electrode of the first transistor T1 is connected to the Reset signal line Reset, the source electrode of the first transistor T1 is connected to the initial signal line Vinit, the drain electrode of the first transistor T1 is connected to the first plate C1 of the capacitor C, the gate electrode of the second transistor T2 is connected to the gate line G, the source electrode of the second transistor T2 is connected to the first plate C1 of the capacitor C, the drain electrode of the second transistor T2 is connected to the drain electrode of the sixth transistor T6, the gate electrode of the third transistor T3 is connected to the first plate C1 of the capacitor C, the source electrode of the third transistor T3 is connected to the drain electrode of the fourth transistor T4, the drain electrode of the third transistor T3 is connected to the drain electrode of the sixth transistor T6, the gate electrode of the fourth transistor T4 is connected to the gate line G, the source electrode of the fourth transistor T4 is connected to the data line D, and the gate electrode of the fifth transistor T5 is connected to the emission control signal line EM, a source electrode of the fifth transistor T5 is connected to the power supply line VDD, a drain electrode of the fifth transistor T5 is connected to the source electrode of the third transistor T3, a gate electrode of the sixth transistor T6 is connected to the emission control signal line EM, a drain electrode of the sixth transistor T6 is connected to the anode of the light emitting device, a gate electrode of the seventh transistor T7 is connected to the Reset signal line Reset, a source electrode of the seventh transistor T7 is connected to the initial signal line Vinit, a drain electrode of the seventh transistor T7 is connected to the anode of the light emitting device, the second plate C2 of the capacitor is connected to the power supply line VDD, and the cathode of the light emitting device OLED is connected to the low-level power supply terminal VSS.

The third transistor T3 is a driving transistor, and the other transistors except the third transistor T3 are switching transistors, and the first transistor T1 to the seventh transistor T7 provided in this embodiment may all be P-type transistors or N-type transistors, which is not limited in this embodiment of the present invention.

Specifically, the general operation process of the driving circuit includes: the light emitting device comprises a driving circuit, a reset signal line, a gate line, a light emitting control signal line and a light emitting device, wherein the driving circuit comprises a driving circuit, the light emitting control signal line comprises a data line and a data line, the data line comprises a data line, the data line and the light emitting control signal line comprises a data line.

Specifically, as shown in fig. 2 and fig. 3, the display substrate provided in the embodiment of the present application further includes: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a gate line G, a Reset signal line Reset, a light emission control signal line EM, and an initial signal line Vinit, which are sequentially disposed on the substrate 10.

The gate line G, the Reset signal line Reset, the emission control signal line EM, the first electrode plate C1 of the capacitor, and the gate electrode of the transistor are disposed in the same layer, the second electrode plate C2 of the capacitor and the initial signal line Vinit are disposed in the same layer, and the data line D, the power supply VDD line, and the source/drain electrode of the transistor are disposed in the same layer.

Wherein the first insulating layer 11 is disposed between the active layer 20 of the transistor and the gate electrode of the transistor, the second insulating layer 12 is disposed between the gate electrode of the transistor and the second plate C2 of the capacitor, and the third insulating layer 13 is disposed between the second plate C2 of the capacitor and the data line.

Alternatively, the base 10 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass, metal sheet; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

Optionally, the gate electrode of the transistor, the source/drain electrode of the transistor, the data line D, and the power line VDD are all made of metal, for example, metal materials such as silver, aluminum, or copper may be used, and this is not limited in this embodiment of the present application.

Optionally, the active layer 20 is made of polysilicon, which is not limited in this embodiment.

According to the display substrate, the second plates of the capacitors connected with each other and the active layers of the transistors connected with each other ensure that power signals provided by the power lines of all the sub-pixels in the same row are the same, poor display of the display substrate is avoided, and the display effect of the display substrate is ensured.

The display substrate provided by the embodiment of the application comprises: the liquid crystal display panel comprises a substrate, a plurality of sub-pixels arranged on the substrate, a plurality of columns of power lines and data lines arranged on the same layer with the power lines, wherein each sub-pixel comprises: a drive circuit; the drive circuit includes: a transistor and a capacitor; the capacitor includes: the first polar plate and the second polar plate are oppositely arranged; the active layer of the transistor is positioned on one side of the second plate of the capacitor close to the substrate, and the power line is positioned on one side of the second plate of the capacitor far away from the substrate; for each sub-pixel, the power line is respectively connected with the second polar plate of the capacitor and the active layer of the transistor, the second polar plate of the capacitor of each sub-pixel is connected with the second polar plate of the capacitor of one adjacent sub-pixel in the same row, and the active layer of the transistor of each sub-pixel is connected with the active layer of the transistor of the other adjacent sub-pixel in the same row. The second polar plate through the electric capacity and the active layer of transistor multiplex for the power signal of power connecting wire transmission power cord, because the distance of the active layer of transistor and data line is far away than the distance between the second polar plate of electric capacity and the data line, consequently, the technical scheme that this application provided has increased the distance between partial power connecting wire and the data line, has reduced the load of data line, and then has reduced the consumption of display substrate and has shortened data signal's write-in time.

Alternatively, in the present embodiment, as shown in fig. 2, the active layers 20 of adjacent sub-pixels located in the same column are connected to each other.

Alternatively, as shown in fig. 2, the pixel structure of the sub-pixel located in the ith row and the jth column is the same as the pixel structure of the sub-pixel located in the (i + 1) th row and the (j + 1) th column.

As shown in fig. 2, adjacent power lines are symmetrical to each other, and specifically, the i-th column power line VDDi and the i + 1-th column power line VDDi +1 are arranged symmetrically along the extending direction of the data line. In the embodiment of the present application, the power line VDD is a zigzag.

Specifically, as shown in fig. 2, in the display substrate provided in the embodiment of the present application, each pixel includes: four sub-pixels, the pixel comprising: a first pixel and a second pixel.

In the first pixel, the second plate of the capacitor in the ith sub-pixel is connected with the second plate of the capacitor in the (i + 1) th sub-pixel, the active layer of the transistor in the ith sub-pixel is disconnected from the active layer of the transistor in the (i + 1) th sub-pixel, the active layer of the transistor in the second sub-pixel is connected with the active layer of the transistor in the third sub-pixel, and the second plate of the capacitor in the second sub-pixel is disconnected from the second plate of the capacitor in the third sub-pixel.

In the second pixel, the second plate of the capacitor in the second sub-pixel is connected with the second plate of the capacitor in the third sub-pixel, the active layer of the transistor in the second sub-pixel is disconnected from the active layer of the transistor in the third sub-pixel, the active layer of the transistor in the ith sub-pixel is connected with the active layer of the transistor in the (i + 1) th sub-pixel, and the second plate of the capacitor in the ith sub-pixel is disconnected from the second plate of the capacitor in the (i + 1) th sub-pixel.

Wherein i is an odd number less than 4.

It should be noted that fig. 2 illustrates 2 pixels arranged along a column direction as an example, where an upper pixel is a first pixel, and a lower pixel is a second pixel, which is not limited in this application, and the pixel structures of adjacent sub-pixels are symmetrical in this application, so in the display substrate provided in this application, the first pixel is arranged between the adjacent second pixels, and the second pixel is arranged between the adjacent first pixels.

Fig. 5 is a partial top view of a subpixel in a display substrate provided in an embodiment of the present application, fig. 6 is another partial top view of the subpixel in the display substrate provided in the embodiment of the present application, fig. 7 is another partial top view of the subpixel in the display substrate provided in the embodiment of the present application, and it should be noted that the display substrate provided in fig. 5 does not include a power line, a data line, and a source/drain electrode of a transistor, the display substrate provided in fig. 6 only includes a film layer where a second electrode of a capacitor is located and a film layer where the data line is located, and the display substrate provided in fig. 7 only includes a film layer where an active layer of a transistor and a data line are located, as shown in fig. 5, in the display substrate provided in the embodiment of the present application, a first via hole V1 is provided in a third insulating layer.

Specifically, in each sub-pixel, in combination with fig. 5 and 6, an orthographic projection of the second plate C2 of the capacitor on the substrate covers an orthographic projection of the first via V1 on the substrate, and the power line is connected with the second plate C2 of the capacitor through the first via V1.

Optionally, the number of the first vias V1 is at least one. Specifically, the greater the number of first vias V1, the better the conductivity between the power line and the second plate of the capacitor.

Optionally, as shown in fig. 5, in the display substrate provided in the embodiment of the present application, the first insulating layer, the second insulating layer, and the third insulating layer are provided with a second via hole V2 therein.

Specifically, in each sub-pixel, in conjunction with fig. 5 and 7, there is an overlapping region between the orthographic projection of the second via V2 on the substrate and the orthographic projection of the active layer 20 on the substrate, and the power supply line is connected to the active layer 20 of the transistor through the second via V2.

Optionally, the number of the second vias V2 is at least one, and the larger the number of vias, the better the conductivity of the components connected by the vias.

Fig. 5 to 7 illustrate two first vias V1 and one second via V2, which are not limited in this embodiment of the present invention.

The embodiment of the present application further provides a manufacturing method of a display substrate, including: providing a substrate; an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer are sequentially formed on a substrate.

Based on the same inventive concept, an embodiment of the present application further provides a manufacturing method of a display substrate, which is used for manufacturing the display substrate provided in the foregoing embodiment, and fig. 8 is a flowchart of the manufacturing method of the display substrate provided in the embodiment of the present application, and as shown in fig. 8, the manufacturing method of the display substrate provided in the embodiment of the present application specifically includes the following steps:

step 100, a substrate is provided.

Step 200, forming a plurality of sub-pixels, a plurality of rows of power lines and data lines arranged on the same layer as the power lines on the substrate.

Each sub-pixel includes: a drive circuit; the drive circuit includes: a transistor and a capacitor; the capacitor includes: the first polar plate and the second polar plate are oppositely arranged; the capacitor includes: the first polar plate and the second polar plate are oppositely arranged; the active layer of the transistor is positioned on one side of the second plate of the capacitor close to the substrate, and the power line is positioned on one side of the second plate of the capacitor far away from the substrate;

for each sub-pixel, the power line is respectively connected with the second polar plate of the capacitor and the active layer of the transistor, the second polar plate of the capacitor of each sub-pixel is connected with the second polar plate of the capacitor of one adjacent sub-pixel in the same row, and the active layer of the transistor of each sub-pixel is connected with the active layer of the transistor of the other adjacent sub-pixel in the same row.

The manufacturing method of the display substrate provided by the embodiment of the application is used for manufacturing the display substrate provided by the embodiment, and the implementation principle and the implementation effect are similar, and are not repeated here.

Take the case of forming two pixels arranged along the extending direction of the data line, wherein each pixel comprises four sub-pixels, for convenience of description, the film layer where the first electrode plate of the capacitor is located is referred to as a first metal layer, the film layer where the second electrode plate of the capacitor is located is referred to as a second metal layer, the film layer where the power line is located is referred to as a third metal layer, fig. 9 is a schematic view illustrating an active layer of a display substrate according to an embodiment of the present disclosure, fig. 10 is a schematic view illustrating a first insulating layer and a first metal layer of a display substrate according to an embodiment of the present disclosure, FIG. 11 is a schematic diagram illustrating a second insulating layer and a second metal layer of a display substrate according to an embodiment of the present disclosure, fig. 12 is a schematic view illustrating a manufacturing method of a third insulating layer according to an embodiment of the present disclosure, and the following further describes a manufacturing method of a display substrate according to an embodiment of the present disclosure with reference to fig. 9 to 12, and specifically describes the following:

step 101, providing a substrate 10, and forming an active layer 20 on the substrate, as shown in fig. 9.

Step 102 is to form a first insulating layer on the active layer 20, and form a first metal layer 30 on the first insulating layer, as shown in fig. 10.

Wherein the first metal layer includes: a gate line G, a Reset signal line Reset, a light emission control signal line EM, and a first plate C1 of a capacitor.

Step 103, forming a second insulating layer on the first metal layer, and forming a second metal layer on the second insulating layer, as shown in fig. 11.

Wherein the second metal layer includes: an initial signal line Vinit and a second plate C2 of the capacitor.

Step 104, forming a third insulating layer on the second metal layer, as shown in fig. 12.

Specifically, the third insulating layer is provided with a first via hole exposing the second plate of the capacitor, and the first insulating layer, the second insulating layer and the third insulating layer further comprise a second via hole exposing the active layer.

Step 105, a third metal layer is formed on the third insulating layer, as shown in fig. 2.

The third metal layer comprises a data line D, a power line VDD and a source drain electrode of the transistor.

Based on the same inventive concept, the embodiment of the present application further provides a display device, wherein the display device includes: a display substrate.

In an exemplary embodiment, the display device may further include: a timing controller, a data driver, a scan driver and a light emitting driver; the display substrate includes: data lines, gate lines and light emission control signal lines.

In one exemplary embodiment, the timing controller is electrically connected to the data driver, the scan driver, and the light emitting driver, respectively. The data driver is connected with the data lines, the scanning driver is connected with the grid lines, and the light-emitting driver is connected with the light-emitting control signal lines.

Optionally, the display substrate is an OLED display substrate.

Specifically, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator, etc., but the embodiment of the present invention is not limited thereto.

The display substrate is provided in the foregoing embodiments, and the implementation principle and the implementation effect thereof are similar, and are not described herein again.

In the drawings used to describe embodiments of the invention, the thickness and dimensions of layers or microstructures are exaggerated for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A display substrate, characterized in that it comprises: sub-pixels arranged in an array, a plurality of data lines and a plurality of power supply lines; at least one sub-pixel comprises: a driving circuit; the driving circuit comprises: a transistor and a capacitor; The capacitor includes: a first electrode plate and a second electrode plate that are arranged oppositely, and the display substrate includes: a base and an active layer, a first insulating layer, a first metal layer, a second layer stacked on the base in sequence an insulating layer, a second metal layer, a third insulating layer and a third metal layer;

The active layer includes: an active layer of a transistor in at least one driver circuit;

The first metal layer includes: the first plate of the capacitor;

The second metal layer includes: the second pole plate of the capacitor; the second pole plate of the capacitor in the drive circuit is connected with the second pole plate of the capacitor in the first adjacent drive circuit in the same row;

The third insulating layer includes: a first via hole and a second via hole;

The third metal layer includes: a power supply line; the power supply line includes at least three power supply parts: a first power supply part, a second power supply part, and a third power supply part; the second power supply part is connected to the first power supply part and the third power supply part; the data line is arranged parallel to the extending direction of the first power supply part and the second power supply part;

The third metal layer is electrically connected to the second metal layer through the first via hole, and the third metal layer is electrically connected to the active layer of the transistor through the second via hole.

2 . The display substrate according to claim 1 , wherein the driving circuit comprises: a first transistor to a seventh transistor, wherein the first electrode of the fifth transistor is connected to a power supply line, and at least one of the driving circuits The active layer of the transistor includes: the active layers of the first transistor to the seventh transistor, the active layer protrusion and the power supply connection part; the active layer of at least one transistor includes: a channel part and a channel part respectively located on both sides of the channel part. the first conductor part and the second conductor part, the first pole of the transistor is connected with the first conductor part, and the second pole of the transistor is connected with the second conductor part;

For at least one driving circuit, the first conductor portion of the fifth transistor is respectively connected with the active layer bump and the power supply connection portion, wherein the first conductor portion, the active layer bump and the power supply connection portion of the fifth transistor are set to write Input power signal, wherein, the power signal is the signal of the power line.

3 . The display substrate according to claim 2 , wherein, for at least one driving circuit, the active layer protrusion and the power supply connecting portion are respectively located on both sides of the first conductor portion of the fifth transistor. 4 .

4 . The display substrate according to claim 3 , wherein the active layer protrusion is located on a side of the first conductor portion of the fifth transistor away from the active layer of the sixth transistor, and the power connection portion is located on the side of the active layer of the sixth transistor. 5 . The first conductor portion of the fifth transistor is close to one side of the active layer of the sixth transistor.

5 . The display substrate according to claim 4 , wherein the active layer bumps in at least one driving circuit are connected to the active layer bumps in the second adjacent driving circuit in the same row. 6 .

6 . The display substrate according to claim 2 , wherein the power line is electrically connected to the power connection portion through the second via hole. 7 .

7 . The display substrate according to claim 2 , wherein the second metal layer further comprises: a connection electrode; the second power supply part is connected to the connection electrode through a first via hole, and the third power supply part is connected to the connection electrode through a first via hole. The power supply part is connected to the second electrode plate of the capacitor through the first via hole.

8. The display substrate according to claim 7, wherein the first metal layer further comprises: a plurality of gate lines, a plurality of reset signal lines and a plurality of light-emitting control signal lines;

The orthographic projection of the first power supply part on the substrate coincides with the orthographic projection of the initial signal line and the reset signal line on the forehead of the substrate;

There is no overlapping area between the orthographic projection of the second power supply portion on the substrate and the orthographic projection of the second electrode plate of the capacitor and the grid line on the substrate, and the orthographic projection of the second power supply portion on the substrate at least partially overlapping the orthographic projection of the connection electrode and the active layer of the first transistor on the substrate;

The orthographic projection of the third power supply portion on the substrate at least partially overlaps the orthographic projection of the gate line, the second substrate of the capacitor, and the light-emitting control signal on the substrate.

9 . The display substrate according to claim 2 , wherein the first insulating layer, the second insulating layer and the third insulating layer are provided with a first insulating layer exposing the active layer of the sixth transistor. 10 . a sixth via hole of the conductor part;

For at least one driving circuit, the dummy line of the first power supply part passes through the sixth via hole.

10 . The display substrate of claim 2 , wherein the second metal layer further comprises: an initial signal line, the first insulating layer, the second insulating layer and the third insulating layer further include: 11 . a third via hole exposing the second conductor portion of the active layer of the seventh transistor is opened, and an eighth via hole exposing the initial signal line is also opened in the third insulating layer;

For at least one driving circuit, the dummy line of the third power supply part passes through part of the third via hole and the eighth via hole.

11 . The display substrate of claim 1 , wherein an angle between the first power supply portion and the second power supply portion is greater than or equal to 90 degrees and less than 180 degrees; 11 .

The included angle between the second power supply part and the third power supply part is greater than or equal to 90 degrees and less than 180 degrees.

12 . The display substrate of claim 1 , wherein the width of the first power supply portion is greater than or equal to the width of the third power supply portion; 12 .

The width of the first power supply portion is greater than or equal to the width of the second power supply portion.

13 . The display substrate of claim 1 , wherein the data lines are located in the third metal layer. 14 .

14 . The display substrate according to claim 8 , wherein the data line comprises: a first sub-data line and a second sub-data line; the first sub-data line and the second sub-data line are respectively on both sides of the power cord;

For the i-th row driving circuit, the distance between the first power supply part and the first sub-data line is greater than the distance between the first power supply part and the second sub-data line, and the third power supply The distance between the part and the first sub-data line is smaller than the distance between the third power supply part and the second sub-data line;

For the i+1 th row driving circuit, the distance between the first power supply part and the first sub-data line is smaller than the distance between the first power supply part and the second sub-data line, and the The distance between the three power supply parts and the first sub-data line is greater than the distance between the third power supply part and the second sub-data line.

15 . The display substrate of claim 1 , wherein the pixel structures of adjacent sub-pixels are symmetrically arranged along a center line of the pixel structures of the adjacent sub-pixels. 16 .

16 . The display substrate according to claim 1 , wherein adjacent power lines are symmetrically arranged along a center line between adjacent power lines. 17 .

17. The display substrate according to claim 2, wherein, for at least one driving circuit, the second electrode plate of the capacitor comprises: an integrally formed main body portion and a protruding portion;

The protruding portion is located on one side of the main body portion, and the orthographic projection of the protruding portion on the substrate at least partially overlaps the orthographic projection of the active layer of the sixth transistor on the substrate;

The orthographic projection of the main body portion on the substrate partially overlaps the orthographic projection of the first electrode plate on the substrate, and the main body portion is provided with a via hole exposing the first electrode plate of the capacitor.

18. The display substrate according to claim 17, wherein the connection electrode comprises: a first connection part and a second connection part which are integrally formed;

The extension direction of the first connection portion is the same as the extension direction of the data line, and the extension direction of the second connection portion is the same as the extension direction of the gate line;

The orthographic projection of the first connection part on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor on the substrate, and the second connection part and the active layer of the first transistor on the substrate orthographic projections at least partially overlap;

The dummy line of the first connecting portion passes through the protruding portion of the second electrode plate of the capacitor.

19 . The display substrate according to claim 8 , wherein the first metal layer further comprises: a gate electrode of a second transistor, the gate electrode of the second transistor and the gate line are integrally formed, and the The gate electrode of the second transistor includes: a first branch segment and a second branch segment connected to each other;

The extension direction of the first branch segment is the same as the extension direction of the data line, and the extension direction of the second branch segment is the same as the extension direction of the gate line;

The dummy line of the first branch segment passes through the second connection portion of the connection electrode.

20. The display substrate according to claim 14, wherein at least one driving circuit located in the i-th row is connected to the first sub-data line;

At least one driving circuit in row i+1 is connected to the second sub-data line; 1≤i≤M, and i is an odd number.

21. The display substrate according to claim 14, wherein the t-th power line and the t+1-th power line comprise: the first sub-data line of the t-th data line and the t+1-th power line The first sub-data line of the data line, or the second sub-data line of the t-th data line and the second sub-data line of the t+1-th data line.

22 . The display substrate according to claim 14 , wherein the first sub-data line of the jth data line is located on the side of the jth power supply line close to the driving circuit of the j-1th column, and the jth data line The second sub data line is located on the side of the jth power line close to the j+1th column driving circuit;

The first sub-data line of the j+1th data line is located on the side of the j+1th power supply line close to the driving circuit of the j+2th column, and the second sub-data line of the j+1th data line is located on the j+th column One power line is close to one side of the j-th column driving circuit, 1≤j≤N, and j is an odd number.

23 . The display substrate according to claim 14 , wherein the orthographic projection of the first sub-data line and the second sub-data line on the substrate is the same as the initial signal line, the reset signal line, Orthographic projections of the gate lines and the light-emitting control signal lines on the substrate at least partially overlap.

24 . The display substrate of claim 14 , wherein the width of the first power supply portion is greater than the width of the first sub-data line and greater than the width of the second sub-data line. 25 .

25. The display substrate according to claim 8, wherein, for at least one driving circuit, the active layers of all transistors are integrally formed into a structure;

The active layer of the sixth transistor of the drive circuit at row s and column t is connected to the active layer of the seventh transistor of the drive circuit at row s+1 at column t; 1≤s≤M, 1≤t ≤N, M is the number of rows of the drive circuit, N is the number of columns of the drive circuit;

The active layer bump of the driver circuit located at row i, column j+1 is connected to the active layer bump of the drive circuit at row i, column j+2; the drive at row i+1, column j The active layer bumps of the circuit are connected to the active layer bumps located at the i+1th row and the j+1th column; 1≤i≤M, 1≤j≤N, and i, j are odd numbers.

26. The display substrate according to claim 25, wherein the first plate of the capacitor comprises: a first side and a second side arranged oppositely; for at least one driving circuit, the gate line and the reset signal line are located at On the first side of the first pole plate of the capacitor, the reset signal line is located on the side of the grid line away from the first pole plate of the capacitor, and the light-emitting control signal line is located on the second side of the first pole plate of the capacitor;

The first metal layer further includes: the gate electrode of the first transistor to the gate electrode of the seventh transistor, the gate electrode of the first transistor is arranged across the active layer of the first transistor, and the gate electrode of the second transistor is arranged across the active layer. On the active layer of the second transistor, the gate electrode of the third transistor is arranged across the active layer of the third transistor, the gate electrode of the fourth transistor is arranged across the active layer of the fourth transistor, and the gate electrode of the fifth transistor is arranged across the active layer of the fourth transistor. The electrode is arranged across the active layer of the fifth transistor, the gate electrode of the sixth transistor is arranged across the active layer of the sixth transistor, and the gate electrode of the seventh transistor is arranged across the active layer of the seventh transistor;

The gate electrode of the first transistor, the gate electrode of the seventh transistor and the reset signal line are integrally formed, the gate electrode of the second transistor, the gate electrode and the gate line of the fourth transistor are integrally formed, and the gate electrode of the third transistor and the gate line are integrally formed. The first electrode plate of the capacitor is an integrally formed structure, and the gate electrode of the fifth transistor, the gate electrode of the sixth transistor and the light-emitting control signal line are integrally formed.

27 . The display substrate according to claim 26 , wherein, for at least one driving circuit, the first insulating layer, the second insulating layer and the third insulating layer are further provided with fourth vias and the fifth via hole, the second insulating layer and the third insulating layer are provided with a seventh via hole;

The fourth via hole exposes the active layer of the fourth transistor, the fifth via hole exposes the active layer of the second transistor, the sixth via hole exposes the active layer of the sixth transistor, and the seventh via hole exposes the active layer of the sixth transistor. The via hole exposes the first plate of the capacitor.

28. The display substrate according to claim 27, wherein the third metal layer further comprises: a first electrode and a second electrode of the first transistor, a first electrode and a second electrode of the second transistor, a second electrode The first pole of the four transistors, the second pole of the fifth transistor, the second pole of the sixth transistor, the first pole and the second pole of the seventh transistor;

For at least one driving circuit, the second electrode of the first transistor and the second electrode of the seventh transistor are integrally formed, and the orthographic projection of the second electrode of the first transistor on the substrate is the same as the active layer of the seventh transistor and the initial signal line. at least partially overlap with the orthographic projection of the reset signal line on the substrate;

The first electrode of the first transistor and the second electrode of the second transistor are integrally formed, and the orthographic projection of the first electrode of the first transistor on the substrate and the orthographic projection of the active layer and the gate line of the second transistor on the substrate are at least partially overlapping;

The second pole of the sixth transistor and the second pole of the seventh transistor are integrally formed, and the orthographic projection of the second pole of the sixth transistor on the substrate at least partially overlaps the orthographic projection of the light-emitting control signal line on the substrate;

The first electrode of the fourth transistor of the driving circuit in the i-th row and the first sub-data line are integrally formed, and the first electrode of the fourth transistor of the driving circuit in the i+1-th row and the second sub-data line are In the one-piece molding structure, the orthographic projection of the first electrode of the fourth transistor on the substrate at least partially overlaps with the orthographic projection of the active layer of the fourth transistor on the substrate.

29 . The display substrate of claim 28 , wherein the orthographic projection of the dummy line of the first electrode of the fourth transistor on the substrate protrudes through the active layer. 30 .

30 . The display substrate according to claim 28 , wherein an orthographic projection of the second electrode of the second transistor on the substrate and an orthographic projection of the seventh via hole on the substrate have an overlapping area; 30 .

The dummy line of the second pole of the second transistor passes through the second power supply part.

31. A display device, comprising: a display substrate as claimed in any one of claims 1 to 30, a timing controller, a data driver, a scan driver and a light-emitting driver; the display substrate comprises: data lines, grid lines and light-emitting control signal lines;

the timing controller is respectively electrically connected with the data driver, the scan driver and the light-emitting driver;

The data driver is connected with the data line, the scan driver is connected with the gate line, and the light-emitting driver is connected with the light-emitting control signal line.

32. A method for manufacturing a display substrate, wherein the method is configured to manufacture the display substrate according to any one of claims 1 to 30;

provide a base;

Active layers, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer, are sequentially formed on the substrate.