CN114003286B - Instruction execution method based on dummy, computing device and storage medium - Google Patents
Instruction execution method based on dummy, computing device and storage medium Download PDFInfo
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- CN114003286B CN114003286B CN202111289517.3A CN202111289517A CN114003286B CN 114003286 B CN114003286 B CN 114003286B CN 202111289517 A CN202111289517 A CN 202111289517A CN 114003286 B CN114003286 B CN 114003286B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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Abstract
本发明公开了一种基于哑元的指令执行方法、计算设备及存储介质。方法包括步骤：将应用在内部存储器中的存储数据的第一存储指令提交到所述处理器；根据处理器产生的数据存储异常消息生成第二存储指令；根据第二存储指令所存储数据的存储地址写入哑元；通过处理器执行第二存储指令在内部存储器中存储数据，对所存储的哑元进行替换；当写入哑元后接收到在内部存储器中读取数据的第一读取指令时，通过处理器执行第一读取指令，判断是否读取到哑元；若读取到哑元，提示所读取数据无效，则再次通过处理器执行所述第一读取指令；若未读取到哑元，则通过第一读取指令读取数据。本发明能够使数据访存的原子性不丢失，避免某些特殊应用程序运行异常问题。
The present invention discloses an instruction execution method based on dummy variables, a computing device and a storage medium. The method comprises the steps of: submitting a first storage instruction for storing data in an internal memory to the processor; generating a second storage instruction according to a data storage exception message generated by the processor; writing a dummy variable according to the storage address of the data stored in the second storage instruction; executing the second storage instruction by the processor to store data in the internal memory and replace the stored dummy variable; when receiving a first read instruction for reading data in the internal memory after writing the dummy variable, executing the first read instruction by the processor to determine whether the dummy variable is read; if the dummy variable is read, prompting that the read data is invalid, then executing the first read instruction by the processor again; if the dummy variable is not read, reading the data by the first read instruction. The present invention can prevent the atomicity of data access from being lost and avoid abnormal operation of certain special applications.
Description
Technical Field
The present invention relates to the field of computer instruction execution, and in particular, to a method for executing instructions based on a dummy, a computing device, and a storage medium.
Background
With the continuous development of computer technology, more and more applications are being developed. Accordingly, more and more data are applied, and the data structure is more and more complex. Therefore, the access performance of the system to the complex data structure in the memory is also more and more important, and the operation speed of the key application program is directly influenced. When the data is stored, special storage conditions often occur, and when the processor is applied to access the stored data, the processor does not support special access instructions for the data, the error reporting condition occurs, and the processor cannot directly process the operation data of the access instructions.
For this reason, in the prior art, in order to access these stored data, a change data access instruction is adopted, so that an instruction for accessing these data by an application becomes a normal instruction, and the processor can perform the access of the data. The scheme is that an original cross-boundary access instruction is converted into two cross-boundary access instructions, and complete data can be successfully stored or read by executing the two cross-boundary access instructions.
But this way one memory access is translated to multiple memory accesses, thus essentially changing the memory access model of the application. For some special application scenarios, the atomicity of one memory access is destroyed by multiple memory accesses, and if an application program depends on the atomicity of the memory access, in this case, the data is error or error due to the destruction of the atomicity, and the application program can run abnormally when serious.
For this reason, a new instruction execution method is required.
Disclosure of Invention
To this end, the present invention provides a dummy-based instruction execution method in an effort to solve or at least alleviate the above-presented problems.
According to one aspect of the invention, there is provided a dummy-based instruction execution method adapted to be executed in a computing device comprising a processor, an internal memory and running one or more applications, the memory area of the internal memory being mapped to memory space and the applications reading and writing data in the internal memory with memory addresses in the memory space, the method comprising the steps of submitting a first memory instruction of the stored data in the internal memory to the processor; when the processor can not normally execute the first storage instruction due to the storage address of the data stored by the first storage instruction, a second storage instruction is generated according to the data storage abnormal information generated by the processor, the second storage instruction is suitable for storing the data to be stored by the first storage instruction, the processor can not generate the data storage abnormal information when executing the second storage instruction, the dummy is written according to the storage address of the data stored by the second storage instruction, the dummy is suitable for being read to prompt that the read data is invalid, the processor executes the second storage instruction to store the data in the internal memory to replace the stored dummy, when the first read instruction of the read data in the internal memory is received after the dummy is written, the processor executes the first read instruction to judge whether the dummy is read, if the dummy is read, the first read instruction is read again, and if the dummy is not read, the data is read through the first read instruction.
Optionally, in the method according to the invention, generating the second storage instruction according to the data storage exception message generated by the processor comprises the steps of generating a first half storage instruction and a second half storage instruction according to the storage address of the first storage instruction, wherein the first half storage instruction and the second half storage instruction are respectively suitable for storing data according to the first half address and the second half address, and taking the first half storage instruction and the second half storage instruction as the second storage instruction.
Optionally, in the method according to the invention the writing of the dummy in the memory address of the data stored in the second memory instruction comprises the step of writing the dummy in accordance with the second half address of the data stored in the second half memory instruction.
Optionally, in the method according to the invention, storing the data in the internal memory by the processor executing the second storing instruction comprises the steps of generating a first half piece of data and a second half piece of data from the data, storing the first half piece of data from the first half piece of address by the processor executing the first half storing instruction, storing the second half piece of data from the second half piece of address by the processor executing the second half storing instruction, and replacing the stored dummy.
Optionally, in the method according to the invention, the first read instruction comprises a second half read instruction, the step of executing the first read instruction by the processor, determining whether the dummy is read comprises the step of executing the second half read instruction by the processor, reading the stored data from the second half address to determine whether the dummy is stored.
Optionally, in the method according to the invention, executing the first read instruction again by the processor comprises the step of executing the second half read instruction by the processor, reading the stored data from the second half address to determine if a dummy is stored.
Optionally, in the method according to the invention, the first read instruction comprises a first half read instruction, and reading the data by the first read instruction comprises the steps of executing the first half read instruction by the processor, reading the stored first half data according to the first half address, and combining the first half data read from the first half address with the second half data read from the second half address to obtain the data.
Optionally, the method according to the invention further comprises the steps of submitting the second read instruction to the processor if the second read instruction is received, generating the first read instruction according to the data access exception message generated by the processor when the processor cannot normally execute the second read instruction due to the address of the data read by the second read instruction, wherein the first read instruction is suitable for reading the data to be read by the second read instruction, and the processor cannot generate the data access exception message when executing the first read instruction.
Optionally, in the method according to the invention, generating the first read instruction according to the data access exception message generated by the processor comprises the steps of generating a first half read instruction and a second half read instruction according to the memory address of the second read instruction, the first half read instruction and the second half read instruction being respectively suitable for reading data according to the first half address and the second half address, and taking the first half read instruction and the second half read instruction as the first read instruction.
Optionally, in the method according to the present invention, the first store instruction comprises an uncorrupted store instruction, and the first half store instruction and the second half store instruction comprise an uncorrupted store instruction.
Optionally, in the method according to the invention, the second read instruction comprises an uncoupling read instruction, and the first half read instruction and the second half read instruction comprise an uncoupling read instruction.
According to another aspect of the invention, a computing device is provided that includes one or more processors, memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing a dummy-based instruction execution method according to the invention.
According to yet another aspect of the invention, there is provided a computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform a method of a dummy-based instruction execution method according to the invention.
The method for executing the instruction based on the dummy is suitable for being executed in the computing equipment, the computing equipment comprises a processor and an internal memory, and one or more applications are operated, and the method comprises the steps of submitting a first storage instruction of storage data in the internal memory to the processor, generating a second storage instruction according to a data storage abnormal message generated by the processor when the processor cannot normally execute the first storage instruction due to the storage address of the data stored by the first storage instruction, wherein the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor cannot generate the data storage abnormal message when executing the second storage instruction. In order to avoid that the thread with other cores of the processor executes a data reading instruction while storing data, and incomplete data is read from a position where data storage is not completed, so that the application operation is made to be wrong, firstly, a dummy is required to be written according to a storage address of the data stored by the second storage instruction, and is suitable for prompting that the read data is invalid when the dummy is read, then the processor executes the second storage instruction to store the data in an internal memory, the stored dummy is replaced, and the data storage is completed by carrying out a replacement mark on the dummy. When a first reading instruction for reading data in the internal memory is received after the dummy is written, the processor executes the first reading instruction to judge whether the dummy is read, and if the dummy is read, the read data is prompted to be invalid, so that the data can not be read normally without completing the storage of the data. And the first reading instruction needs to be executed again through the processor, and if the dummy is not read, the data is read through the first reading instruction, so that the data storage is completed at the moment, and the data can be read normally. The invention can restrict the edge effect caused by the changed memory access model of the application program, so that the atomicity of the data access is not lost, thereby avoiding the abnormal operation problem of certain special application programs caused by the edge effect, and further improving the stability of the application program and the compatibility of the whole system.
Drawings
To the accomplishment of the foregoing and related ends, certain illustrative aspects are described herein in connection with the following description and the annexed drawings, which set forth the various ways in which the principles disclosed herein may be practiced, and all aspects and equivalents thereof are intended to fall within the scope of the claimed subject matter. The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. Like reference numerals generally refer to like parts or elements throughout the present disclosure.
FIG. 1 illustrates a schematic diagram of a configuration of a deployment processor and internal memory in a computing device, according to an exemplary embodiment of the invention;
FIG. 2 illustrates a block diagram of a computing device 200 according to an exemplary embodiment of the invention;
FIG. 3 illustrates a flow diagram of a dummy-based instruction execution method 300 according to an exemplary embodiment of the invention;
FIG. 4 illustrates a schematic diagram of generating a second store instruction in accordance with an exemplary embodiment of the invention, an
FIG. 5 illustrates a schematic diagram of destroying instruction atomicity in accordance with an exemplary embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals generally refer to like parts or elements.
FIG. 1 illustrates a schematic diagram of a configuration of a deployment processor and internal memory in a computing device, according to an exemplary embodiment of the invention. As shown in fig. 1, a processor 204 and an internal memory 140 are included in the computing device 200. The computing device 200 also has an operating system 220 installed therein, with the application 110 running on the operating system 220. The invention is not limited to the specific type of operating system 220. The number of applications shown in fig. 1 is merely exemplary. The number and type of applications running on operating system 220 are not limited. The internal memory 140 is adapted to store operating system 220 and operating data for the applications 110, and the processor 204 is adapted to process the operating data.
The specific structure of the computing device 200 in fig. 1 is described in detail by fig. 2. FIG. 2 illustrates a block diagram of a computing device 200 according to an exemplary embodiment of the invention. As shown in FIG. 2, in a basic configuration 202, computing device 200 typically includes a system memory 206 and one or more processors 204. A memory bus 208 may be used for communication between the processor 204 and the system memory 206.
Depending on the desired configuration, processor 204 may be any type of processing including, but not limited to, a microprocessor (μP), a microcontroller (μC), a digital information processor (DSP), or any combination thereof. Processor 204 may include one or more levels of cache, such as a first level cache 210 and a second level cache 212, a processor core 214, and registers 216. The example processor core 214 may include an Arithmetic Logic Unit (ALU), a Floating Point Unit (FPU), a digital signal processing core (DSP core), or any combination thereof. The example memory controller 218 may be used with the processor 204, or in some implementations, the memory controller 218 may be an internal part of the processor 204.
Depending on the desired configuration, system memory 206 may be any type of memory including, but not limited to, volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. The system memory 206 may include an operating system 220, one or more programs 222, and program data 228. In some implementations, the program 222 may be arranged to execute instructions 223 of the method 300 according to the present invention on an operating system by the one or more processors 204 using the program data 228.
Computing device 200 may also include a storage interface bus 234. Storage interface bus 234 enables communication from storage devices 232 (e.g., removable storage 236 and non-removable storage 238) to base configuration 202 via bus/interface controller 230. At least a portion of operating system 220, programs 222, and data 224 may be stored on removable storage 236 and/or non-removable storage 238, and when the program 222 is powered up or is to be executed by the computing device 200, loaded into the system memory 206 via storage interface bus 234 and executed by the one or more processors 204.
Computing device 200 may also include an interface bus 240 that facilitates communication from various interface devices (e.g., output devices 242, peripheral interfaces 244, and communication devices 246) to basic configuration 202 via bus/interface controller 230. The example output device 242 includes a graphics processing unit 248 and an audio processing unit 250. They may be configured to facilitate communication with various external devices, such as a display or speakers, via one or more a/V ports 252. Example peripheral interfaces 244 may include a serial interface controller 254 and a parallel interface controller 256, which may be configured to facilitate communications with external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device) or other peripherals (e.g., printer, scanner, etc.) via one or more I/O ports 258. The example communication device 246 may include a network controller 260 that may be arranged to communicate with one or more other computing devices 262 over a network communication link via one or more communication ports 264.
The network communication link may be one example of a communication medium. Communication media may typically be embodied by computer readable instructions, data structures, program modules, and may include any information delivery media in a modulated data signal, such as a carrier wave or other transport mechanism. A "modulated data signal" may be a signal that has one or more of its data set or changed in such a manner as to encode information in the signal. By way of non-limiting example, communication media may include wired media such as a wired network or special purpose network, and wireless media such as acoustic, radio Frequency (RF), microwave, infrared (IR) or other wireless media. The term computer readable media as used herein may include both storage media and communication media.
In the computing device 200 according to the invention, the program 222 includes a plurality of program instructions of the dummy-based instruction execution method 300 that can instruct the processor 204 to perform some of the steps of running the dummy-based instruction execution method 300 in the computing device 200 of the invention so that portions of the computing device 200 execute instructions by executing the dummy-based instruction execution method 300.
Computing device 200 may be implemented as a server, such as file server 240, database 250, a server, an application server, etc., such as a Personal Digital Assistant (PDA), a wireless web-browsing device, an application-specific device, or a hybrid device that may include any of the above functions. May be implemented as a personal computer including desktop and notebook computer configurations, and in some embodiments, computing device 200 is configured to execute a dummy-based instruction execution method 300.
Fig. 3 shows a flow diagram of a dummy-based instruction execution method 300 according to an exemplary embodiment of the invention. The dummy-based instruction execution method 300 of the present invention is suitable for execution in a computing device and is further suitable for execution by an operating system 220 as shown in FIG. 1. As shown in fig. 3, the dummy-based instruction execution method 300 begins at step S310 with the application 110 submitting a first store instruction of the stored data in the internal memory 140 to the processor 204. When the application 110 needs to store data in the internal memory 140, a first store instruction to store the data needs to be committed to the processor 204 via the operating system 220 for execution. The storage area of the internal memory 140 is mapped to a storage space, and the application 110 stores data in the internal memory 140 with a storage address in the storage space.
Subsequently, step S320 is performed, when the processor 204 cannot normally execute the first storage instruction due to the storage address of the data stored in the first storage instruction, generating a second storage instruction according to the data storage exception message generated by the processor 204, the second storage instruction being adapted to store the data to be stored in the first storage instruction, and the processor 204 not generating the data storage exception message when executing the second storage instruction
When the memory address is not bounded in the internal memory 140, the processor 204 cannot execute the special operation instruction, and a data storage exception message is generated, according to one embodiment of the present invention. The first store instruction includes an out-of-bounds store instruction. When the data to be read by the application 110 is stored in the internal memory 140 without being bound, the first operation instruction is an access instruction of the memory without being bound, and the data storage exception message is an abnormal storage of the memory without being bound. The non-alignment is that the initial position of the data stored in the memory is not aligned with the natural boundary of the data of the type sequentially stored in the memory. For example, a certain 32-bit register, when data is normally stored, the register completely stores 32-bit data, and the first address of the data storage is the first address of the register. However, when the storage is not bounded, the calculator only stores a part of the 32-bit data, the first address of the 32-bit data is offset from the first address of the register, and the first address of the data is at a certain address in the middle of the register. Another portion of the 32-bit data is stored in the next register along with it. Or a 32-bit register, the processor 204 supports reading 16-bit data at a time, and when the first address of the 16-bit data is in the middle of the 32-bit register, that is, a cross-range storage of the 16-bit data is generated, the processor 204 cannot read the data normally. The processor 204 cannot completely fetch the 16-bit data stored separately according to an instruction, and thus the processor 204 throws an exception. The non-bounded memory storage exception refers to directly storing non-bounded data on the processor 204 that does not support direct storage of non-bounded data, which would cause the processor 204 to throw the exception.
FIG. 4 illustrates a schematic diagram of generating a second store instruction according to an exemplary embodiment of the present invention. As shown in fig. 4, when the access instruction is not converted, the instruction decomposition calculation sequence is executed first, a first half storage instruction and a second half storage instruction are generated according to the storage address of the first storage instruction, the first half storage instruction and the second half storage instruction are respectively suitable for storing data according to the first half address and the second half address, and finally the first half storage instruction and the second half storage instruction are used as the second storage instruction. The first half store instruction and the second half store instruction include a store-to-store instruction.
In the instruction conversion process, since the memory access model of the application 110 is changed, one memory operation is broken into a plurality of memory operations, which causes an edge effect, in particular, a change in memory access atomicity. When the correctness of the application 110's operating logic depends on the assumption of atomicity, the application 110 may be abnormally operated due to the lack of atomicity.
FIG. 5 illustrates a schematic diagram of destroying instruction atomicity in accordance with an exemplary embodiment of the present invention. As shown in FIG. 5, since the first half memory instruction and the second half memory instruction are two independent operations, there is no atomicity, there is a FOV gap between them, and other FOVs can be inserted. If a thread with other processing cores in its view performs a memory write operation, the integrity of the data may be compromised, possibly causing an application 110 to run abnormally.
Therefore, it is necessary to perform step S330 to write a dummy according to the storage address of the data stored in the second storage instruction, the dummy being adapted to indicate that the read data is invalid when being read. At the beginning of storing data, the write dummy represents the beginning of data storage when data cannot be read from the memory segment. The dummy is a piece of preset data that, when read by the processor 204, is invalid on behalf of the read data. The dummy is written in the position where the first storage instruction stores data, specifically, the complete data space stored by the first storage instruction is [0, n ], and the data space for storing the dummy is [ i, j ], wherein i is more than or equal to 0 and less than or equal to n, j is more than or equal to 0 and less than or equal to j is more than or equal to j. The dummy is inserted to replace an extra locking mechanism, so that the problem of atomic loss generated after the conversion of the access memory instruction is solved, and the overall performance of data access is improved. And when the dummy is written specifically, writing the dummy according to the second half address of the data stored in the second half storage instruction.
Subsequently, step S340 is performed, wherein the stored dummy is replaced by the processor executing the second storage instruction to store data in the internal memory 140. The dummy replacement is completed, i.e., the storing of data in the internal memory 140 is completed. Specifically, first half data and second half data are generated according to the data, then the first half storage instruction is executed by the processor 204, the first half data is stored according to the first half address, finally the second half storage instruction is executed by the processor 204, and the stored dummy is replaced according to the second half data stored in the second half address.
In the process of storing data, if there is a thread executing an instruction for accessing data, to operate in the memory segment where the data is currently written, step S350 is executed to protect the atomicity of the process of writing data. When a first read instruction to read data in the internal memory 140 is received after writing the dummy, the first read instruction is executed by the processor 204 to determine whether the dummy is read. The first read instruction includes a second half read instruction and a first half read instruction, the first half read instruction and the second half read instruction including a boundary read instruction. Since the dummy is written in the second half address when the dummy is written, the second half read instruction is executed by the processor 204 to read the stored data from the second half address to determine whether the dummy is stored.
If the dummy is not read, the storage section is indicated to finish data storage, and the data can be read normally.
Subsequently, step S360 is performed, and if the dummy is read, the read data is prompted to be invalid, and the first read command is performed again by the processor 204. If the dummy is read, the data storage section is marked as being used for data storage, and if the data is read, the wrong and incomplete data can be read. The first read command is executed again, i.e. it is determined again whether the data storage is completed. When the first read instruction is executed again. The second half read instruction is still executed by the processor 204 to read the stored data from the second half address to determine if a dummy is stored.
If the dummy is still read at this time, the first reading instruction is continuously executed, whether the data storage is completed is continuously judged, until the data storage is completed, the first reading instruction is continuously executed, and until the dummy is not read. In the process of continuously repeating the reading, the data is also written, and when the data is written, the data can be read normally and the cycle is exited, so that the error data can be prevented from being read.
Finally, step S370 is executed, and if the dummy is not read, the data is read by the first read command. When the data storage is completed, step S360 is executed, and the stored second half segment data can be read out according to the second half segment address. When the data is read by the first read instruction, the processor 204 executes the first half read instruction, reads the stored first half data according to the first half address, and combines the first half data read from the first half address with the second half data read from the second half address to obtain the data. When the first half data and the second half data are combined and arranged, the obtained first half data and the second half data are subjected to shift, AND or equal logic bit operation according to the data structures of the first half data and the second half data, and the needed data are intercepted and aligned from the data obtained by the access instruction.
According to one embodiment of the invention, when an instruction in the execution instruction stream is a non-memory-access instruction, the instruction is converted to a memory-access instruction. And traversing all instructions after the instruction stream, and converting the subsequent non-demarcation access storage instruction to obtain a demarcation access storage instruction. The non-demarcated access instructions include non-demarcated read instructions and non-demarcated store instructions, and the demarcated access instructions include demarcated read instructions and demarcated store instructions.
If a second read instruction in the instruction stream is received, the second read instruction includes an untranslated, non-critical read instruction, which is first committed to the processor 204. When the processor 204 cannot normally execute the second read instruction due to the address of the data read by the second read instruction, the first read instruction is generated according to the data access exception message generated by the processor 204, the first read instruction is suitable for reading the data to be read by the second read instruction, and the processor 204 does not generate the data access exception message when executing the first read instruction.
When generating the first read command according to the data access exception message generated by the processor 204, the command decomposition sequence is executed first, and the first half read command and the second half read command are generated according to the storage address of the second read command, and are respectively suitable for reading data according to the first half address and the second half address, and the first half read command and the second half read command are used as the first read command.
The method for executing the instruction based on the dummy is suitable for being executed in the computing equipment, the computing equipment comprises a processor and an internal memory, and one or more applications are operated, and the method comprises the steps of submitting a first storage instruction of storage data in the internal memory to the processor, generating a second storage instruction according to a data storage abnormal message generated by the processor when the processor cannot normally execute the first storage instruction due to the storage address of the data stored by the first storage instruction, wherein the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor cannot generate the data storage abnormal message when executing the second storage instruction. In order to avoid that the thread with other cores of the processor executes a data reading instruction while storing data, and incomplete data is read from a position where data storage is not completed, so that the application operation is made to be wrong, firstly, a dummy is required to be written according to a storage address of the data stored by the second storage instruction, and is suitable for prompting that the read data is invalid when the dummy is read, then the processor executes the second storage instruction to store the data in an internal memory, the stored dummy is replaced, and the data storage is completed by carrying out a replacement mark on the dummy. When a first reading instruction for reading data in the internal memory is received after the dummy is written, the processor executes the first reading instruction to judge whether the dummy is read, and if the dummy is read, the read data is prompted to be invalid, so that the data can not be read normally without completing the storage of the data. And the first reading instruction needs to be executed again through the processor, and if the dummy is not read, the data is read through the first reading instruction, so that the data storage is completed at the moment, and the data can be read normally. The invention can restrict the edge effect caused by the changed memory access model of the application program, so that the atomicity of the data access is not lost, thereby avoiding the abnormal operation problem of certain special application programs caused by the edge effect, and further improving the stability of the application program and the compatibility of the whole system.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim.
Those skilled in the art will appreciate that the modules or units or groups of devices in the examples disclosed herein may be arranged in a device as described in this embodiment, or alternatively may be located in one or more devices different from the devices in this example. The modules in the foregoing examples may be combined into one module or may be further divided into a plurality of sub-modules.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or groups of embodiments may be combined into one module or unit or group, and furthermore they may be divided into a plurality of sub-modules or sub-units or groups. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments.
Furthermore, some of the embodiments are described herein as methods or combinations of method elements that may be implemented by a processor of a computer system or by other means of performing the functions. Thus, a processor with the necessary instructions for implementing the described method or method element forms a means for implementing the method or method element. Furthermore, the elements of the apparatus embodiments described herein are examples of apparatus for performing the functions performed by the elements for the purpose of practicing the invention.
The various techniques described herein may be implemented in connection with hardware or software or, alternatively, with a combination of both. Thus, the methods and apparatus of the present invention, or certain aspects or portions of the methods and apparatus of the present invention, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other machine-readable storage medium, wherein, when the program is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention.
In the case of program code execution on programmable computers, the computing device will generally include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. Wherein the memory is configured to store program code and the processor is configured to execute the dummy-based instruction execution method of the invention in accordance with instructions in said program code stored in the memory.
By way of example, and not limitation, computer readable media comprise computer storage media and communication media. Computer-readable media include computer storage media and communication media. Computer storage media stores information such as computer readable instructions, data structures, program modules, or other data. Communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. Combinations of any of the above are also included within the scope of computer readable media.
As used herein, unless otherwise specified the use of the ordinal terms "first," "second," "third," etc., to describe a general object merely denote different instances of like objects, and are not intended to imply that the objects so described must have a given order, either temporally, spatially, in ranking, or in any other manner.
While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of the above description, will appreciate that other embodiments are contemplated within the scope of the invention as described herein. Furthermore, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is defined by the appended claims.
Claims (7)
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| US9465663B2 (en) * | 2008-10-31 | 2016-10-11 | Synopsys, Inc. | Allocating resources in a compute farm to increase resource utilization by using a priority-based allocation layer to allocate job slots to projects |
| CN101510781B (en) * | 2009-03-24 | 2011-08-10 | 华为技术有限公司 | Method and device for filling dummy argument for interlace and de-interlace process as well as processing system |
| US9996329B2 (en) * | 2016-02-16 | 2018-06-12 | Microsoft Technology Licensing, Llc | Translating atomic read-modify-write accesses |
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