CN114005832B - NAND flash memory device and method for manufacturing NAND flash memory - Google Patents
NAND flash memory device and method for manufacturing NAND flash memory Download PDFInfo
- Publication number
- CN114005832B CN114005832B CN202111266556.1A CN202111266556A CN114005832B CN 114005832 B CN114005832 B CN 114005832B CN 202111266556 A CN202111266556 A CN 202111266556A CN 114005832 B CN114005832 B CN 114005832B
- Authority
- CN
- China
- Prior art keywords
- layer
- floating gate
- control gate
- flash memory
- nand flash
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
-
- H10W20/039—
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a manufacturing method of a NAND flash memory, which comprises the steps of providing a substrate, forming at least two floating gate layers on the substrate, arranging an opening between every two adjacent floating gate layers, forming a first side wall on each floating gate layer, covering the side wall and the top of each floating gate layer, forming a control gate material layer, filling the opening and covering the first side wall by the control gate material layer, carrying out an etching process on the control gate material layer to form a control gate layer, forming floating gate layer residues at the floating gate layers, carrying out an atomic layer deposition oxidation process to form a first oxidation layer, covering the control gate layer and the opening by the first oxidation layer, carrying out a rapid thermal oxidation process to form a second oxidation layer, and removing the floating gate layer residues through the first oxidation layer by process gas of the rapid thermal oxidation process. The problems of short circuit and electric leakage of adjacent floating gates caused by residues of the floating gates in the control gate etching process are solved.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a NAND flash memory device and a method for manufacturing a NAND flash memory.
Background
NAND flash memory is a better storage device than hard disk drives, and is widely used in electronic products as people seek nonvolatile memory products with low power consumption, light weight and good performance.
During the control gate etch of NAND FLASH, the Floating Gate (FG) is surrounded by silicon oxide-silicon nitride-silicon oxide (ONO). The floating gate is made of polysilicon, the etching speed of the silicon oxide-silicon nitride-silicon oxide is different from that of the polysilicon, a fence (fence) of the silicon oxide-silicon nitride-silicon oxide is formed at the side edge of the floating gate, and a residue (residual) of the floating gate is formed at the side lower edge of the silicon oxide-silicon nitride-silicon oxide. The residue of the floating gate can cause shorting and leakage of adjacent floating gates.
Disclosure of Invention
The invention aims to provide a NAND flash memory device and a manufacturing method of the NAND flash memory, which are used for solving the problems of short circuit and electric leakage of adjacent floating gates caused by residues of the floating gates in the control gate etching process.
In order to solve the above technical problems, the present invention provides a method for manufacturing a NAND flash memory, including:
providing a substrate, forming at least two floating gate layers on the substrate, and forming an opening between adjacent floating gate layers, wherein a first side wall is formed on the floating gate layers, and covers the side wall and the top of the floating gate layers;
Forming a control gate material layer, wherein the control gate material layer fills the opening and covers the first side wall;
Etching the control gate material layer to form a control gate layer, and forming floating gate layer residues at the floating gate layer;
Performing an atomic layer deposition oxidation process to form a first oxide layer, wherein the first oxide layer covers the control gate layer and the opening;
A rapid thermal oxidation process is performed to form a second oxide layer, and a process gas of the rapid thermal oxidation process penetrates the first oxide layer to remove the floating gate layer residue.
Optionally, the material of the floating gate layer is polysilicon.
Optionally, the process gas in the rapid thermal oxidation process includes oxygen, and the oxygen reacts with the floating gate layer residue to form the silicon oxide layer.
Optionally, the thickness of the floating gate layer residue removed in the rapid thermal oxidation process is no more than 1 nanometer.
Optionally, the process temperature of the rapid thermal oxidation process is 850-950 ℃.
Optionally, the thickness of the first oxide layer formed by the atomic layer deposition oxidation process is 10 angstroms to 40 angstroms.
Optionally, before the etching process is performed on the control gate material layer, a hard mask layer is further formed on the control gate material layer.
Optionally, before performing an etching process on the control gate material layer, a patterned photoresist is formed on the hard mask layer.
Optionally, a dry etching process is adopted for the etching process of the control gate material layer.
Based on the same inventive concept, the present invention also provides a NAND flash memory device including:
The floating gate structure comprises a substrate, wherein at least two floating gate layers are formed on the substrate, openings are formed between adjacent floating gate layers, a first side wall is formed on the floating gate layers, and the first side wall covers the top of the floating gate layers;
the control gate layer is positioned at the upper part of the first side wall;
the first oxide layer covers the control gate layer;
and the second oxide layer is formed by rapid thermal oxidation of the floating gate layer residues and oxygen, and covers the first oxide layer.
Compared with the prior art, the invention has the following beneficial effects:
In the NAND flash memory device and the manufacturing method of the NAND flash memory, the etching process is carried out on the control gate material layer, when the control gate layer is formed, floating gate layer residues are formed at the floating gate layer, the atomic layer deposition oxidation process is adopted to form the first oxide layer, the first oxide layer covers the control gate layer and the opening, process gas of the rapid thermal oxidation process penetrates through the first oxide layer to remove the floating gate layer residues, the control gate layer is the control gate, and the floating gate layer is the floating gate, so that the problems of short circuit and electric leakage of adjacent floating gates caused by the floating gate residues in the control gate etching process can be solved.
Drawings
FIG. 1 is a flow chart of a method for fabricating a NAND flash memory according to an embodiment of the present invention;
FIGS. 2-5 are schematic cross-sectional views of structures formed in a method of fabricating a NAND flash memory according to an embodiment of the present invention;
In the drawing the view of the figure,
100-Substrate, 101-gate oxide layer, 102-floating gate layer, 103-first sidewall, 104-control gate material layer, 104 a-control gate layer, 105-second hard mask layer, 106-second patterned photoresist, 107-floating gate layer residue, 108-first oxide layer, 109-second oxide layer.
Detailed Description
The following describes a NAND flash memory device and a method for manufacturing a NAND flash memory according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Specifically, referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a NAND flash memory according to an embodiment of the invention. As shown in fig. 1, the embodiment provides a method for manufacturing a NAND flash memory, which includes:
Step S10, a substrate is provided, at least two floating gate layers are formed on the substrate, openings are formed between adjacent floating gate layers, first side walls are formed on the floating gate layers, and the side walls and the top of the floating gate layers are covered by the first side walls.
Step S20, forming a control gate material layer, wherein the control gate material layer fills the opening and covers the first side wall;
step S30, performing an etching process on the control gate material layer to form a control gate layer, and forming floating gate layer residues at the floating gate layer;
Step S40, performing an atomic layer deposition oxidation process to form a first oxide layer, wherein the first oxide layer covers the control gate layer and the opening;
And S50, performing a rapid thermal oxidation process to form a second oxide layer, wherein process gas of the rapid thermal oxidation process penetrates through the first oxide layer to remove the floating gate layer residues.
Fig. 2 to 5 are schematic cross-sectional views of structures formed in the method for fabricating a NAND flash memory according to an embodiment of the present invention, and the method for fabricating a NAND flash memory according to the embodiment will be described in more detail with reference to fig. 2 to 5.
First, step S10 is performed, as shown in fig. 2, a substrate 100 is provided, where the substrate 100 may be monocrystalline silicon or polycrystalline silicon, semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, or composite structures such as silicon on insulator. Those skilled in the art may select the type of the semiconductor substrate 100 according to the semiconductor device formed on the semiconductor substrate 100, and thus the type of the semiconductor substrate 100 should not limit the scope of the present invention. At least two floating gate layers 102 are formed on the substrate 100, openings (not shown in the figure) are arranged between adjacent floating gate layers 102, first side walls 103 are formed on the floating gate layers 102, and the first side walls 103 cover the side walls and the top of the floating gate layers 102.
Before forming the floating gate layer 102, the gate oxide layer 101 is formed on the substrate 100, and the gate oxide layer 101 may be formed by a thermal oxidation process. A floating gate layer material layer is formed on the gate oxide layer 101, and a first hard mask layer (not shown in the figure) is deposited on the floating gate layer material layer, wherein the first hard mask layer is silicon nitride, a patterned photoresist layer is formed on the first hard mask layer by means of chemical vapor deposition, the patterned photoresist layer is used as a mask, the first hard mask layer is etched, and a first patterned hard mask layer is formed, and the first patterned hard mask layer and the first patterned photoresist layer form a mask pattern. And etching the floating gate layer material layer by taking the first patterned hard mask layer and the first patterned photoresist layer as masks together, forming an opening in the floating gate layer material layer, and etching the floating gate layer material layer into a floating gate layer 102. After the step of forming the floating gate layer, if the first patterned photoresist is not consumed, a photoresist removing process is also required, and the residual first patterned photoresist is removed usually by an ashing process or a stripping process. The first sidewall 103 is deposited on top of and on the sidewall of the floating gate layer 102, and may be formed by chemical vapor deposition, and in this embodiment, the first sidewall 103 is, for example, an ONO stack, that is, a silicon oxide-silicon nitride-silicon oxide layer. The floating gate layer 102 is a floating gate.
Next, step S20 is performed, as shown in fig. 2, a control gate material layer 104 is formed, and the control gate material layer 104 fills the opening and covers the first sidewall 103. The control gate material layer 104 is, for example, polysilicon, and the control gate material layer 104 may be formed by chemical vapor deposition.
After step S20, before step S30, a second hard mask layer 105 and a second patterned photoresist 106 are further formed on the control gate material layer 104. The second hard mask layer 105 is, for example, silicon nitride, and a second patterned photoresist layer 106 may be formed on the second hard mask layer 105 by chemical vapor deposition.
Next, step S30 is performed, as shown in fig. 3, an etching process is performed on the control gate material layer 104 to form a control gate layer 104a, and a floating gate layer residue 107 is formed at the floating gate layer 102.
In step S30, the second patterned photoresist layer 106 is used as a mask to etch the second hard mask layer 105 to form a second patterned hard mask layer 105a, where the second patterned hard mask layer 105a and the second patterned photoresist layer 106 form a mask pattern. And etching the control gate material layer 104 by using the second patterned hard mask layer 105a and the second patterned photoresist layer 106 as masks together to form a control gate layer 104a. After the step of forming the control gate layer 104a, if the second patterned photoresist 106 is not consumed, a photoresist removal process is further required, and the remaining second patterned photoresist 106 is removed, typically by an ashing process or a stripping process.
The etching process is, for example, a dry etching process. During etching of the control gate material layer 104, the floating gate layer 102 is surrounded by the first sidewall 103. The material of the first sidewall 103 is, for example, ONO, and the material of the floating gate layer 102 is, for example, polysilicon, where the etching speed of ONO is different from that of poly, so that a fence (fense) of ONO is formed on the side of the floating gate layer 102, and a floating gate layer residue (residue) 107 is formed on the lower side of ONO. In this embodiment, the control gate layer 104a is a control gate.
Next, step S40 is performed, as shown in fig. 4, to perform an Atomic Layer Deposition (ALD) oxidation process to form a first oxide layer 108, where the first oxide layer 108 covers the control gate layer 104a, and the thickness of the first oxide layer 108 formed by the ALD oxidation process is, for example, 10 a-40 a.
Next, step S50 is performed, as shown in fig. 5, to perform a Rapid Thermal Oxidation (RTO) process to form a second oxide layer 109, wherein the rapid thermal oxidation process penetrates the first oxide layer 108 to remove the floating gate layer residue 107.
In this embodiment, the process temperature of the rapid thermal oxidation process is, for example, 850 ℃ to 950 ℃. The process gas in the rapid thermal oxidation process includes oxygen, the oxygen reacts with the floating gate layer residue 107 to generate the second oxide layer 109, and the floating gate layer residue 107 is polysilicon, that is, the oxygen in the rapid thermal oxidation process passes through the first oxide layer 108 and reacts with the floating gate layer residue 107 to generate the second oxide layer 109, so as to remove the floating gate layer residue 107, and avoid the short circuit and leakage phenomena of adjacent floating gate layers due to the floating gate layer residue 107. The thickness of the floating gate layer 102 removed in the rapid thermal oxidation process is not more than 1 nm. The first oxide layer 108 may control the amount of oxygen reacted with the floating gate layer residue 107 during the rapid thermal oxidation process, preventing oxygen from continuing to react with the floating gate layer 102. The second oxide layer 109 formed by the rapid thermal oxidation process is denser, improving the performance of the NAND flash memory device. The first oxide layer 108 and the second oxide layer 109 form the sidewalls of the control gate layer 104 a.
With continued reference to fig. 5, based on the same inventive concept, this embodiment also provides a NAND flash memory device, including:
The substrate 100, at least two floating gate layers 102 are formed on the substrate 100, openings are arranged between adjacent floating gate layers 102, a first side wall 103 is formed on the floating gate layers 102, and the first side wall 103 covers the top of the floating gate layers 102;
A control gate layer 104a, wherein the control gate layer 104a is located at the upper part of the first side wall 103;
a first oxide layer 108, the first oxide layer 108 covering the control gate layer 104a;
A second oxide layer 109 formed by rapid thermal oxidation of the floating gate layer residue with oxygen, said second oxide layer 109 covering said first oxide layer 108.
In this embodiment, the floating gate layer 102 is a floating gate, the control gate layer 104a is a control gate, and the first oxide layer 108 and the second oxide layer 109 form a sidewall of the control gate layer 104 a.
In summary, in the NAND flash memory device and the manufacturing method of the NAND flash memory provided by the embodiments of the invention, the etching process is performed on the control gate material layer, when the control gate layer is formed, the floating gate layer residue is formed at the floating gate layer, the atomic layer deposition oxidation process is adopted to form the first oxide layer, the first oxide layer covers the control gate layer, the process gas of the rapid thermal oxidation process penetrates through the first oxide layer to remove the floating gate layer residue, the control gate layer is the control gate, and the floating gate layer is the floating gate, so that the problems of adjacent floating gate short circuit and electric leakage caused by the floating gate residue in the control gate etching process can be solved.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111266556.1A CN114005832B (en) | 2021-10-28 | 2021-10-28 | NAND flash memory device and method for manufacturing NAND flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111266556.1A CN114005832B (en) | 2021-10-28 | 2021-10-28 | NAND flash memory device and method for manufacturing NAND flash memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114005832A CN114005832A (en) | 2022-02-01 |
| CN114005832B true CN114005832B (en) | 2025-07-15 |
Family
ID=79924768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111266556.1A Active CN114005832B (en) | 2021-10-28 | 2021-10-28 | NAND flash memory device and method for manufacturing NAND flash memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114005832B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118401004B (en) * | 2024-06-14 | 2024-08-30 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050069189A (en) * | 2003-12-31 | 2005-07-05 | 동부아남반도체 주식회사 | Method for fabricating flash memory device |
| CN106298674A (en) * | 2015-05-25 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | Memorizer and forming method thereof |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3314807B2 (en) * | 1998-11-26 | 2002-08-19 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| KR100466188B1 (en) * | 2002-05-29 | 2005-01-13 | 주식회사 하이닉스반도체 | Method of manufacturing for floating gate in flash memory cell |
| KR100507703B1 (en) * | 2003-12-29 | 2005-08-09 | 주식회사 하이닉스반도체 | Method of manufacturing in a flash memory devices |
| CN102368479B (en) * | 2011-11-24 | 2015-01-21 | 上海华虹宏力半导体制造有限公司 | Flash memory and manufacturing method thereof |
| CN104779209B (en) * | 2014-01-13 | 2018-07-20 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of flash memory |
| CN105789132B (en) * | 2014-12-16 | 2019-01-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of forming method of side wall |
| CN105990249A (en) * | 2015-02-27 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure formation method |
| CN107359163B (en) * | 2016-05-05 | 2020-06-02 | 中芯国际集成电路制造（天津）有限公司 | Preparation method of storage unit |
| CN106206598B (en) * | 2016-07-27 | 2019-06-28 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory device making method |
| CN112713149B (en) * | 2019-10-25 | 2025-06-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for forming the same |
| CN113035698B (en) * | 2019-12-24 | 2025-02-25 | 中芯国际集成电路制造(上海)有限公司 | A method for forming a NAND flash memory and a NAND flash memory |
| CN111785723B (en) * | 2020-07-24 | 2023-07-11 | 上海华虹宏力半导体制造有限公司 | A method of manufacturing a split-gate memory |
| CN113192960B (en) * | 2021-04-27 | 2023-11-03 | 上海华虹宏力半导体制造有限公司 | How flash memory is formed |
| CN113224068A (en) * | 2021-04-28 | 2021-08-06 | 华虹半导体(无锡)有限公司 | NORD flash memory device structure and manufacturing method thereof |
-
2021
- 2021-10-28 CN CN202111266556.1A patent/CN114005832B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050069189A (en) * | 2003-12-31 | 2005-07-05 | 동부아남반도체 주식회사 | Method for fabricating flash memory device |
| CN106298674A (en) * | 2015-05-25 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | Memorizer and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114005832A (en) | 2022-02-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108933140B (en) | Method for manufacturing semiconductor device | |
| JP4217406B2 (en) | Split gate flash memory device and manufacturing method thereof | |
| TWI624032B (en) | Semiconductor component and method of manufacturing same | |
| CN101847596A (en) | patterning method | |
| CN100407376C (en) | Method of manufacturing floating gate of flash memory device | |
| CN114005832B (en) | NAND flash memory device and method for manufacturing NAND flash memory | |
| CN113497046B (en) | Memory element and method of manufacturing same | |
| CN112242399A (en) | NAND flash memory device and method of manufacturing the same | |
| US20100093142A1 (en) | Method of fabricating device | |
| KR100824633B1 (en) | Flash memory device and manufacturing method thereof | |
| KR100673182B1 (en) | Manufacturing Method of Flash Memory Device | |
| CN115101527A (en) | Method for manufacturing memory device | |
| TWI469269B (en) | Method of forming word line of embedded flash memory | |
| TW201036111A (en) | Method for fabricating nonvolatile memory device | |
| KR100829612B1 (en) | A thin film forming method and a manufacturing method of a charge trapping nonvolatile memory device. | |
| TWI565035B (en) | Memory cell and fabricating method thereof | |
| CN108110008B (en) | Semiconductor element, method for manufacturing the same, and method for manufacturing memory | |
| CN107706153B (en) | Method of forming a semiconductor device | |
| CN118401004B (en) | Method for manufacturing semiconductor device | |
| CN119208144B (en) | Manufacturing method of SONOS memory | |
| CN119967891B (en) | Semiconductor devices and their fabrication methods | |
| CN114765184B (en) | Memory structure and manufacturing method thereof | |
| KR100456579B1 (en) | Mask Read-Only Memory(ROM) Devices And Method Of Fabricating The Same | |
| KR101087723B1 (en) | Manufacturing method of NAND flash memory device | |
| CN120603244A (en) | Method for manufacturing semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20250417 Address after: No.6 liangteng Road, Pudong New Area, Shanghai, 201314 Applicant after: SHANGHAI HUALI INTEGRATED CIRCUIT MANUFACTURING Co.,Ltd. Country or region after: China Address before: No.6 liangteng Road, Pudong New Area, Shanghai 201315 Applicant before: Shanghai Huali Microelectronics Co.,Ltd. Country or region before: China |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |