CN103996714A - N type silicon carbide longitudinal metal oxide semiconductor tube - Google Patents

Abstract

An N-type silicon carbide vertical metal oxide semiconductor tube, comprising: an N-type substrate, a drain metal is connected to one side of the N-type substrate, and an N-type drift region is provided on the other side of the N-type substrate, A P-type base region is provided in the N-type drift region, a P-type body contact region and an N-type source region are provided in the P-type base region, a gate oxide layer is provided on the surface of the N-type drift region, and the boundary of the gate oxide layer Extending to both sides and ending at the boundary of the N-type source region, a polysilicon gate is provided on the surface of the gate oxide layer, a field oxide layer is provided on the polysilicon gate and the N-type source region, and a gate is connected to the surface of the polysilicon gate Metal, the source metal is connected to the N-type source region and the P-type body contact region. It is characterized in that a metal layer is embedded between the P-type body contact region and the P-type base region. The advantage of this structure is that it can not only significantly reduce the reverse recovery time of the device, but also improve the anti-latch-up ability of the device under the premise of keeping other parameters such as the breakdown voltage of the device basically unchanged.

Description

An N-type silicon carbide vertical metal oxide semiconductor tube

technical field

The invention mainly relates to the field of high-voltage power semiconductor devices, specifically, an N-type silicon carbide vertical metal oxide semiconductor tube, which is suitable for high-temperature, high-frequency, and high-power applications in aerospace, aviation, oil exploration, nuclear energy, radar, and communications. , Strong radiation and other extreme environments coexist.

Background technique

Silicon carbide is one of the wide bandgap semiconductor materials developed rapidly in the past ten years. Compared with the widely used semiconductor materials silicon, germanium and gallium arsenide, silicon carbide has the advantages of wide bandgap, high breakdown electric field, high carrier saturation drift rate, high thermal conductivity, high power density, etc. Ideal material for high-power, high-frequency devices. At present, developed countries such as the United States, Europe, and Japan have basically solved the problems of silicon carbide single crystal growth and homoepitaxial thin films, and occupy a dominant position in the field of high-power semiconductor devices. According to reports, in January 2014, China realized the mass production of silicon carbide high-power devices for the first time, forming a breakthrough in the semiconductor field dominated by the United States, Europe and Japan.

Power metal oxide semiconductor tube is an ideal switching device and linear amplifier device. It has the advantages of fast switching speed, high fidelity, good frequency response, high thermal stability, etc., and occupies an extremely important position in power devices. In the traditional silicon-based metal oxide semiconductor tube, its current transmission capability is limited by the contradictory relationship between reducing the on-resistance and increasing the breakdown voltage. In order to obtain a higher breakdown voltage, a high-resistivity drift must be used. area, thus limiting its application in the field of high-voltage circuits. However, due to the large critical breakdown electric field of silicon carbide material, under the same withstand voltage and area, the on-resistance of silicon carbide metal oxide semiconductor transistors is at least two orders of magnitude smaller than that of silicon-based metal oxide semiconductor transistors. , so in the field of high-voltage applications, silicon carbide metal oxide semiconductor tubes have very obvious advantages.

The silicon carbide vertical metal oxide semiconductor tube has a conductive path perpendicular to the chip surface. It has a short channel and a large cross-sectional area. As a unipolar device, the silicon carbide vertical metal oxide semiconductor tube has good performance in high frequency and high power applications. performance. However, in practical applications, the switching speed of silicon carbide vertical metal oxide semiconductor transistors is limited by the parasitic body diode inside the device. The reason is that the PN junction as a bipolar device has problems such as minority carrier lifetime and reverse recovery delay. As a result, the current flowing through the device cannot react quickly with the switch of the metal oxide semiconductor tube. To solve this problem, a common practice is to connect a fast recovery Schottky diode in parallel outside the switch tube, which increases the size and cost of the device. When the device of the invention is applied in a system, fast reverse recovery can be realized even if the Schottky diode is not connected in parallel at the source and drain ends, thereby effectively reducing the hardware cost of the system. the

Contents of the invention

The invention provides an N-type silicon carbide vertical metal oxide semiconductor tube.

The present invention adopts the following technical scheme: an N-type silicon carbide vertical metal oxide semiconductor tube, comprising: an N-type substrate, a drain metal is connected to one side of the N-type substrate, and a drain metal is connected to the other side of the N-type substrate An N-type drift region is provided, a P-type base region is provided in the N-type drift region, a P-type body contact region and an N-type source region are provided in the P-type base region, and a gate oxide is provided on the surface of the N-type drift region. and the boundary of the gate oxide layer extends to both sides and ends at the boundary of the N-type source region. A polysilicon gate is arranged on the surface of the gate oxide layer, and a field oxide layer is arranged on the polysilicon gate and the N-type source region. On the polysilicon Gate metal is connected to the surface of the gate, source metal is connected to the N-type source region and the P-type body contact region, and a metal layer is arranged in the P-type body contact region and the P-type base region, and one end of the metal layer Through the P-type body contact region and connected to the source metal, the other end of the metal layer passes through the P-type base region and enters the N-type drift region.

Compared with prior art, the present invention has following advantage:

(1) In the device of the present invention, a metal layer 12 is embedded between the P-type body contact region 4 and the P-type base region 3, and the upper surface of the metal layer 12 is connected to the source metal 10, and the lower surface passes through the P-type body contact region 4 and the P-type base region 3 and extend into the N-type drift region 2 to form a Schottky contact with the N-type drift region 2 . When the body diode of the device is in the forward conduction state, since there is a Schottky junction at both ends, and its built-in potential is much lower than the forward voltage drop of the body diode of the device, most of the electrons in the drain metal 11 pass through The N-type drift region 2 and the metal layer 12 flow to the source metal 10 to form a forward current, only a small number of carriers are collected by the source through the body diode, and there is no accumulation of minority carriers in this process, so when the body diode suddenly When turning from forward conduction to reverse cutoff, its reverse recovery time is very short, similar to Schottky diodes. Accompanying drawing 3 is the contrast chart of the reverse recovery characteristic curve of the device adopting structure of the present invention and conventional device, as seen from the figure compared with conventional device, reverse recovery time and reverse recovery peak current have all obtained obvious improvement reduce.

(2) The advantage of the present invention is that the embedded metal layer 12 also improves the anti-latch capability of the device, thereby improving the reliability of the device and prolonging the service life of the device. Accompanying drawing 4 is the comparison diagram of the electric field distribution along the cross-sectional direction of the bottom of the P-type base region for the devices of the two structures. The bottom of the base region moves to the bottom of the metal layer 12, so the bottom of the metal layer 12 breaks down earlier than the bottom of the P-type base region, and when avalanche breakdown occurs, most of the minority carrier holes generated by impact ionization pass through the metal layer 12 is drawn away by the source metal, and only a small part is collected by the source metal through the P-type base region, which makes the parasitic triode not easy to open, so the anti-latch-up ability of the device is significantly enhanced.

(3) The advantage of the present invention is that the overall breakdown characteristics of the device adopting the structure of the present invention remain basically unchanged compared with conventional devices. Accompanying drawing 5 is the comparison diagram of the ideal breakdown characteristics of the device adopting the structure of the present invention and the conventional device. Terminal structures such as rings and field plates will also lose a part of the breakdown voltage of the device, and the loss is about 20% of the ideal breakdown voltage. The influence of the overall breakdown voltage is almost negligible, so it can be said that the overall breakdown characteristics of the device adopting the structure of the present invention are basically unchanged compared with the original structure.

(4) The manufacture of the device of the present invention is fully compatible with the existing technology, and the manufacturing process is also very simple. It only needs to add a process of manufacturing the metal layer 12 on the basis of the manufacturing process of the conventional structure. the

Description of drawings

FIG. 1 is a cross-sectional view of a device structure of an N-type silicon carbide vertical metal-oxide-semiconductor tube with a conventional structure.

Fig. 2 is a cross-sectional view of the device structure of the improved N-type silicon carbide vertical metal oxide semiconductor tube of the present invention.

Fig. 3 is a graph comparing the reverse recovery characteristic curves of the device adopting the structure of the present invention and the conventional device. It can be seen that the reverse recovery time and the reverse recovery peak current of the device adopting the structure of the present invention are significantly reduced compared with the conventional device.

Fig. 4 is a comparison diagram of the electric field distribution along the cross-section direction of the bottom of the P-type base region between the device adopting the structure of the present invention and the conventional device. It can be seen that the electric field of the P-type base region of the device adopting the structure of the present invention is significantly lower than that of the conventional device, and the strongest point of the electric field is transferred to the bottom of the embedded metal layer. When an avalanche breakdown occurs, most of the carriers will pass through the embedded metal layer. The metal layer instead of the body diode flows away, making the parasitic transistor difficult to turn on, and the anti-latch-up ability of the device is significantly improved.

Fig. 5 is a graph comparing the ideal breakdown characteristics of the device adopting the structure of the present invention and the conventional device. It can be seen that the breakdown characteristics of the devices adopting the structure of the present invention are not much different from those of conventional devices.

Fig. 6 is a specific implementation process of the device of the present invention.

Detailed ways

The present invention will be described in detail below in conjunction with accompanying drawings 2 and 6. An N-type silicon carbide vertical metal oxide semiconductor tube includes: an N-type substrate 1, and a drain metal 11 is connected to one side of the N-type substrate 1. , the other side of the N-type substrate 1 is provided with an N-type drift region 2, a P-type base region 3 is arranged in the N-type drift region 2, a P-type body contact region 4 and a P-type body contact region are arranged in the P-type base region 3 The N-type source region 5 is provided with a gate oxide layer 6 on the surface of the N-type drift region 2, and the boundaries of the gate oxide layer 6 extend to both sides and end at the boundary of the N-type source region 5. On the surface of the gate oxide layer 6 A polysilicon gate 7 is provided, a field oxide layer 8 is provided on the polysilicon gate 7 and the N-type source region 5, and a gate metal 9 is connected to the surface of the polysilicon gate 7, and the N-type source region 5 and the P-type body contact region 4 The source metal 10 is connected, and it is characterized in that a metal layer 12 is provided in the P-type body contact region 4 and the P-type base region 3, and one end of the metal layer 12 passes through the P-type body contact region 4 and connects to the source The pole metal 10 is connected, and the other end of the metal layer 12 passes through the P-type base region 3 and enters the N-type drift region 2 .

The metal layer 12 protrudes into the N-type drift region 2 to a depth of 0-0.3 μm.

The width of the metal layer 12 is one-third to one-half of the width of the P-type body contact region 4 .

The material of the metal layer 12 is nickel-chromium alloy or tungsten-titanium alloy.

The present invention adopts following method to prepare:

In the first step, a layer of N-type epitaxial layer drift region 2 is grown on the surface of N-type substrate 1, as shown in Figure 6 Step1.

In the second step, a P-type base region 3 is formed in the N-type drift region 2 by boron ion implantation and high-temperature annealing, as shown in Figure 6 Step2.

The third step is to form a P-type body contact region 4 in the P-type base region 3 by aluminum ion implantation and high-temperature annealing, as shown in Figure 6 Step3.

In the fourth step, an N-type source region 5 is formed in the P-type base region 3 by nitrogen ion implantation and high-temperature annealing, as shown in Figure 6 Step4.

The fifth step is to grow the gate oxide layer 6, then deposit polysilicon, and etch the polysilicon gate 7, as shown in Figure 6 Step5.

The sixth step is to deposit a layer of sacrificial oxide layer on the surface of the device, and then etch a groove for depositing a metal layer in the central part of the P-type body contact region 4 in the P-type base region 3, and the groove extends into the Inside drift zone 2, as shown in Figure 6 Step6.

The seventh step is to deposit nickel-chromium alloy or tungsten-titanium alloy to form an embedded metal layer, as shown in Figure 6 Step7.

The eighth step is to etch away the excess nickel-chromium alloy or tungsten-titanium alloy, and deposit a thicker field oxide layer on the surface, as shown in Figure 6 Step8.

The ninth step is to etch the electrode contact area, deposit metal, and then etch the metal lead-out electrode, as shown in Figure 6 Step9.

Claims (4)

1. An N-type silicon carbide vertical metal oxide semiconductor tube, comprising: an N-type substrate (1), a drain metal (11) is connected to one side of the N-type substrate (1), and a drain metal (11) is connected to the N-type substrate (1). The other side of (1) is provided with an N-type drift region (2), a P-type base region (3) is provided in the N-type drift region (2), and a P-type body is provided in the P-type base region (3) The contact region (4) and the N-type source region (5), a gate oxide layer (6) is provided on the surface of the N-type drift region (2), and the boundaries of the gate oxide layer (6) extend to both sides and end at N type source region (5), a polysilicon gate (7) is provided on the surface of the gate oxide layer (6), and a field oxide layer (8) is provided on the polysilicon gate (7) and the N-type source region (5), A gate metal (9) is connected to the surface of the polysilicon gate (7), and a source metal (10) is connected to the N-type source region (5) and the P-type body contact region (4), characterized in that, in the The P-type body contact region (4) and the P-type base region (3) are provided with a metal layer (12), and one end of the metal layer (12) passes through the P-type body contact region (4) and is connected to the source metal (10 ) connection, the other end of the metal layer (12) passes through the P-type base region (3) and enters the N-type drift region (2). 2. The N-type silicon carbide vertical metal oxide semiconductor tube according to claim 1, characterized in that the metal layer (12) extends into the N-type drift region (2) to a depth of 0-0.3 μm. 3. The N-type silicon carbide vertical metal oxide semiconductor tube according to claim 1, characterized in that the width of the metal layer (12) is one-third to half of the width of the P-type body contact region (4) one. 4. The N-type silicon carbide vertical metal oxide semiconductor tube according to claim 1, characterized in that the material of the metal layer (12) is nickel-chromium alloy or tungsten-titanium alloy.