CN103929271B - Parallel achieving method and device for LTE system rate matching - Google Patents

Abstract

The present invention discloses a parallel implementation method and device for LTE system rate matching. The method includes: combining and storing Turbo-encoded data bit streams and parity bit 1 streams and parity bit 2 streams in rows, and storing data according to Turbo-encoded Length D, determine the column replacement style; complete column replacement row by row; special treatment for special columns after parity bit 1 stream and parity bit 2 stream are merged; read data by column from the specified position, and get the rate matching bitstream. After applying the embodiment of the present invention, the speed of rate matching can be accelerated.

Description

A parallel implementation method and device for LTE system rate matching

technical field

The present invention relates to the technical field of wireless communication, and more specifically, to the realization of rate matching in an LTE system.

Background technique

Long Term Evolution (LTE/LTE-Advanced) is a typical representative of the 4G wireless communication system, which provides a higher transmission rate for the wireless communication system. For the implementation of baseband processing of LTE/LET-Advanced, how to speed up bit-level data processing, especially the rate matching of physical transmission channels, is one of the bottlenecks of the entire baseband processing.

Existing rate matching is divided into three parts: sub-block interleaving, bit collection and bit selection. Figure 1 is a schematic diagram of rate matching specified in the 3GPP protocol. As shown in Figure 1, the coded data bit stream, parity bit 1 stream and parity bit 2 stream are first bit filled and interleaved respectively, and then the data is stored in the ring memory through bit collection, and finally the output is obtained through bit selection calculation The data start position and data size, and the corresponding data in the ring memory are removed from the padding bit output to obtain the result of rate matching.

It can be seen that padding bits need to be added during the sub-block interleaving process, and bit padding bits need to be removed during the bit selection process. The above serial implementation method is slow and has a large hardware overhead.

Contents of the invention

(1) Technical problems to be solved

Aiming at the problems of slow speed and large hardware overhead in the serial implementation method of rate matching in the LTE system, the present invention proposes a parallel implementation method and device for rate matching in the LTE system.

(2) Technical solutions

In order to solve the above technical problems, the present invention proposes a parallel implementation method of LTE system rate matching on the one hand, the method comprising:

Step S1, combining the data bit stream, the parity bit 1 stream and the parity bit 2 stream in a row and reading them into a 2R×64 matrix, where R is a natural number, and D is the length of the data bit stream, wherein the data bit stream is stored in the first 32 columns, and the parity bit 1 stream and the parity bit 2 stream are alternately stored in the last 32 columns by row, and the data bit stream is Turbo encoded data bitstream or convolutionally encoded data bitstream;

Step S2, determine the column permutation pattern of each row of the combination matrix according to the length of the data bit stream;

Step S3, perform column replacement row by row according to the column replacement pattern of each row of the merge matrix;

Step S4, find the specific column where the first bit of the check bit 2 stream is located in the merged matrix after the column permutation, and perform row permutation on this column;

Step S5, starting to read the data column by column from the designated position, to obtain the rate matching result;

According to an embodiment of the present invention, the combination matrix has the following characteristics: the sub-matrix [R×32] stores the data bit stream; the sub-matrix [2R×64] stores the parity bit stream, parity bit 1 stream and parity bit 2 The streams are stored alternately; the remaining elements of the matrix are filled with 0 bits.

According to an embodiment of the present invention, in the step S2, according to the data length D, 8 kinds of column replacement patterns of the combination matrix are determined, and these 8 kinds of column replacement patterns correspond to the row where the parity bit 1 stream in the combination matrix is located. There are 4 types of column permutation patterns in the row where the check bit 2 stream is located, wherein the data length D=K+4, K represents the length of the coding block, and 4 represents the number of tail bits after coding.

According to an embodiment of the present invention, each column permutation pattern has a total of 64 columns, wherein the first 32 columns represent the column permutation pattern of the data bit stream, and the last 32 columns represent the column permutation pattern of the check bit 1 stream or parity bit 2 stream .

According to an embodiment of the present invention, in step S3, starting from N=0 and incrementing to R-1 with a step size of 1, where N is a natural number, the column permutation operation is completed row by row for the merging matrix according to the column permutation pattern, and Two rows are processed at a time.

According to one embodiment of the present invention, in step S4, find the specific column where the first bit of the parity bit 2 stream is located in the merged matrix after the column permutation, and perform row permutation for pairwise exchange of the column .

According to an embodiment of the present invention, in step S5, the starting column position k ₀ of the output data is calculated, and the data is read column by column starting from this column, wherein only the first R rows are read from the first 32 columns of the merge matrix.

Another aspect of the present invention proposes an LTE system rate matching device, including:

Bit stream merging device: the device combines data bit stream, parity bit 1 stream and parity bit 2 stream in a row and reads them into a 2R×64 matrix, where R is a natural number, and D is the length of the data bit stream, wherein the data bit stream is stored in the first 32 columns, and the parity bit 1 stream and the parity bit 2 stream are alternately stored in the last 32 columns by row, and the data bit stream is Turbo encoded data bitstream or convolutionally encoded data bitstream.

Column permutation pattern determination device: the device determines the column permutation pattern of each row of the combination matrix according to the length of the data bit stream.

Combined matrix column replacement device: the device performs column replacement row by row according to the column replacement pattern of each row of the merged matrix.

Row permutation device: this device finds the specific column where the first bit of the parity bit 2 stream is located in the column permuted combination matrix, and performs row permutation on this column.

Bit stream output device: This device reads data column by column from the specified position, and obtains the rate matching result.

According to an embodiment of the present invention, the merging matrix in the bit stream merging device has the following characteristics: the sub-matrix [R×32] stores the data bit stream; the sub-matrix [2R×64] stores the verification bit stream, and the verification The bit 1 stream and check 2 bit stream are stored alternately; the remaining elements of the matrix are filled with 0 bits.

According to an embodiment of the present invention, the column replacement pattern determination device determines 8 column replacement patterns of the combination matrix according to the data length D, and these 8 column replacement patterns correspond to the row where the check bit 1 stream in the combination matrix is located. There are 4 types of column permutation patterns in the row where the check bit 2 stream is located, wherein the data length D=K+4, K represents the length of the coding block, and 4 represents the number of tail bits after coding.

According to an embodiment of the present invention, each column replacement pattern of the column replacement pattern determination device has a total of 64 columns, wherein the first 32 columns represent the column replacement pattern of the data bit stream, and the last 32 columns represent the check bit 1 stream or parity bit stream. Checks the column permutation pattern for bit2 streams.

According to an embodiment of the present invention, in the unit for replacing the columns of the merged matrix, start from N=0 and increase to R-1 with a step size of 1, where N is a natural number, and complete the merged matrix row by row according to the column replacement pattern Column permutation operations, and process two rows at a time.

According to an embodiment of the present invention, the row permutation device finds the specific column where the first bit of the parity 2 bit stream is located in the merged matrix after the column permutation, and performs row permutation of two-by-two exchange on the column .

According to an embodiment of the present invention, the bit stream output device calculates the starting column position k ₀ of the output data, and reads data column by column starting from this column, wherein the first 32 columns of the merge matrix only read the first R rows.

(3) Beneficial effects

By adopting the method of the present invention, the bit collection and bit selection are completed in the sub-block interleaving process, and the bit collection and bit selection operations are completed after the sub-block interleaving is completed, and there is no need to add padding bits in the sub-block interleaving process, which improves the rate matching speed. At the same time, the hardware overhead required for bit stuffing and stuffing bit removal is reduced, thus reducing the hardware scale during implementation.

Description of drawings

Accompanying drawing 1 is the rate matching schematic diagram that 3GPP agreement stipulates;

Accompanying drawing 2 LTE system rate matching flowchart of the present invention;

Accompanying drawing 3 is the structural diagram of LTE system rate matching device of the present invention;

Accompanying drawing 4 is the schematic diagram of the special column processing procedure of LTE system rate matching of the present invention;

Accompanying drawing 5 is pattern 0 after sub-block row replacement and verification 2 special processing;

Accompanying drawing 6 is pattern 1 after sub-block row replacement and check 2 special processing;

Accompanying drawing 7 is pattern 2 after sub-block row replacement and check 2 special processing;

Figure 8 is the pattern 3 after sub-block column replacement and parity 2 special processing.

detailed description

The rate matching method that the present invention proposes comprises the following steps:

Step S1, combining the data bit stream, the parity bit 1 stream and the parity bit 2 stream in a row and reading them into a 2R×64 matrix, where R is a natural number, and D is the length of the data bit stream, wherein the data bit stream is stored in the first 32 columns, and the check bit 1 stream and the check bit 2 stream are alternately stored in the last 32 columns by row.

The data bit stream is a Turbo encoded data bit stream or a convolutionally encoded data bit stream.

Step S2. Determine the column permutation pattern of each row of the combination matrix according to the length of the data bit stream.

Step S3, perform column replacement row by row according to the column replacement pattern of each row of the merge matrix, and process two rows at a time.

Step S4: Find the specific column where the first bit of the check-2 bit stream is located in the merged matrix after the column permutation, and perform row permutation on this column.

Step S5, reading data column by column from the specified position to obtain the rate matching result.

A kind of LTE system rate matching device that the present invention proposes, as shown in Figure 3, this device comprises:

Bit stream merging device: the device combines data bit stream, parity bit 1 stream and parity bit 2 stream in a row and reads them into a 2R×64 matrix, where R is a natural number, and D is the length of the data bit stream, wherein the data bit stream is stored in the first 32 columns, and the parity bit 1 stream and the parity bit 2 stream are alternately stored in the last 32 columns by row, and the data bit stream is Turbo encoded data bitstream or convolutionally encoded data bitstream.

Column permutation pattern determination device: the device determines the column permutation pattern of each row of the combination matrix according to the length of the data bit stream.

Combined matrix column replacement device: the device performs column replacement row by row according to the column replacement pattern of each row of the merged matrix.

Row permutation device: this device finds the specific column where the first bit of the parity 2 bit stream is located in the combination matrix after the column permutation, and performs row permutation on this column.

Bit stream output device: This device reads data column by column from the specified position, and obtains the rate matching result.

It can be seen that in the present invention, there is no need to perform filling bit processing, and a row of data bit streams and a row of check bit streams are processed in parallel at the same time. The processing method is simple, the loop structure is clear, and the speed of rate matching is accelerated.

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

Accompanying drawing 2 is the flowchart of the LTE system rate matching method of the present invention. As shown in Figure 2, the present invention specifically comprises the following steps:

Step S1, combining the data bit stream, parity bit 1 stream and parity bit 2 stream into a 2R×64 matrix rowwise, wherein R is a natural number, and D is the length of the data bit stream, wherein the data bit stream is stored in the first 32 columns, and the check bit 1 stream and the check bit 2 stream are alternately stored in the last 32 columns by row.

According to the LTE protocol, there are a total of 188 types of Turbo code block lengths, of which the first 60 types of code block lengths are 8 as the progressive step length, and the range of code block length K is 40≤K≤512; among them, there are 32 types of code block lengths with 16 as the step length. Progressive step length, the range of code block length K is 528≤K≤1024; among them, there are 32 kinds of code block lengths with 32 as the progressive step length, and the range of code block length K is 1056≤K≤2048; among them, there are 64 kinds of code block lengths with 64 is the progressive step length, and the range of code block length K is 2112≤K≤6144;

The present invention uses 64 as the number of columns of the merging matrix, the first 32 columns store the data bit stream, and the last 32 columns store the parity bit 1 stream and the parity bit 2 stream, because the parity bit 1 stream and the parity bit 2 stream are divided into rows Alternate storage, so the maximum number of rows of the matrix is 2R, where R represents the length of the first-rate bit,

Table 1 below is the organizational structure table of the data matrix, and the elements in the table represent the index address of each data.

In Table 1, * indicates the 0 element of non-local code block data, 100 etc. start with 1 to indicate the index address of check 1 data, 200 etc. start with 2 to indicate the index address of check 2 data, and the three bit streams are represented by different patterns respectively.

Step S2. Determine the column permutation pattern of the merge matrix according to the data length.

Since the data in the present invention is organized without adding padding bits, it is necessary to improve the original column replacement pattern. According to the data length D of the coded bit stream, four types of column permutation patterns are obtained. Wherein the data length D=K+4, K represents the length of the coding block, and 4 represents the tail bit length. The present invention needs to select a type of column permutation mode for processing according to the encoded data length D.

Although the data organization of the present invention does not add padding bits, the four types of column permutation patterns need to be obtained according to the number of padding bits for 188 different data lengths, and the number of padding bits ND =R*32- _D .

For 188 coded output lengths, the filling bits of each stream have the following rules:

Corresponding padding bits _ND = 28, a total of 127 kinds of code block length K; example K = 6144;

Corresponding padding bits _ND = 20, a total of 15 kinds of code block length K; example K = 488;

Corresponding padding bits _ND = 12, a total of 31 kinds of code block length K; example K = 496;

Corresponding padding bits _ND = 4, a total of 15 kinds of code block length K; example K = 504;

The column permutation patterns are divided into four types according to the number of padding bits. Since the data bit stream and parity bit stream 1 use the same column permutation pattern, and parity bit stream 2 uses another column permutation pattern, each type of column permutation pattern is divided into two types:

The first one is to combine the data bit stream and the check bit 1 stream to generate a 64-column permutation pattern;

In the second type, the data bit stream and the check bit 2 stream are combined to generate a 64-column permutation pattern.

To sum up, the four types and eight column replacement styles are sorted out as follows:

When N _D =28, the first type of column replacement style:

The first column replacement style is:

{4, 20, 12, 28, 8, 24, 16, 0, 6, 22, 14, 30, 10, 26, 18, 2, 5, 21, 13, 29, 9, 25, 17, 1, 7 , 23, 15, 31, 11, 27, 19, 3, 36, 52, 44, 60, 40, 56, 48, 32, 38, 54, 46, 62, 42, 58, 50, 34, 37, 53 ,45,61,41,57,49,33,39,55,47,63,43,59,51,35}

The second column replacement style is:

{4, 20, 12, 28, 8, 24, 16, 0, 6, 22, 14, 30, 10, 26, 18, 2, 5, 21, 13, 29, 9, 25, 17, 1, 7 , 23, 15, 31, 11, 27, 19, 3, 37, 53, 45, 61, 41, 57, 49, 33, 39, 55, 47, 63, 43, 59, 51, 35, 38, 54 , 46, 62, 42, 58, 50, 34, 40, 56, 48, 32, 44, 60, 52, 36}

When N _D =20, the second type of column replacement style:

The first column replacement style is:

{12, 28, 20, 4, 16, 0, 24, 8, 14, 30, 22, 6, 18, 2, 26, 10, 13, 29, 21, 5, 17, 1, 25, 9, 15 , 31, 23, 7, 19, 3, 27, 11, 44, 60, 52, 36, 48, 32, 56, 40, 46, 62, 54, 38, 50, 34, 58, 42, 45, 61 , 53, 37, 49, 33, 57, 41, 47, 63, 55, 39, 51, 35, 59, 43}

The second column replacement style is:

{4, 20, 12, 28, 8, 24, 16, 0, 6, 22, 14, 30, 10, 26, 18, 2, 5, 21, 13, 29, 9, 25, 17, 1, 7 , 23, 15, 31, 11, 27, 19, 3, 37, 53, 45, 61, 41, 57, 49, 33, 39, 55, 47, 63, 43, 59, 51, 35, 38, 54 , 46, 62, 42, 58, 50, 34, 40, 56, 48, 32, 44, 60, 52, 36}

When N _D =12, the third type of column replacement style:

The first column replacement style is:

{20, 4, 28, 12, 24, 8, 0, 16, 22, 6, 30, 14, 26, 10, 2, 18, 21, 5, 29, 13, 25, 9, 1, 17, 23 , 7, 31, 15, 27, 11, 3, 19, 52, 36, 60, 44, 56, 40, 32, 48, 54, 38, 62, 46, 58, 42, 34, 50, 53, 37 ,61,45,57,41,33,49,55,39,63,47,59,43,35,51}

The second column replacement style is:

{20, 4, 28, 12, 24, 8, 0, 16, 22, 6, 30, 14, 26, 10, 2, 18, 21, 5, 29, 13, 25, 9, 1, 17, 23 , 7, 31, 15, 27, 11, 3, 19, 53, 37, 61, 45, 57, 41, 33, 49, 55, 39, 63, 47, 59, 43, 35, 51, 54, 38 ,62,46,58,42,34,50,56,40,32,48,60,44,36,52}

When N _D =4, the fourth type of column replacement style:

The first column replacement style is:

{28, 12, 4, 20, 0, 16, 8, 24, 30, 14, 6, 22, 2, 18, 10, 26, 29, 13, 5, 21, 1, 17, 9, 25, 31 , 15, 7, 23, 3, 19, 11, 27, 60, 44, 36, 52, 32, 48, 40, 56, 62, 46, 38, 54, 34, 50, 42, 58, 61, 45 ,37,53,33,49,41,57,63,47,39,55,35,51,43,59}

The second column replacement style is:

{28, 12, 4, 20, 0, 16, 8, 24, 30, 14, 6, 22, 2, 18, 10, 26, 29, 13, 5, 21, 1, 17, 9, 25, 31 , 15, 7, 23, 3, 19, 11, 27, 61, 45, 37, 53, 33, 49, 41, 57, 63, 47, 39, 55, 35, 51, 43, 59, 62, 46 ,38,54,34,50,42,58,32,48,40,56,36,52,44,60}

Step S3, perform column replacement row by row according to different column replacement patterns of 64 columns in each row of the merge matrix.

First, start from N=0 and increase to R-1 with a step size of 1. R represents the number of rows of the data bit stream. Since two rows of data need to be processed at a time, the first row is the merged data of the data bit stream and the parity bit 1 stream, and the second row is the merged data of the data bit stream and the parity bit 2 stream.

Next, the column permutation is done row by row using the column permutation pattern.

After selecting a type of column permutation pattern according to the encoded bit stream data length D, two rows of data are processed each time in a loop. The processing method is to perform interleaving operations according to different column permutation patterns to complete the column permutation. ;

Step S4, find the specific column where the first bit of the parity bit 2 stream is located in the merged matrix after the column permutation, and perform row permutation of two-by-two exchange on the column deal with.

After the check bit 2 stream adopts the column replacement mode, special column replacement processing is required. The processing method is to find the column that needs special processing, exchange the data of the column two by two, and select 2R-1 data storage.

Accompanying drawing 4 is the schematic diagram of special column processing process.

As shown in Figure 4, since the column length is up to 2*R, pairwise exchange can be completed, and then 2*R-1 data can be completed.

The columns that require special handling are:

Corresponding to the first type of column replacement mode, the 59th column needs special treatment;

Corresponding to the second type of column replacement mode, the 57th column needs special treatment;

Corresponding to the third type of column replacement mode, the 58th column needs special treatment;

Corresponding to the fourth type of column replacement mode, the 56th column needs special treatment;

After processing in steps S3 and S4, four types of data storage structures with different column replacement modes are obtained:

Accompanying drawing 5 shows the data organization structure after the first type of column replacement, accompanying drawing 6 shows the data organization structure after the second type of column replacement, accompanying drawing 7 shows the data organization structure after the third type of column replacement, and accompanying drawing 8 shows the fourth type of column Data organization structure after replacement.

The number of rows in the data matrix after each type of column permutation includes five cases of R-1, R, 2(R-1), 2R-1, and 2R, so a vector with 64 elements is required to record the length of each column.

Step S5, reading data column by column from the specified position to obtain the rate matching result.

In the present invention, the starting column position k ₀ of the output data is calculated, in It is a multiple of the code block length divided by 32, N _cb indicates the size of the rate matching soft buffer, and rv _idx indicates the redundant version information. It can be known by calculation that the value of k ₀ is determined by rv _idx .

In addition, since the present invention combines and stores the check bit 1 stream and the check bit 2 stream, when k ₀ is greater than 32R, the starting position is at

Each bit selection is always selected from the beginning of the specified row, and the matrix after column permutation has no filling bits, so the output of the matrix by column is changed to the specified column from k ₀ (the specified column represented by the ellipse in the table below) by Column output, the matrix output and bit selection are combined for processing, as shown in Table 3 below.

So far, the process of rate matching is completed.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.

Claims (14)

1. a kind of Parallel Implementation method of LTE system rate-matched, the method includes：

Step S1, data bit flow, check bit 1 are flowed and check bit 2 flows and merges and read in 2R × 64 by line mode Matrix, wherein R are natural number, andD is the length of data bit flow, wherein data bit flow is stored in into front 32 Row, the stream of check bit 1 and check bit 2 flow 32 row after being alternately stored in by row, and the data bit flow is the number after Turbo codings According to the data bit flow after bit stream or convolutional encoding；

Step S2, the column permutation pattern often gone according to the length of data bit flow determination merging matrix；

Step S3, the column permutation pattern often gone according to merging matrix, carry out line by line column permutation；

The particular column that step S4, merging after the column permutation look for check bit 2 to flow the 1st bit in matrix is located, and it is right The row carry out line replacement；

Step S5, from specified location start by row read data, obtain rate-matched result.

2. LTE system speed matching method according to claim 1, it is characterised in that merge matrix and there are following features： Submatrix [R × 32] data storage bit stream；Submatrix [2R × 64] stores check bit stream, and check bit 1 flows and verify ratio Special 2 stream is alternately stored；Matrix remaining element fills 0 bit.

3. LTE system speed matching method according to claim 1, it is characterised in that in step S2, according to institute State data length D and determine that 8 kinds merge matrix column displacement pattern, this 8 kinds of column permutation patterns are corresponded to merge in matrix respectively and verified The stream of bit 1 to be expert at and flow each 4 kinds of column permutation patterns of being expert at, wherein data length D=K+4, K presentation codes with check bit 2 Block length, tail number of bits after 4 presentation codes.

4. LTE system speed matching method according to claim 3, it is characterised in that every kind of column permutation pattern amounts to 64 Row, wherein it is front 32 row represent data bit flow column permutation pattern, afterwards 32 row represent check bits 1 flow or check bit 2 stream Column permutation pattern.

5. LTE system speed matching method according to claim 1, it is characterised in that in step s3, from the beginning of N=0 And R-1 is incremented to for 1 by step-length, and column permutation operation is completed line by line to merging matrix according to column permutation pattern, and it is per treatment Two rows.

6. LTE system speed matching method according to claim 1, it is characterised in that in step s 4, puts in the row The particular column that merging after changing looks for check bit 2 to flow the 1st bit in matrix is located, and the row that the row are exchanged two-by-two is put Change.

7. LTE system speed matching method according to claim 1, it is characterised in that in step s 5, calculates output number According to starting column location k₀, and start to read data by row from the row, wherein merging the read-only front R rows of front 32 row of matrix.

8. a kind of LTE system rate matching apparatus, including：

Bit stream merges device：The device flows data bit flow, check bit 1 and check bit 2 flows and merges simultaneously by line mode 2R × 64 matrix is read in, wherein R is natural number, andD for data bit flow length, wherein by data Bit stream is stored in front 32 row, and the stream of check bit 1 and check bit 2 flow 32 row after being alternately stored in by row, and the data bit flow is Data bit flow or the data bit flow after convolutional encoding after Turbo codings；

Column permutation pattern determining device：The device determines the column permutation that merging matrix is often gone according to the length of the data bit flow Pattern；

Merge rectangular array displacement apparatus：The device carries out line by line column permutation according to the column permutation pattern that matrix is often gone is merged；

Line replacement device：The spy that the device merging after the column permutation looks for check bit 2 to flow the 1st bit in matrix is located Fixed row, and line replacement is carried out to the row；

Bit stream output device：The device starts to read data by row from specified location, obtains rate-matched result.

9. LTE system rate matching apparatus according to claim 8, it is characterised in that the bit stream merges in device Merging matrix there are following features：Submatrix [R × 32] data storage bit stream；Submatrix [2R × 64] stores check bit Stream, the stream of check bit 1 and the stream of check bit 2 are alternately stored；Matrix remaining element fills 0 bit.

10. LTE system rate matching apparatus according to claim 8, it is characterised in that the column permutation pattern determines dress Put and determine that 8 kinds merge matrix column displacement pattern according to the data length D, this 8 kinds of column permutation patterns correspond to merge square respectively The stream of check bit 1 to be expert at and flow be expert at each 4 kinds of column permutation patterns, wherein data length D=K+4, K with check bit 2 in battle array Presentation code block length, tail number of bits after 4 presentation codes.

11. LTE system rate matching apparatus according to claim 10, it is characterised in that the column permutation pattern determines Every kind of column permutation pattern of device amounts to 64 row, wherein front 32 row represent the column permutation pattern of data bit flow, afterwards 32 row are represented The column permutation pattern that check bit 1 flows or check bit 2 flows.

12. LTE system rate matching apparatus according to claim 8, it is characterised in that in the merging matrix column permutation In device, start from N=0 and be incremented to R-1 for 1 by step-length, column permutation is completed line by line to merging matrix according to column permutation pattern Operation, and two row per treatment.

13. LTE system rate matching apparatus according to claim 8, it is characterised in that the line replacement device is described The particular column that merging after column permutation looks for check bit 2 to flow the 1st bit in matrix is located, and the row are exchanged two-by-two Line replacement.

14. LTE system rate matching apparatus according to claim 8, it is characterised in that the bit stream output device meter Calculate the starting column location k of output data₀, and start to read data by row from the row, wherein merging the read-only front R of front 32 row of matrix OK.