CN103903989A - Method for forming semiconductor packaging structure - Google Patents

Abstract

A method for forming a semiconductor packaging structure, comprising: providing a semiconductor chip, sequentially forming a heat-resistant metal layer and a metal wetting layer on a pad of the chip, sequentially forming an adhesion layer and a barrier layer on the metal wetting layer, forming Solder is reflowed to form columnar bumps; a lead frame is provided, and the chip formed with columnar bumps is flipped on the lead frame, and the columnar bumps are electrically connected to the inner pins of the lead frame; forming and sealing the chip, columnar bumps and leadframes, and expose the plastic encapsulation layer of the outer pins. The invention reduces the lateral area occupied by the package structure, reduces the volume of the whole package structure accordingly, and improves the integration degree of the package structure.

Description

Method for forming semiconductor package structure

technical field

The invention relates to the field of semiconductor packaging, in particular to a semiconductor packaging structure and a method for forming it.

Background technique

With the development of electronic products such as mobile phones and notebook computers towards miniaturization, portable, ultra-thin, multimedia and low-cost to meet the needs of the public, high-density, high-performance, high-reliability and low-cost packaging forms and their Assembly technology has been rapidly developed. Compared with expensive BGA (Ball Grid Array) and other packaging forms, new packaging technologies that have developed rapidly in recent years, such as Quad Flat No-lead QFN (Quad Flat No-leadPackage) packaging, due to its good thermal performance and electrical The advantages of performance, small size, low cost and high productivity have triggered a new revolution in the field of microelectronic packaging technology.

Fig. 1 is the structure schematic diagram of existing QFN package structure, and described QFN package structure comprises: semiconductor chip 14, has pad 2 on the described semiconductor chip 1; Pin 3 (lead frame), described pin 3 surrounds all Arrange around the semiconductor chip 1; metal wire 4, the metal wire 4 electrically connects the pad 2 of the semiconductor chip 1 with the pin 3 surrounding the semiconductor chip 1; plastic packaging material 5, the plastic packaging material 5 connects the semiconductor chip 1 , the metal wire 4 and the pin 3 are sealed, the surface of the pin 3 is exposed on the bottom surface of the plastic packaging material, and the electrical connection between the semiconductor chip 1 and the external circuit is realized through the pin 3 .

The existing packaging structure occupies a large volume, which is not conducive to the improvement of the integration degree of the packaging structure.

Contents of the invention

The problem solved by the invention is how to improve the integration degree of the packaging structure.

In order to solve the above problems, the present invention provides a method for forming a semiconductor package structure, comprising: providing a semiconductor chip, the surface of the chip is provided with a pad and a passivation layer, and the passivation layer is provided with an exposed pad. The first opening; a heat-resistant metal layer and a metal wetting layer are sequentially formed on the pad and the passivation layer of the chip; a photoresist is formed on the metal wetting layer, and the photoresist is provided to expose the metal wetting above the chip pad The second opening of the layer; sequentially forming an adhesion layer and a barrier layer on the metal wetting layer in the second opening; forming solder on the barrier layer; removing photoresist; etching the heat-resistant metal layer and the metal wetting layer on the passivation layer until the passivation layer is exposed; reflow the solder to form a columnar bump; provide a lead frame, the lead frame is provided with a number of discrete pins, and the inner pin and the outer pin are located on opposite sides of the pin; the columnar bump will be formed The chip of the point is flip-chip on the lead frame, and the columnar bump is electrically connected with the inner pin; a plastic sealing layer is formed to seal the chip, the columnar bump and the lead frame, and expose the outer pin.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the method for forming the packaging structure of the present invention, the semiconductor chip is flip-chip placed above the pins, and the pads on the semiconductor chip are electrically connected to the inner pins through columnar bumps, so that the lateral area occupied by the formed packaging structure is reduced, and the entire The volume of the package structure is small, and the integration degree of the package structure is improved.

Description of drawings

FIG. 1 is a structural schematic diagram of a prior art packaging structure;

2 to 11 are schematic cross-sectional structural views of the forming process of the packaging structure according to the embodiment of the present invention.

Detailed ways

The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Firstly, referring to FIG. 2 , a semiconductor chip 200 is provided, the surface of the semiconductor chip 200 is provided with a pad 201 and a passivation layer 202 , and the passivation layer 202 is provided with a first opening exposing the pad 201 .

The pad 201 is the functional output terminal of the chip 200, and finally realizes the conductive transition of the electrical function through the post-formed stud bump 206; the material of the passivation layer 202 includes silicon oxide, silicon nitride, silicon oxynitride, poly Dielectric materials such as imide and benzenetributene or their mixtures are used to protect the circuits in the chip 200 .

It should be noted that the pad and passivation layer of the chip can be the initial pad and the initial passivation layer of the chip, and can also be a transition pad and a passivation layer formed according to the needs of circuit layout design; The way of the pad and passivation layer is mainly to use the rewiring process technology to transfer the initial pad and passivation layer to the transition pad and passivation layer through one or more layers of rewiring. The rewiring process technology is an existing mature process, which is well known to those skilled in the art, and will not be repeated here.

Next, referring to FIG. 3 , a heat-resistant metal layer 203 and a metal wetting layer 204 are sequentially formed on the pad 201 and the passivation layer 202 of the chip 200 .

The material of the heat-resistant metal layer 203 may be titanium Ti, chromium Cr, tantalum Ta or a combination thereof, and Ti is preferred in the present invention. The material of the metal wetting layer 204 may be one of copper Cu, aluminum Al, nickel Ni or a combination thereof, wherein the preferred metal wetting layer 204 is Cu. The refractory metal layer 203 together with the metal wetting layer 204 constitutes the seed layer of the final structure. The method of the heat-resistant metal layer 203 and the metal wetting layer 204 can also adopt the existing method of evaporation or sputtering or physical vapor deposition, and the preferred method is sputtering. Of course, according to the common knowledge of those skilled in the art, the forming method is not limited to the sputtering method, other applicable methods can be applied to the present invention, and the thickness of the formed heat-resistant metal layer 203 and metal wetting layer 204 is also based on the actual Depends on process requirements.

Next, referring to FIG. 4 , a photoresist 205 is formed on the metal wetting layer 204 , and the photoresist 205 is provided with a second opening exposing the metal wetting layer 204 above the pad 201 of the chip 200 .

The method for forming the photoresist 205 may be spin coating, and the specific steps of these methods are well known to those skilled in the art, and will not be repeated here. After the photoresist 205 is formed, the shape of the bonding pad 201 can be defined by the existing photolithography and developing technology, so that an opening is formed in the photoresist 205 to expose the metal wetting layer 204 on the bonding pad 201 .

In other embodiments of the present invention, the second opening is smaller than the first opening, that is, the opening size of the photoresist 205 is smaller than the opening size of the passivation layer of the chip 200; It can fall into the first opening, avoiding the reliability problem that the stud bump 206 is formed on the passivation layer 202 to cause excessive stress and the solder pad 201 is easy to be brittle.

Next, referring to FIG. 5 , an adhesion layer 206 a and a barrier layer 206 b are sequentially formed on the metal wetting layer 204 in the second opening.

In this step, using the remaining photoresist 205 on the chip 200 as a mask, an adhesion layer 206a and a barrier layer 206b are sequentially formed in the second opening formed in the previous step and above the metal wetting layer 204. The specific process It can be done by electroplating. Of course, according to the common knowledge of those skilled in the art, the forming method is not limited to electroplating, and other suitable methods can be applied to the present invention. The material of the adhesion layer 206a is copper Cu, and the material of the barrier layer 206b is nickel Ni.

The copper thickness of the adhesion layer 206a is 5-50 μm, specifically 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm or 50 μm. The adhesion layer 206 a is the column structure main body of the final electrical output terminal, ie, the column bump 206 . The adhesion layer 206a provides a sufficient material space in space, which ensures that the subsequently formed solder 206c can be firmly placed on the adhesion layer 206a after reflow without deviation, and also improves the bonding force with the solder 206c At the same time, because of the columnar structure of the adhesive layer 206a, the size of the solder 206c can be reduced. On the premise of ensuring the reliability of the physical connection in the welding process of the final product, the number of functional output ports in the unit space is improved, and the density can be better met. Packaging requirements with multiple pitches and functional outputs.

The nickel barrier layer 206b has a thickness of 1.5 μm˜3 μm, specifically 1.5 μm, 2 μm, 2.5 μm or 3 μm. The function of the barrier layer 206b is to prevent the material that subsequently forms the solder bump from diffusing into the metal wetting layer 204. When the thickness of the Ni layer is less than 1.5 μm, the Ni will eventually disappear due to the diffusion effect between adjacent metals, and thus cannot effectively block Subsequent solder bumps diffuse into the metal wetting layer 204; when the thickness of the Ni layer is greater than 3 μm, the electrical resistivity of the Ni metal itself is poor, resulting in an increase in resistivity, thereby affecting the electrical and thermal properties of the final product. Therefore, on the one hand, a barrier layer (Ni) with an appropriate thickness can prevent itself from disappearing due to the diffusion effect, thereby effectively preventing the pores between the solder and the metal wetting layer due to the formation of intermetallic compounds; If the layer is too thick, the resistivity will increase and affect the electrothermal performance of the product.

Next, referring to FIG. 6, solder 206c is formed on the barrier layer 206b.

In this step, the photoresist 205 is still used as a mask to form solder 206c on the barrier layer 206b. The material for forming the solder 206c is pure tin or tin alloy, such as tin-silver alloy, tin-copper alloy, tin-silver alloy, etc. copper alloy etc. The method of forming the solder 206c may be electrolytic plating, sputtering, screen printing, or directly implanting prefabricated solder balls. The specific steps of these methods are well known to those skilled in the art and will not be repeated here.

In this embodiment, the thickness of the solder 206c is 5 μm-70 μm, and the specific thickness is, for example, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm or 70 μm. The columnar structure formed by the above steps can greatly reduce the amount of solder 308a used. On the one hand, the cost of materials is saved. More importantly, the size of a small amount of solder 206c after reflow is small, which can meet the fine pitch of pads 201 or more in the same space. Application requirements of multi-function output points.

Next, referring to FIG. 7 , the photoresist 205 is removed; using the adhesion layer 206a as a mask, the heat-resistant metal layer 203 and the metal wetting layer 204 on the passivation layer 202 are etched until the passivation layer is exposed.

After the above process is completed, the photoresist 205 can be removed, and can be removed by wet method or stripping. The specific steps of these methods are well known to those skilled in the art and will not be repeated here.

In this embodiment, the metal wetting layer 204 and the heat-resistant metal layer 203 on the surface of the chip 200 other than the solder 206c can be removed by spraying the acid solution or immersing the wafer in the acid solution, thereby exposing the passivation layer 202 .

Next, referring to FIG. 8 , the solder is reflowed to form stud bumps 206 .

In this embodiment, the solder 206c is melted into a hemispherical shape by reflow heating to form a columnar bump 206 composed of an adhesion layer 206a, a barrier layer 206b and a solder 206c. At this time, the functional output terminal of the chip 200 is transitioned from the pad 201 On the stud bump 206 , the stud bump 206 becomes the electrical output terminal of the chip 200 .

Next, referring to FIG. 9 , a lead frame 300 is provided. The lead frame 300 is provided with several discrete pins, and the inner pins 301 and outer pins 302 are arranged on opposite sides of the pins.

The lead frame 300 is formed by a punching or etching process, the inner pin 301 is used as the electrical input terminal of the pin and connected to the active device or passive device, and the outer pin is used as the electrical output terminal to connect with the next level of packaging such as printing. Circuit boards, etc. for interconnection.

Next, referring to FIG. 10 , the chip 200 formed with stud bumps 206 is flip-chipped on the lead frame 300 , and the stud bumps 206 are electrically connected to the inner pins 301 .

The pads 201 on the chip 200 are electrically connected to the inner pins 301 through the stud bumps 206, so that the lateral area occupied by the formed packaging structure is reduced, the volume of the entire packaging structure is small, and the integration degree of the packaging structure is improved. At the same time, compared with the traditional method of interconnecting the pad 201 and the inner pin 301 through metal leads, the flip-chip structure of the present invention greatly shortens the transmission distance between the chip 200 and the inner pin 201, and the resistance and thermal resistance are also corresponding The performance of the whole product is improved, and the stud bump 206 as the output end of the chip 200 can better meet the requirements of high-power products.

After the stud bumps 206 are interconnected with the inner pins 301 , a reflow process is required. The reflow process has the functions of solidifying the solder and aligning, so that the stud bumps 206 and the inner pins 301 can be accurately aligned and fixed.

Then, please refer to FIG. 11 , forming a plastic encapsulation layer 400 that seals the chip 200 , stud bumps 206 and lead frame 300 and exposes the outer pins 302 .

The plastic encapsulation layer 400 surrounds the chip 200 , fills the area between the chip 200 and the inner pins 301 , the plastic encapsulation layer 400 also fills the openings between the pins, and the bottom of the plastic encapsulation layer 400 exposes the outer pins 302 . When filling the plastic encapsulation layer 400, because the opening between the pins and the space between the chips 200 and the space between the chip 200 and the inner pins 301 are connected, the fluidity of the plastic encapsulation material is improved, thereby preventing in the plastic encapsulation layer 400 Defects such as voids are generated.

The plastic sealing layer 400 is used to protect and isolate the packaging structure, and the material of the plastic sealing layer 400 is resin, and the resin can be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole Resin; The resin can also be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, Polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol; the plastic sealing layer 400 can also be other suitable plastic sealing materials.

The forming process of the plastic sealing layer 400 is an injection molding process or a transfer molding process (transfermolding). The forming process of the plastic encapsulation layer 400 may also be other suitable processes.

After forming the plastic encapsulation layer 400 , it also includes dividing the plastic encapsulation layer 400 by a cutting process to form a plurality of discrete semiconductor packaging units.

Please refer to Figure 11 for the package structure formed by the above method, including:

Chip 200, the surface of the chip 200 is provided with a pad 201 and a passivation layer 202, the passivation layer 202 is provided with a first opening exposing the pad 201, the pad 201 is provided with a seed layer and a stud bump 206, the seed layer is connected to the pad 201, and the stud bump 206 is stacked on the seed layer;

A lead frame 300, the lead frame 300 is provided with several discrete pins, and the inner pins 301 and the outer pins 302 are arranged on opposite sides of the pins;

The chip 200 is flip-chip mounted on the lead frame 300, and the stud bumps 206 are connected to the inner pins 301;

A plastic sealing layer 400, the plastic sealing layer 400 seals the chip 200, the stud bumps 206 and the lead frame 300, and exposes the external pins 302;

The stud bumps 206 are sequentially composed of an adhesion layer 206a, a barrier layer 206b and a solder 206c stacked from bottom to top, the adhesion layer 206a is connected to the seed layer, the barrier layer 206b is stacked on the adhesion layer 206a, and the solder 206c is stacked on the barrier layer 206b.

Specifically, the seed layer is composed of a heat-resistant metal layer 203 and a metal wetting layer 204 stacked, the heat-resistant metal layer 203 is connected to the pad 201, and the metal wetting layer 204 is stacked on the heat-resistant metal layer 203 .

The stud bumps 206 are disposed in the first opening.

The material of the heat-resistant metal layer 203 is titanium, chromium, tantalum or a combination thereof.

The material of the metal wetting layer 204 is copper, aluminum, nickel or a combination thereof.

The material of the adhesion layer 206a is copper, and the thickness of the copper is 5-50 μm.

The material of the barrier layer 206b is nickel, and the thickness of nickel is 1.5-3 μm.

The material of the solder 206c is pure tin or tin alloy, and the thickness of the solder 206c is 5-70 μm.

In summary, the packaging structure and the method for forming the packaging structure according to the embodiment of the present invention, the semiconductor chip is flip-mounted on the inner pin, and the pad on the semiconductor chip and the lead are connected through the connection structure formed by the seed layer and the columnar bump block. The pins are electrically connected, so that the volume of the entire packaging structure is small, and the forming method of the packaging structure can realize chip-scale packaging of the lead frame structure, thereby improving the integration degree of the packaging structure.

Although the present invention is disclosed above with preferred embodiments, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (10)

1. A method for forming a semiconductor package structure, comprising: A semiconductor chip is provided, the surface of the chip is provided with a pad and a passivation layer, and the passivation layer is provided with a first opening exposing the pad; A heat-resistant metal layer and a metal wetting layer are sequentially formed on the pad and passivation layer of the chip; forming a photoresist on the metal wetting layer, the photoresist having a second opening exposing the metal wetting layer above the chip pad; sequentially forming an adhesion layer and a barrier layer on the metal wetting layer in the second opening; forming solder on the barrier layer; remove photoresist; Etching the heat-resistant metal layer and the metal wetting layer on the passivation layer until the passivation layer is exposed; Reflow solder to form stud bumps; providing a lead frame, the lead frame is provided with several discrete pins, and the inner pins and outer pins are arranged on opposite sides of the pins; Flip-chip the chip with the columnar bumps formed on the lead frame, the columnar bumps are electrically connected to the inner pins; A plastic sealing layer is formed to seal the chip, the stud bump and the lead frame, and expose the outer pins. 2 . The method for forming a semiconductor package structure according to claim 1 , wherein the second opening is smaller than the first opening. 3. The method for forming a semiconductor package structure according to claim 1, wherein the material of the heat-resistant metal layer is titanium, chromium, tantalum or a combination thereof. 4. The method for forming a semiconductor package structure according to claim 1, wherein the material of the metal wetting layer is copper, aluminum, nickel or a combination thereof. 5. The method for forming a semiconductor package structure according to claim 1, wherein the material of the adhesion layer is copper. 6 . The method for forming a semiconductor package structure according to claim 5 , wherein the thickness of the copper adhesion layer is 5-50 μm. 7. The method for forming a semiconductor package structure according to claim 1, wherein the barrier layer is made of nickel. 8 . The method for forming a semiconductor package structure according to claim 7 , wherein the nickel barrier layer has a thickness of 1.5-3 μm. 9 . The method for forming a semiconductor package structure according to claim 1 , wherein the material of the solder is pure tin or a tin alloy. 10 . The method for forming a semiconductor package structure according to claim 9 , wherein the thickness of the solder is 5-70 μm. 11 .

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