CN103901804A - Servo system real-time motion controller based on DSP and FPGA and control method - Google Patents

Abstract

A real-time motion controller and control method for a servo system based on DSP and FPGA relate to the field of motion control of a servo system. The invention aims to solve the problem that the existing motion controller cannot achieve higher real-time communication. The RS422 of the present invention communicates with the FPGA, the output end of the clock circuit is connected to the input end of the FPGA and the input end of the DSP at the same time, the DSP communicates with the memory space configuration module, the memory space configuration module communicates with the FPGA, the DA conversion module, DSP and FPGA perform data interaction through the EMIF data bus. The output end of the FPGA is connected to the input end of the DA conversion module, the output end of the DA conversion module is connected to the input end of the motor, and the output end of the code disc signal access circuit is connected to the input end of the FPGA. The input or output end of the FPGA is connected to the output or input end of the drive interface of the motor control terminal. It can be used in motor control systems.

Description

Real-time Motion Controller and Control Method of Servo System Based on DSP and FPGA

technical field

The invention relates to a real-time motion controller and control method of a servo system based on DSP and FPGA. It belongs to the field of servo system motion control.

Background technique

With the continuous progress and improvement of motion control technology, motion controller, as an independent industrial automation control product, has been widely used in more and more industrial fields, especially in the field of automation control. As a control device, the motion controller takes the central logic control unit as the core, the sensor as the signal sensitive element, and the motor or power unit and the execution unit as the control objects. Its main task is to perform necessary logic and mathematical operations according to the requirements of motion control and the signals of sensor devices, and provide correct control signals for motors or other power and actuators.

The servo system, also known as the servo system, is a feedback control system used to accurately follow or reproduce a certain process. With the continuous development of productivity, the servo system is required to develop in the direction of high precision, high speed and high power, which puts forward requirements for its controller. In some servo systems, the motion controller needs to perform servo control in real time, which requires DSP and FPGA as the core processors to optimize the controller by making full use of the advantages of high-speed precision of DSP and flexibility of FPGA.

Contents of the invention

The invention aims to solve the problem that the existing motion controller cannot achieve higher real-time communication. A real-time motion controller and control method for a servo system based on DSP and FPGA are now provided.

Servo system real-time motion controller based on DSP and FPGA, which includes FPGA, DSP, motor, clock circuit, DA conversion module, code disc signal access circuit, memory space configuration module, RS422 communication interface and motor control terminal drive interface,

The data signal input or output end of the RS422 communication interface is connected to the data signal output or input end of the FPGA, and the clock signal output end of the clock circuit is connected to the clock signal input end of the FPGA and the clock signal input end of the DSP at the same time, and the DSP passes the EMIF data bus Data interaction with the memory space configuration module, the memory space configuration signal input or output of the memory space configuration module is connected to the memory space configuration signal output or input of the FPGA, the DA conversion module, DSP and FPGA perform data interaction through the EMIF data bus, and the FPGA The digital signal output end of the DA conversion module is connected to the digital signal input end of the DA conversion module, the analog signal output end of the DA conversion module is connected to the analog signal input end of the motor, and the motor code disc signal output end of the code disc signal access circuit is connected to the motor code disc of the FPGA The signal input terminal, the drive signal input or output terminal of the FPGA is connected to the drive signal output or input terminal of the drive interface of the motor control terminal.

The control method realized by the real-time motion controller of the servo system based on DSP and FPGA, the method comprises the following steps:

Step 1. The upper computer sends instructions to FPGA7 through the RS422 communication interface, and at the same time, FPGA7 receives the acquisition signal of the motor control terminal drive interface; and choose one to perform step 2 or step 3;

Step 2. The FPGA transmits the received command to the DSP through the EMIF data bus of the DSP's external memory interface, and the DSP processes the command and sends the processing result to the memory space configuration module through the EMIF data bus. At the same time, the FFPGA7 and the memory space configuration module 4. Communication; the DA conversion module receives the digital signal of the DSP through the EMIF data bus and performs digital-to-analog conversion to obtain a voltage analog signal, so as to control the motor and perform step 4;

Step 3, the DA conversion module performs digital-to-analog conversion on the drive signal received by the FPGA from the drive interface of the motor control terminal, and then controls the motor, and performs step 4;

Step 4. Use the code disc signal access circuit to receive the signal of the motor code disc and convert it into a TTL level signal to connect to the FPGA. The DSP reads the code disc information cached in the FPGA through the EMIF bus at regular intervals according to the clock signal in the clock circuit. And process the data, the data processed by the DSP is sent to the FPGA, and the signal received by the FPGA is sent back to the host computer through the RS422 communication interface.

The present invention utilizes DSP and serial ports to enrich the FPGA to communicate with the outside, and the two communicate through the EMIF bus of the DSP and jointly form the core processor of the motion controller. The RS422 communication interface transmits the upper computer command to the core processor, and the core processes The command signal of the device is passed through the DA conversion module to obtain an analog voltage, which is used to control the motor; the motor code disc signal is connected to the circuit to transmit the motor code disc information to the processor, which is processed by the DSP and sends out a control signal. At the same time, the FPGA and the motor The control terminal drives the interface communication to form a control loop. As the lower computer, the motion controller receives the position command information of the upper computer at high speed through the RS422 communication interface, realizing the real-time communication function of the motion controller, which is more than twice as fast as the real-time communication efficiency of the existing motion controller. It can be used in motor control systems.

Description of drawings

Fig. 1 is the principle schematic diagram of the real-time motion controller of the servo system based on DSP and FPGA described in specific embodiment one,

Fig. 2 is a schematic diagram of the principle of the DA conversion module described in the second specific embodiment,

FIG. 3 is a schematic diagram of the principle of the clock circuit described in Embodiment 3,

FIG. 4 is a schematic diagram of the principle of the 4-way analog switch described in Embodiment 4,

Fig. 5 is a schematic diagram of the principle of the code wheel signal access circuit described in the fifth embodiment,

FIG. 6 is a schematic diagram of the principle of the memory space configuration module described in Embodiment 6,

7 is a schematic diagram of the principle of the RS422 communication interface described in Embodiment 7,

FIG. 8 is a schematic diagram of the principles of the motor control terminal drive interface described in Embodiment 8. FIG.

Detailed ways

Specific embodiment one: with reference to Fig. 1 concrete description present embodiment, the servo system real-time motion controller based on DSP and FPGA described in this embodiment, it comprises FPGA7, DSP8, motor 9, clock circuit 1, DA conversion module 2, Code disc signal access circuit 3, memory space configuration module 4, RS422 communication interface 5 and motor control terminal drive interface 6,

The data signal input or output end of described RS422 communication interface 5 is connected to the data signal output or input end of FPGA7, and the clock signal output end of clock circuit 1 is connected to the clock signal input end of FPGA7 and the clock signal input end of DSP8 simultaneously, and DSP8 passes EMIF The data bus and the memory space configuration module 4 perform data interaction, the memory space configuration signal input or output of the memory space configuration module 4 is connected to the memory space configuration signal output or input of the FPGA7, and the DA conversion module 2, DSP8 and FPGA7 pass the EMIF data bus For data interaction, the digital signal output terminal of FPGA7 is connected to the digital signal input terminal of DA conversion module 2, the analog signal output terminal of DA conversion module 2 is connected to the analog signal input terminal of motor 9, and the code disc signal is connected to the motor code disc of circuit 3 The signal output terminal is connected to the motor encoder signal input terminal of FPGA7, and the drive signal input or output terminal of FPGA7 is connected to the drive signal output or input terminal of the motor control terminal drive interface 6.

Specific embodiment two: this embodiment is described in detail with reference to Fig. 2, the difference between this embodiment and the servo system real-time motion controller based on DSP and FPGA described in specific embodiment one is that DA conversion module 2 includes 4-way DA conversion Chip 2-1, 4-way DA secondary output buffer area 2-2, 4-way analog switch 2-3 and 4-way motor control voltage 2-4,

The 4-way DA conversion chip 2-1, DSP8 and FPGA7 perform data interaction through the EMIF data bus, and the digital signal output end of the FPGA7 is connected to the digital signal input end of the 4-way DA conversion chip 2-1 and the 4-way analog switch 2-1 at the same time. The digital signal input terminal of 3, the cache signal output terminal of the 4-way DA conversion chip 2-1 is connected to the buffer signal input terminal of the 4-way DA secondary output buffer area 2-2, and the buffer signal input end of the 4-way DA secondary output buffer area 2-2 The analog signal output end is connected to the analog signal input end of the 4-way analog switch 2-3, the control signal output end of the 4-way analog switch 2-3 is connected to the control signal input end of the 4-way motor control voltage 2-4, and the 4-way motor control voltage The control signal output terminal of 2-4 is connected with the control signal input terminal of the motor.

In this embodiment, the 4-way DA conversion chip 2-1 and the 4-way DA secondary output buffer area 2-2 are on the same chip, and are also on the chip U10 whose model is ADG5236BRUZ.

In this embodiment, the 4-way DA conversion chip is implemented by a 4-way 16-bit DA chip of the model AD669BR, and its output signal is used as the control output signal of the motor. The chip has a 4-way DA secondary output buffer, and the output range is negative 10V to positive 10V is used to control the motor. Its data bus is mounted on the EMIF data bus, and the control bus is controlled by FPGA; at the same time, in order to prevent the DA from drifting during startup and affect the motor, 4 Road analog switch ADG5236BRUZ selects the output of the final output voltage.

Specific embodiment three, with reference to Fig. 3 specifically illustrate this embodiment, the difference between this embodiment and the servo system real-time motion controller based on DSP and FPGA described in specific embodiment one is that described clock circuit 1 adopts the model as SN74HC125D Realized by the bus buffer gate chip U1, the circuit includes: capacitor C1, capacitor C2, capacitor C3, resistor R1, resistor R2 and active crystal oscillator OS1,

The No. 2 pin of the bus buffer gate chip U1 whose model is SN74HC125D is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the No. 3 pin of the active crystal oscillator OS1 and one end of the resistor R2 at the same time, and the other end of the resistor R2 is connected to The 5th pin of the bus buffer gate chip U1 whose model is SN74HC125D, and the 4th pin of the active crystal oscillator OS1 are simultaneously connected to one end of the capacitor C2, one end of the capacitor C1 and the positive pole of the 3.3V power supply +3.3V, and the active crystal oscillator OS1 Pin No. 2 is connected to capacitor C2, capacitor C1 and the power ground of the 3.3V power supply. Pin No. 14 of the bus buffer gate chip U1 of model SN74HC125D is connected to one end of capacitor C3 and the positive pole of the 3.3V power supply +3.3V at the same time. , the other end of the capacitor C3 is connected to the power ground of the 3.3V power supply, the No. 1 pin of the bus buffer gate chip of the model SN74HC125D, the No. 4 pin of the bus buffer gate chip U1 of the model SN74HC125D, and the bus bus of the model SN74HC125D The 10th pin of the buffer gate chip U1 and the 13th pin of the bus buffer gate chip of the model SN74HC125D, the 7th pin of the bus buffer gate chip U1 of the model SN74HC125D is connected to the power ground of the 3.3V power supply, and the model is SN74HC125D The No. 3 pin of the bus buffer gate chip U1 is used as the clock signal output end of the clock circuit 1.

In this embodiment, the clock circuit generates a 25MHz clock signal through the active crystal oscillator OS1, and is connected to the DSP and the FPGA through the bus buffer gate. The DSP and the FPGA determine the clock frequency to be used through their respective PLL modules, and the DSP controls the clock through the PLL module. Frequency multiplication, after frequency multiplication, the DSP core clock is 200MHz, the DSP peripheral clock is 50MHz, and the DSP external memory interface bus EMIF clock is 12.5MHz. In the FPGA, the clock is not multiplied, and the active crystal oscillator is directly used. Clock 25MHz.

Specific embodiment four, this embodiment is specifically described with reference to Fig. 4, the difference between this embodiment and the servo system real-time motion controller based on DSP and FPGA described in specific embodiment two is that 4 road analog switches 2-3 adopt model It is implemented for the chip U10 of ADG5236BRUZ, the No. 2 pin of the chip U10 of the model ADG5236BRUZ is connected to the power ground of the +15V power supply, and the No. 10 pin of the chip U10 of the model ADG5236BRUZ is connected to the power ground of the +15V power supply. The 13th pin of the chip U10 whose model is ADG5236BRUZ is connected to the positive pole +15V of the 15V power supply, and the 5th pin of the chip U10 whose model is ADG5236BRUZ is connected to the negative pole of the 15V power supply The pin is connected to the power ground of the -15V power supply. The No. 1 and No. 9 pins of the chip U10 of the model ADG5236BRUZ are used as the digital signal input terminals of the 4-way analog switch 2-3, and the No. 4 of the chip U10 of the model ADG5236BRUZ Both pin and pin 12 are used as the analog signal input terminals of the 4-way analog switch 2-3, and pin 3 and pin 11 of the chip U10 whose model is ADG5236BRUZ are both used as the control signals of the 4-way analog switch 2-3 output.

In this embodiment, the 4-way analog switch 2-3ADG5236BRUZ is controlled by the control signals IN1 and IN2 to control the currently selected output, B=ON when IN1=0, A=ON when IN1=1, the IN signal is controlled by FPGA, and the power-on The default is high-impedance state 1.

Specific embodiment five, with reference to Fig. 5, specifically illustrate this embodiment, the difference between this embodiment and the servo system real-time motion controller based on DSP and FPGA described in specific embodiment one is that the code disc signal access circuit 3 adopts the model Implemented for the differential conversion chip U8 of AM26LS32AC, the circuit includes: capacitor C22, capacitor C23 and capacitor C24,

The No. 3 pin of the differential conversion chip U8 whose model is AM26LS32AC is connected to one end of the capacitor C22, the other end of the capacitor C22 is connected to the power ground of the +5V power supply, and the No. 5 pin of the differential conversion chip U8 whose model is AM26LS32AC is connected to the capacitor One end of C23, the other end of capacitor C23 is connected to the power ground of +5V power supply, the 11th pin of the differential conversion chip U8 of model AM26LS32AC is connected to one end of capacitor C24, and the other end of capacitor C24 is connected to the power ground of +5V power supply , the 4th pin of the differential conversion chip U8 of the model AM26LS32AC is connected to the positive pole +5V of the 5V power supply, the 12th pin of the differential conversion chip U8 of the model AM26LS32AC is connected to the power ground of the +5V power supply, and the differential conversion chip of the model is AM26LS32AC The No. 16 pin of the conversion chip U8 is connected to the positive pole +5V of the 5V power supply, the No. 8 pin of the differential conversion chip U8 of the model AM26LS32AC is connected to the power ground of the +5V power supply, and the No. 13 of the differential conversion chip U8 of the model AM26LS32AC The pin is connected to the output end of the code wheel signal of the circuit 3 as the code wheel signal.

In this embodiment, the code disc signal access circuit 3 uses 4 differential conversion chips AM26LS32AC to convert the differential signals of 12 code discs of 4 motors into TTL level signals, and the two differential signals of each code disc are respectively connected to The A and B ports of the differential conversion chip U8, model AM26LS32AC, and the output terminal Y are connected to the FPGA, and the 10-bit signal output by the motor code disc is converted into a 12-bit code disc signal by 4 times in the FPGA for output.

Specific embodiment six, with reference to Fig. 6 specifically illustrate this embodiment, the difference between this embodiment and the servo system real-time motion controller based on DSP and FPGA described in specific embodiment one is that memory space configuration module 4 includes SDRAM4-1 , NANDFLASH4-3 and NORFLASH4-2, the SDRAM4-1, NANDFLASH4-2 and NORFLASH4-3 all perform data interaction with DSP8 through the EMIF data bus, and the memory space of NANDFLASH4-3 configures the signal input or output terminal and the memory space of FPGA7 Configure the signal output or input to be connected.

Memory space configuration module 4 comprises SDRAM, NANDFLASH and NORFLASH in the present embodiment, in addition FPGA is also used as the EMIF external memory of DSP, and SDRAM, NANDFLASH, NORFLASH and FPGA all link to each other with DSP by EMIF bus, the EMIF memory space address of all DSPs starts with DSP is used as the reference design, and capacitors are used to delay DSP startup so that FPGA is configured before DSP. FPGA distributes signals to SDRAM, NANDFLASH and NORFLASH, and all EMIF external space chip selection signals are decoded by FPGA. The system memory space allocation is shown in Table 1.

Table 1 System memory space allocation table

memory class space allocation address allocation memory size SDRAM0 CE0 0x80000000 8Mbytes (16 bits wide) NORFLASH CE1 0x90000000 1Mbytes (8 bits wide) SDRAM1 CE2 0xA0000000 8Mbytes (16 bits wide) FPGA CE3 0xB0000000 32-bit wide asynchronous interface

The specific embodiment seven, with reference to Fig. 7 specifically illustrate this embodiment, the difference between this embodiment and the servo system real-time motion controller based on DSP and FPGA described in the specific embodiment one is that the RS422 communication interface 5 adopts a model that is MAX488ESA Realized by interface chips U422_1 and U422_2, the circuit includes capacitor C422_1, capacitor C422_2, resistor R422_1, resistor R422_2, resistor R422_3, resistor R422_4 and interface J422,

The No. 4 pin of the interface chip U422_1 whose model is MAX488ESA is connected to the power ground of the +5V power supply, and the No. 1 pin of the interface chip U422_1 whose model is MAX488ESA is connected to one end of the capacitor C422_1 and the positive pole +5V of the 5V power supply at the same time. The other end of the capacitor C422_1 is connected to the power ground of the +5V power supply, the No. 8 pin of the interface chip U422_1 of the model MAX488ESA is connected to one end of the resistor R422_1, and the other end of the resistor R422_1 is connected to the No. 7 pin of the interface chip U422_1 of the model MAX488ESA , the No. 6 pin of the interface chip U422_1 whose model is MAX488ESA is connected to one end of the resistor R422_2, the other end of the resistor R422_2 is connected to the No. 5 pin of the interface chip U422_1 whose model is MAX488ESA, and the No. 8 pin of the interface chip U422_1 whose model is MAX488ESA Connect to pin 1 of interface J422, connect pin 7 of interface chip U422_1 of model MAX488ESA to pin 6 of interface J422, connect pin 6 of interface chip U422_1 of model MAX488ESA to pin 2 of interface J422 , the 5th pin of the interface chip U422_1 of the model MAX488ESA is connected to the 7th pin of the interface J422,

The No. 4 pin of the interface chip U422_2 whose model is MAX488ESA is connected to the power ground of the +5V power supply, and the No. 1 pin of the interface chip U422_2 whose model is MAX488ESA is connected to one end of the capacitor C422_2 and the positive pole +5V of the 5V power supply at the same time. The other end of the capacitor C422_2 is connected to the power ground of the +5V power supply, the No. 8 pin of the interface chip U422_2 of the model MAX488ESA is connected to one end of the resistor R422_3, and the other end of the resistor R422_3 is connected to the No. 7 pin of the interface chip U422_2 of the model MAX488ESA , the No. 6 pin of the interface chip U422_2 of the model MAX488ESA is connected to one end of the resistor R422_4, the other end of the resistor R422_4 is connected to the No. 5 pin of the interface chip U422_2 of the model MAX488ESA, and the No. 8 pin of the interface chip U422_2 of the model MAX488ESA Connect to pin 8 of the interface J422, connect pin 7 of the interface chip U422_2 of model MAX488ESA to pin 4 of the interface J422, connect pin 6 of the interface chip U422_2 of the model MAX488ESA to pin 9 of the interface J422 , the No. 5 pin of the interface chip U422_2 of the model MAX488ESA is connected to the No. 5 pin of the interface J422, and the No. 3 pin of the interface J422 is connected to the power ground of the +5V power supply.

The No. 2 and No. 3 pins of the interface chip U422_1 whose model is MAX488ESA and the No. 2 pins and No. 3 pins of the interface chip U422_2 whose model is MAX488ESA are both used as the data signal input or output ends of the RS422 communication interface 5 .

In this embodiment, the RS422 communication interface 5 realizes the serial port communication through the interface chip MAX488ESA. In the actual design, two RS422 interfaces are designed, only one of which is applied to the system, and the other is used as a backup. When it needs to be used, it is programmed in FPGA and DSP. Figure 7 also shows the connection relationship between the two interface chips and the hardware interface, so that the real-time communication between the upper computer and the processor can be realized.

Embodiment 8. This embodiment is specifically described with reference to FIG. 8 . The difference between this embodiment and the real-time motion controller of the servo system based on DSP and FPGA described in Embodiment 1 is that the motor control terminal drive interface 6 includes a resistor R_DA11 , resistor R_DA12, No. 1 relay KDA1 and No. 2 relay KDA2,

The positive pole +24V of the 24V power supply is connected to one end of the resistor R_DA11, the other end of the resistor R_DA11 is connected to one end of the resistor R_DA12, and the other end of the resistor R_DA12 is connected to the power ground of the +24V power supply,

The No. 1 pin of the No. 1 relay KDA1 is connected to the power ground of the +24V power supply, the No. 4 pin of the No. 1 relay KDA1 is connected to the power ground of the +24V power supply, and the No. 1 pin of the No. 2 relay KDA2 is connected to the +24V power supply The power ground of the second relay KDA2, the No. 4 pin of the second relay KDA2 is connected to the power ground of the +24V power supply, one end of the resistor R_DA12, the No. 2 pin of the No. 1 relay KDA1 and the No. 2 pin of the No. The three drive signal output or input terminals of the terminal drive interface 6 .

In this embodiment, the motor control terminal drive interface realizes the drive of the motor control terminal through a relay. Each motor has three control terminals, two of which are used to output signals to the motor, and are respectively connected to the CONT1 and CONT2 control terminals of the motor. On the terminal, the specific functions of these two terminals can be configured through the configuration software that comes with Fuji, and the other terminal is used to receive the output signal of the motor, connected to the OUT1 of the motor, and can also be configured through the configuration software of the motor; The CONT1 and CONT2 signals of the four-way motor are respectively driven by the relay ALQ305. When the relay is turned on, CONT1 and CONT2 are connected to the ground. The control circuit forms a loop, so that the control signal is valid; the OUT1 of the motor is a 24V output signal. This enables the FPGA to read this signal, which is realized in the form of resistor division.

Specific embodiment nine, adopt the control method that the servo system real-time motion controller based on DSP and FPGA described in specific embodiment one realizes, the method may further comprise the steps:

Step 1. The upper computer sends instructions to FPGA7 or FPGA7 to receive the acquisition signal of the motor control terminal drive interface through the RS422 communication interface; and choose one to perform step 2 or step 3;

Step 2, FPGA7 transmits the received instruction to DSP8 through the external memory interface EMIF data bus of DSP8, and processes the instruction by DSP8 and sends the processing result to memory space configuration module 4 through EMIF data bus, meanwhile, FPGA7 and memory space configuration Module 4 performs data communication; DA conversion module 2 receives the digital signal of DSP8 through the EMIF data bus and performs digital-to-analog conversion to obtain a voltage analog signal, so as to control the motor and perform step 4;

Step 3, the DA conversion module 2 performs digital-to-analog conversion on the drive signal received by the FPGA 7 from the drive interface 6 of the motor control terminal, and then controls the motor, and performs step 4;

Step 4: Use code disc signal access circuit 3 to receive the signal of the motor code disc and then convert it into a TTL level signal and connect it to FPGA7. DSP8 reads the code cached in FPGA through the EMIF bus at regular intervals according to the clock signal in clock circuit 1. Disk information and data processing, the data processed by DSP8 is sent to FPGA7, and the signal received by FPGA7 is sent back to the host computer through RS422 communication interface 5.

Claims (9)

1. The servo system real-time motion controller based on DSP and FPGA is characterized in that it includes FPGA (7), DSP (8), motor (9), clock circuit (1), DA conversion module (2), code disc Signal access circuit (3), memory space configuration module (4), RS422 communication interface (5) and motor control terminal drive interface (6), The data signal input or output end of described RS422 communication interface (5) connects the data signal output or input end of FPGA (7), and the clock signal output end of clock circuit (1) connects the clock signal input end of FPGA (7) and The clock signal input end of DSP (8), DSP (8) carries out data interaction with memory space configuration module (4) through EMIF data bus, the memory space configuration signal input or output end of memory space configuration module (4) connects FPGA (7 ) memory space to configure the signal output or input end, the DA conversion module (2), DSP (8) and FPGA (7) perform data interaction through the EMIF data bus, and the digital signal output end of FPGA (7) is connected to the DA conversion module (2 ), the analog signal output end of the DA conversion module (2) is connected to the analog signal input end of the motor (9), and the motor code disc signal output end of the code disc signal access circuit (3) is connected to the FPGA (7) The signal input end of the motor code disc, the drive signal input or output end of the FPGA (7) is connected to the drive signal output or input end of the motor control terminal drive interface (6). 2. the servo system real-time motion controller based on DSP and FPGA according to claim 1, is characterized in that, DA conversion module (2) comprises 4 road DA conversion chips (2-1), 4 road DA secondary output buffers zone (2-2), 4-way analog switch (2-3) and 4-way motor control voltage (2-4), The 4-way DA conversion chip (2-1), DSP (8) and FPGA (7) perform data interaction through the EMIF data bus, and the digital signal output end of the FPGA (7) is connected to the 4-way DA conversion chip (2-1) at the same time. ) digital signal input terminal and the digital signal input terminal of the 4-way analog switch (2-3), and the buffer signal output terminal of the 4-way DA conversion chip (2-1) is connected to the 4-way DA secondary output buffer area (2-2 ), the analog signal output end of the 4-way DA secondary output buffer area (2-2) is connected to the analog signal input end of the 4-way analog switch (2-3), and the 4-way analog switch (2-3) The control signal output terminals of the 4 motor control voltages (2-4) are connected to the control signal input terminals of the 4 motor control voltages (2-4), and the control signal output terminals of the 4 motor control voltages (2-4) are connected to the control signal input terminals of the motor. 3. the servo system real-time motion controller based on DSP and FPGA according to claim 1, is characterized in that, described clock circuit (1) adopts the bus buffer gate chip (U1) that model is SN74HC125D to realize, and this circuit comprises : capacitor C1, capacitor C2, capacitor C3, resistor R1, resistor R2 and active crystal oscillator OS1, The No. 2 pin of the bus buffer gate chip (U1) whose model is SN74HC125D is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the No. 3 pin of the active crystal oscillator OS1 and one end of the resistor R2 at the same time, and the other end of the resistor R2 One end is connected to pin 5 of the bus buffer gate chip (U1) of model SN74HC125D, pin 4 of active crystal oscillator OS1 is connected to one end of capacitor C2, one end of capacitor C1 and the positive pole of 3.3V power supply +3.3V at the same time. The No. 2 pin of the source crystal oscillator OS1 is connected to the power ground of the capacitor C2, the capacitor C1 and the 3.3V power supply at the same time, and the No. 14 pin of the bus buffer gate chip (U1) whose model is SN74HC125D is connected to one end of the capacitor C3 and the 3.3V power supply at the same time. The positive pole of the power supply is +3.3V, and the other end of the capacitor C3 is connected to the power ground of the 3.3V power supply, the No. 1 pin of the bus buffer gate chip of the model SN74HC125D, and the No. 4 pin of the bus buffer gate chip (U1) of the model SN74HC125D Pin, No. 10 pin of the bus buffer gate chip (U1) whose model is SN74HC125D and No. 13 pin of the bus buffer gate chip (U1) whose model is SN74HC125D, and No. 7 pin of the bus buffer gate chip (U1) whose model is SN74HC125D Connect the power ground of the 3.3V power supply, and the No. 3 pin of the bus buffer gate chip (U1) whose model is SN74HC125D is used as the clock signal output end of the clock circuit (1). 4. the servo system real-time motion controller based on DSP and FPGA according to claim 2, is characterized in that, 4 road analog switches 2-3 adopt the chip (U10) that model is ADG5236BRUZ to realize, and described model is the chip (U10) of ADG5236BRUZ Pin 2 of the chip (U10) is connected to the power ground of the +15V power supply, pin 10 of the chip (U10) of the model ADG5236BRUZ is connected to the power ground of the +15V power supply, and pin 13 of the chip (U10) of the model ADG5236BRUZ The No. 1 pin is connected to the positive pole of the 15V power supply +15V, the No. 5 pin of the chip (U10) of the model ADG5236BRUZ is connected to the negative pole of the 15V power supply -15V, and the No. 6 pin of the chip (U10) of the model of ADG5236BRUZ is connected to -15V The power ground of the power supply, the No. 1 pin and the No. 9 pin of the chip (U10) whose model is ADG5236BRUZ are used as the digital signal input terminals of the 4-way analog switch (2-3), and the chip (U10) whose model is ADG5236BRUZ Both pin 4 and pin 12 are used as the analog signal input terminals of the 4-way analog switch (2-3), and pin 3 and pin 11 of the chip (U10) whose model is ADG5236BRUZ are both used as the 4-way analog switch (2-3) The control signal output terminal. 5. the servo system real-time motion controller based on DSP and FPGA according to claim 1, is characterized in that, the code disc signal access circuit (3) adopts the difference conversion chip (U8) that model is AM26LS32AC to realize, this circuit Including: capacitor C22, capacitor C23 and capacitor C24, The No. 3 pin of the differential conversion chip (U8) whose model is AM26LS32AC is connected to one end of the capacitor C22, and the other end of the capacitor C22 is connected to the power ground of the +5V power supply. The pin is connected to one end of the capacitor C23, and the other end of the capacitor C23 is connected to the power ground of the +5V power supply. The 11th pin of the differential conversion chip (U8) of the model AM26LS32AC is connected to one end of the capacitor C24, and the other end of the capacitor C24 is connected to the + The power ground of the 5V power supply, the 4th pin of the differential conversion chip (U8) of the model AM26LS32AC is connected to the positive pole of the 5V power supply +5V, and the 12th pin of the differential conversion chip (U8) of the model AM26LS32AC is connected to the +5V power supply The power ground of the power supply, the 16th pin of the differential conversion chip (U8) of the model AM26LS32AC is connected to the positive pole of the 5V power supply +5V, and the 8th pin of the differential conversion chip (U8) of the model AM26LS32AC is connected to the positive pole of the +5V power supply The power ground, the No. 13 pin of the differential conversion chip (U8) whose model is AM26LS32AC is used as the code disc signal output terminal of the code disc signal access circuit (3). 6. the servo system real-time motion controller based on DSP and FPGA according to claim 1, is characterized in that, memory space configuration module (4) comprises SDRAM (4-1), NANDFLASH (4-3) and NORFLASH (4 -2), said SDRAM (4-1), NANDFLASH (4-2) and NORFLASH (4-3) all carry out data interaction with DSP (8) through EMIF data bus, the memory space configuration of NANDFLASH (4-3) The signal input or output end is connected with the memory space configuration signal output or input end of the FPGA (7). 7. the servo system real-time motion controller based on DSP and FPGA according to claim 1, is characterized in that, RS422 communication interface (5) adopts the interface chip U422_1 and U422_2 that model is MAX488ESA to realize, and this circuit comprises electric capacity C422_1, Capacitor C422_2, resistor R422_1, resistor R422_2, resistor R422_3, resistor R422_4 and interface J422, The No. 4 pin of the interface chip U422_1 whose model is MAX488ESA is connected to the power ground of the +5V power supply, and the No. 1 pin of the interface chip U422_1 whose model is MAX488ESA is connected to one end of the capacitor C422_1 and the positive pole +5V of the 5V power supply at the same time. The other end of the capacitor C422_1 is connected to the power ground of the +5V power supply, the No. 8 pin of the interface chip U422_1 of the model MAX488ESA is connected to one end of the resistor R422_1, and the other end of the resistor R422_1 is connected to the No. 7 pin of the interface chip U422_1 of the model MAX488ESA , the No. 6 pin of the interface chip U422_1 whose model is MAX488ESA is connected to one end of the resistor R422_2, the other end of the resistor R422_2 is connected to the No. 5 pin of the interface chip U422_1 whose model is MAX488ESA, and the No. 8 pin of the interface chip U422_1 whose model is MAX488ESA Connect to pin 1 of interface J422, connect pin 7 of interface chip U422_1 of model MAX488ESA to pin 6 of interface J422, connect pin 6 of interface chip U422_1 of model MAX488ESA to pin 2 of interface J422 , the 5th pin of the interface chip U422_1 of the model MAX488ESA is connected to the 7th pin of the interface J422, The No. 4 pin of the interface chip U422_2 whose model is MAX488ESA is connected to the power ground of the +5V power supply, and the No. 1 pin of the interface chip U422_2 whose model is MAX488ESA is connected to one end of the capacitor C422_2 and the positive pole +5V of the 5V power supply at the same time. The other end of the capacitor C422_2 is connected to the power ground of the +5V power supply, the No. 8 pin of the interface chip U422_2 of the model MAX488ESA is connected to one end of the resistor R422_3, and the other end of the resistor R422_3 is connected to the No. 7 pin of the interface chip U422_2 of the model MAX488ESA , the No. 6 pin of the interface chip U422_2 of the model MAX488ESA is connected to one end of the resistor R422_4, the other end of the resistor R422_4 is connected to the No. 5 pin of the interface chip U422_2 of the model MAX488ESA, and the No. 8 pin of the interface chip U422_2 of the model MAX488ESA Connect to pin 8 of interface J422, connect pin 7 of interface chip U422_2 of model MAX488ESA to pin 4 of interface J422, connect pin 6 of interface chip U422_2 of model MAX488ESA to pin 9 of interface J422 , the No. 5 pin of the interface chip U422_2 of the model MAX488ESA is connected to the No. 5 pin of the interface J422, and the No. 3 pin of the interface J422 is connected to the power ground of the +5V power supply. The No. 2 and No. 3 pins of the interface chip U422_1 whose model is MAX488ESA and the No. 2 pins and No. 3 pins of the interface chip U422_2 whose model is MAX488ESA are used as the data signal input or output terminals of the RS422 communication interface (5) . 8. the servo system real-time motion controller based on DSP and FPGA according to claim 1, is characterized in that, motor control terminal drive interface (6) comprises resistance R_DA11, resistance R_DA12, No. 1 relay (KDA1) and No. 2 relay (KDA2), The positive pole +24V of the 24V power supply is connected to one end of the resistor R_DA11, the other end of the resistor R_DA11 is connected to one end of the resistor R_DA12, and the other end of the resistor R_DA12 is connected to the power ground of the +24V power supply, Pin 1 of the No. 1 relay (KDA1) is connected to the power ground of the +24V power supply, No. 4 pin of the No. 1 relay (KDA1) is connected to the power ground of the +24V power supply, and No. 1 pin of the No. 2 relay (KDA2) is The pin is connected to the power ground of the +24V power supply, the No. 4 pin of the second relay (KDA2) is connected to the power ground of the +24V power supply, one end of the resistor R_DA12, the No. 2 pin of the first relay (KDA1) and the No. The No. 2 pin of KDA1 is used as the drive signal output or input end of the motor control terminal drive interface (6). 9. adopt the control method that the servo system real-time motion controller based on DSP and FPGA according to claim 1 realizes, it is characterized in that, the method comprises the following steps: Step 1, the upper computer sends instructions to FPGA (7) or FPGA (7) through the RS422 communication interface to receive the acquisition signal of the motor control terminal drive interface; and choose one to perform step 2 or step 3; Step 2: FPGA (7) transmits the received instruction to DSP (8) through the external memory interface EMIF data bus of DSP (8), and the DSP (8) processes the instruction and sends the processing result to the memory through the EMIF data bus The space configuration module (4), at the same time, the FPGA (7) performs data communication with the memory space configuration module (4); the DA conversion module (2) receives the digital signal of the DSP (8) through the EMIF data bus and performs digital-to-analog conversion to obtain a voltage analog signal to control the motor, go to step 4; Step 3, the DA conversion module (2) performs digital-to-analog conversion on the drive signal received by the FPGA (7) from the motor control terminal drive interface (6), and then controls the motor, and performs step 4; Step 4: Use the code disc signal to access the circuit (3) After receiving the signal of the motor code disc, convert it into a TTL level signal and insert it into the FPGA (7), and the DSP (8) is timed according to the clock signal in the clock circuit (1) Read the code disk information cached in the FPGA (7) through the EMIF bus and process the data, the data processed by the DSP (8) is passed to the FPGA (7), and the signal received by the FPGA (7) is passed through the RS422 communication interface (5 ) back to the host computer.

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