CN103888269B - Programmable network delayer realizing method - Google Patents
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Abstract
The invention discloses a programmable network delayer realizing method. The method comprises the steps of establishing a hardware circuit comprising a two-path Ethernet physical layer, a multiplexer, a dual-clock FIFO and an MCU, connecting the data output of an Ethernet physical interface layer PHY on the receiving side into a multi-tap shifting register, obtaining a digital delay chain by means of the multi-tap shifting register, connecting the output of the multi-tap shifting register into the dual-clock FIFO through the multiplexer, conducting clock-domain-crossing conversion on data on the receiving side and data on the sending side by means of the dual-clock FIFO, inputting the data on the sending side into the Ethernet physical interface layer to be connected to the output of the dual-clock FIFO, and finally conducting network delay simulation on a symmetrical link or an asymmetrical link after the specific beat of the shifting register is selected through the MCU. According to the method, a system is transparent to a networking protocol, only a small number of hardware resources are occupied, delay simulation is realized through pure hardware, delay is fixed and undithered, step pitch adjustment is quite accurate, and the application prospect is good.
Description
Technical field
The present invention relates to a kind of implementation method of programmable networks chronotron, belong to Ethernet communication technology field.
Background technology
Due to the popularity of Ethernet application and the advance of technology, also there is in commercial Application conventional on-site bus
Incomparable superiority, progressively replacing traditional field bus technique so as to become current Industry Control first-selection net
Network.But the time synchronization protocol of various networks needs the time delay of actual physical link is measured comprehensively.Further, since
The requirement of real-time of Industry Control, needs time delay is measured, including the net of remote measurement website and high time delay
Network link, and such network measurement platform will be set up and put into larger, and when measuring, need the personnel of remote station to coordinate work
Make, difficulty is larger.By developing network delay simulator, transmission delay and forwarding using hardware circuit simulated implementation network prolong
When, just can set up a more comprehensive network measurement platform in laboratory environment, scheme economical and effective, and in laboratory model
Enclose interior development network measure work also more convenient, by simulating the time-delay characteristics of long-range network in laboratory scope,
For Network optimization, track remodelling, the network planning has important work to the data that the measurement of network and assessment aspect obtain
Journey guiding value, saves the high cost that network environment at the scene is tested.
At present, network delay simulation mainly has following two methods：
（1）Software delay simulation based on operating system, first passes through the trawl performance receiving data bag of operating system, then
According to certain strategy, specific packet is inserted in a forward delay interval queue, when in queue, packet delay then exists
Packet is sent by network-driven；
（2）Software delay simulation based on FPGA, builds mac controller by FPGA, receives packet by scheduler
The data of buffering is being read the MAC of transmission and through sending by read port by the outside SDRAM of write.
The time delay of the network packet that above two scheme is realized to a certain extent sends, but application places are different, fits
With narrow range, there are different defects, specific as follows,（1）It is mainly used in analogue communications protocols packet loss under complex network environment
With the scene such as dynamic deferred, due to based on operating system so leading to the uncertainty of datagram time delay it is impossible to realize high accuracy
Time delay；（2）Although buffered data being come using FPGA and sending data, improve delay precision, due to the doubleclocking adopting
The elements such as FIFO, SDRAM, multiport scheduling make network delay have the larger shake of ratio, are not suitable for for analog physical chain
The transmission time delay on road.
Content of the invention
In order to overcome the shortcomings of prior art presence and defect, the realization side of the programmable networks chronotron that the present invention provides
Method, the Hardware Implementation of half material object based on FPGA, by the time-delay characteristic simulating long-range network in laboratory scope
Property, save the high cost that network environment at the scene is tested, effectively simplify delay measurements and system test, time delay is trembled
Dynamic very little, occupancy hardware resource cost is very little, simply easily realizes, has a good application prospect.
To achieve the above object, the present invention adopts the following technical scheme that realization：
A kind of implementation method of programmable networks chronotron it is characterised in that：Comprise the following steps,
Step（1）, build network delay device hardware configuration, network delay device includes MCU and two set of ethernet physical layer and connects
Mouth, digital delay chain, MUX, the hardware circuit of doubleclocking FIFO, described MUX comprises DLL, passes through
The Bus Interface Unit of MCU controls the output of MUX, and the output of MUX accesses doubleclocking FIFO, using double when
Clock FIFO realizes cross clock domain conversion；
Step（2）, digital delay chain is set between the ethernet physical layer interface of receiving side and MUX, described
Digital delay chain is shifted by multi-tap shift register and realizes, and is made using the RXCLK of the ethernet physical layer interface of receiving side
For shift clock, the input of shift register is connected to the output signal group of the ethernet physical layer interface of receiving side, displacement
Every tap output of depositor all corresponds to one group of input of MUX, and the outfan of MUX is connected to doubleclocking
The data input pin of FIFO；
Step（3）, the input clock of doubleclocking FIFO is connected to the RXCLK of the ethernet physical layer interface of receiving side
End, the data write request of doubleclocking FIFO uses RXDV, the output clock of doubleclocking FIFO is connected to the Ethernet of respective side
The output of the tranmitting data register TXCLK of physical layer interface, doubleclocking FIFO is connected to the number of the ethernet physical layer interface of respective side
According to input, send out as the reading request signal of FIFO and the ethernet physical layer interface of respective side after being used fifo empty signal to negate
Send enable signal TXEN；
Step（4）, by the EBI of MCU, desired delay value is converted into the control word of MUX, selects
The specific taps of shift register, are allowed to output and arrive opposite side ethernet physical layer interface, realize desired delay simulation；
Step（5）, by the EBI of MCU, two MUX control words are arranged to same value, it is right to realize
The link delay simulation claiming；Two MUX control words are arranged to different value, realize asymmetric link delay simulation.
A kind of implementation method of aforesaid programmable networks chronotron it is characterised in that：Described digital delay chain by taking out more
Head shift register displacement is realized, and the bit wide of shift register is the data width of ethernet physical layer interface and 1 control line
Sum, mobile one of each reception clock (RXCLK) of shift register, the series of shift register is by desired delay value
Tdelay, by formula（1）Determine,
Tdelay=N Tclk（1）
Wherein, N is the series of shift register, TclkFor the clock cycle.
A kind of implementation method of aforesaid programmable networks chronotron it is characterised in that：Described shift register taps it
Between interval M, by formula（2）Determine,
M=Ts/Tclk（2）
Wherein, TsSingle tapped delay for digital delay chain（Adjust step pitch）, then an overall length is the shift register quilt of N
It is divided into K level, and K tap will become the input quantity of rear class MUX, by formula（3）Determine,
K=N/M（3）.
A kind of implementation method of aforesaid programmable networks chronotron it is characterised in that：The selection of described MUX
Value sn, according to formula（4）Obtain,
Sn=Tx/Ts（4）
Wherein, TxFor desired delay value, TsSingle tapped delay for digital delay chain（Adjust step pitch）.
The invention has the beneficial effects as follows：The implementation method of programmable networks chronotron of the present invention, by two-way with
Too net physical layer interface connects the full-duplex communication link needing simulation, simulates time delay using multitap shift register,
Delay value is converted into the tap position of shift register and is selected with MUX thus being realized precision net to postpone mould
Intend, the present invention has and simply easily realizes, non-jitter is fixed in time delay, it is very accurate to adjust step pitch, can accurately simulate symmetric links and
The advantages of asymmetric link delay, have the characteristics that,
1) system is transparent to procotol, can be with the delay of exact physical link；
2) take hardware resource cost very little, simply easily realize；
3) time delay simulation is realized by pure hardware, and non-jitter is fixed in time delay, adjusts step pitch very accurate；
4) symmetric links and asymmetric link delay can accurately be simulated；
5.) delay jitter is very little, only depend on PHY shake (<10ns).
Brief description
Fig. 1 is the hardware block diagram of the implementation method structure of the programmable networks chronotron of the present invention.
Fig. 2 is multi-tap shift register and the multiplexer connection diagram of the present invention.
Fig. 3 is the doubleclocking FIFO of the present invention and the connection diagram of networked physics layer.
Specific embodiment
Below in conjunction with Figure of description, the invention will be further described.Following examples are only used for clearly
Technical scheme is described, and can not be limited the scope of the invention with this.
The implementation method of the programmable networks chronotron of the present invention, by build include two-way ethernet physical layer (PHY),
MUX, the hardware circuit of doubleclocking FIFO and MCU, connect the data output of receiving side Ethernet physical interface layer PHY
Enter shift register, the output of shift register through MUX and is accessed doubleclocking FIFO, realized using doubleclocking FIFO
Receive and dispatch the cross clock domain conversion of two side datas, sending side data input Ethernet physical interface layer PHY connects the defeated of doubleclocking FIFO
Go out, the particular beat selecting shift register finally by MCU, realize the network delay mould of symmetric links or asymmetric link
Intend, specifically include following steps,
Step（1）, build network delay device hardware configuration, network delay device includes MCU and two set of ethernet physical layer and connects
Mouth, digital delay chain, MUX, the hardware circuit of doubleclocking FIFO, described MUX comprises DLL, passes through
The Bus Interface Unit of MCU controls the output of MUX, and the output of MUX accesses doubleclocking FIFO, using double when
Clock FIFO realizes cross clock domain conversion, as shown in figure 1, building network delay device hardware configuration,
1）Hardware configuration, the too net physical layer interface based on MII interface（PHY）, the PHY of the left and right sides simulates entirely double respectively
The transmitting-receiving of work link, the data carrying out automatic network is latched into time delay simulator in the rising edge of RX_CLK, through the data of time delay
It is sent in the rising edge of TX_CLK and answer the PHY of side and be further transmitted to physical network；
2）Digital delay chain, digital delay chain leans on multitap shift register, as shown in Fig. 2 illustrating this displacement
The logical structure of depositor, the bit wide of shift register depends on the connected data-bus width of PHY and 1 control line,
It is 5 for MII interface width, and be then 9 for gmii interface, taking MII interface as a example, low 4 companies of input of shift register
Meet receiving data group RXD of PHY, the high-order RXER connecting PHY, the series of shift register is determined by desired delay value, moves
Mobile one of each timeticks of bit register, the delay value T of shift register outputdelay, according to formula（1）For,
Tdelay=N Tclk（1）
Wherein, N is the series of shift register, TclkFor the clock cycle；
Interval M between described shift register taps, according to formula（2）For,
M=Ts/Tclk（2）
Wherein, TsFor single tapped delay of digital delay chain, then overall length is that the shift register of N is divided into K level, and
K tap will become the input quantity of rear class MUX, according to formula（3）For,
K=N/M
（3）；
3）MUX, the present invention selects the particular beat of shift register, multi-path choice using MUX
Device selects a certain tap output of shift register to doubleclocking FIFO according to the setting of MCU.The selection end of MUX is defeated
Enter value sn, by lower formula（4）Determine：
Sn=Tx/Ts（4）
Wherein, TxFor desired delay value, TsSingle tapped delay for digital delay chain., use hardware taking MII interface as a example
Description language VHDL describing the implementation method of MUX is：First K tap output of shift register is pressed from height
Become vector logic X to low sequential combination（Dimension is K × 5）, further according to formula（4）Selective value sn can export PHY's
Signal Y：
Y(5downto0)<=X(sn*5+5downto sn*5) (5)
Then by low four of the signal Y TXD [3..0] receiving and sending side PHY, a high position meets TXER, realizes the choosing of different delayed time
Select, as shown in figure 1, simulating the two-way link from A side to B side with from B side to A side for the data flow, each direction is by independent shifting
Bit register and MUX control, when two MUX Configuration Values are identical, it is possible to achieve symmetric links postpone mould
Intend, the delay simulation of asymmetric link can be realized when two MUX Configuration Values are different.
4）Doubleclocking FIFO, because the clock of arranged on left and right sides PHY is inconsistent, the output of MUX can't be direct
Drive PHY to send data, need to be isolated using doubleclocking FIFO, realize cross clock domain conversion, by IEEE802.3 regulation,
Receiving data is indicated by RXDV, sends data by TXEN control, as shown in figure 1, adopting to the clock of writing of doubleclocking FIFO
RXCLK, and write data and be respectively RXD and RXER, the reading clock of doubleclocking FIFO adopts TXCLK, and the data of doubleclocking FIFO is defeated
Go out to connect the data input of respective side PHY, and key challenge is how to enable using the read request of doubleclocking FIFO and the transmission of PHY
The control mode of TXEN.
Additionally, it further provides that by IEEE802.3, because the greatest length of an ethernet frame is 1518 bytes, maximum occupancy
Network time is：
Tpkt_max=1518 × 8 × TethTethEach bit stealing time (100Mbps corresponds to 10nS) on-network
And for two clocks of doubleclocking FIFO, even if the peak frequency of each clock drifts about as 100ppm, then double
The total drift of clock is 200ppm, for 100Mbps network, in time Tpkt_maxThe maximum timing that endogenous cause of ill clock jitter leads to
Error is：
Δ t=Tpkt_max×ferr%=1518 × 8 × 10 × 200 × 10-6=24.288nS
And the data clock of MII interface is 25Mhz in 100Mbps, cycle 40ns is it is possible to simply be made with RXDV
For the written request signal of doubleclocking FIFO, and use the empty signal of FIFO（Fifo spacing wave）As the reading of FIFO after negating
Request signal, simultaneously using empty signal（Fifo spacing wave）After negating, the transmission as phy enables, as shown in figure 3, right
For gmii interface, use instead and waft and brim with the crystal of slightly good 20ppm and can also meet above-mentioned requirements；
5）MCU, MCU are used for realizing user interface, for arranging the time delay T that user specifiesx, by formula（4）Calculate many
The parameter value of road selector, and write the values into the interface of MUX, to select the specific taps position of shift register
Realize time delay, the MCU of the present invention is very simply it is only necessary to realize a serial console interface user program data input
?；
Step（2）, digital delay chain is set between the ethernet physical layer interface of receiving side and MUX, described
Digital delay chain is shifted by multi-tap shift register and realizes, and is made using the RXCLK of the ethernet physical layer interface of receiving side
For shift clock, the input of shift register is connected to the output signal group of the ethernet physical layer interface of receiving side, displacement
Every tap output of depositor all corresponds to one group of input of MUX, and the outfan of MUX is connected to doubleclocking
The data input pin of FIFO, wherein, digital delay chain is shifted by shift register and realizes；
Step（3）, the input clock of doubleclocking FIFO is connected to the RXCLK of the ethernet physical layer interface of receiving side
End, the data write request of doubleclocking FIFO uses RXDV, the output clock of doubleclocking FIFO is connected to the Ethernet of respective side
The output of the tranmitting data register TXCLK of physical layer interface, doubleclocking FIFO is connected to the number of the ethernet physical layer interface of respective side
According to input, send out as the reading request signal of FIFO and the ethernet physical layer interface of respective side after being used fifo empty signal to negate
Send enable signal TXEN；
Step（4）, by the EBI of MCU, desired delay value is converted into the control word of MUX, selects
The specific taps of shift register, are allowed to output and arrive opposite side ethernet physical layer interface, realize desired delay simulation；
Step（5）, by the EBI of MCU, two MUX control words are arranged to same value, it is right to realize
The link delay simulation claiming；Two MUX control words are arranged to different value, realize asymmetric link delay simulation.
Ultimate principle, principal character and the advantage of the present invention have been shown and described above.The technical staff of the industry should
Understand, the present invention is not restricted to the described embodiments, the simply explanation present invention's described in above-described embodiment and description is former
Reason, without departing from the spirit and scope of the present invention, the present invention also has various changes and modifications, these changes and improvements
Both fall within scope of the claimed invention.Claimed scope is by appending claims and its equivalent circle.
Fixed.
Claims (3)
1. a kind of implementation method of programmable networks chronotron it is characterised in that：Comprise the following steps,
Step (1), builds network delay device hardware configuration, and network delay device includes MCU and two set of ethernet physical layer interface, number
Word time delay chain, MUX, the hardware circuit of doubleclocking FIFO, described MUX comprises DLL, by MCU's
Bus Interface Unit controls the output of MUX, and the output of MUX accesses doubleclocking FIFO, using doubleclocking
FIFO realizes cross clock domain conversion；
Step (2), arranges digital delay chain, described numeral between the ethernet physical layer interface of receiving side and MUX
Time delay chain by multi-tap shift register shift realize, and be used receiving side ethernet physical layer interface RXCLK as shifting
Bit clock, the input of shift register is connected to the output signal group of the ethernet physical layer interface of receiving side, shift LD
Every tap output of device all corresponds to one group of input of MUX, and the outfan of MUX is connected to doubleclocking FIFO's
Data input pin；
Step (3), the input clock of doubleclocking FIFO is connected to the RXCLK end of the ethernet physical layer interface of receiving side, double
The data write request of clock FIFO uses RXDV, the output clock of doubleclocking FIFO is connected to the ethernet physical layer of respective side
The output of the tranmitting data register TXCLK of interface, doubleclocking FIFO is connected to the data input of the ethernet physical layer interface of respective side
End, sends and enables as the reading request signal of FIFO and the ethernet physical layer interface of respective side after being used fifo empty signal to negate
Signal TXEN；
Desired delay value is converted into the control word of MUX by step (4) by the EBI of MCU, selects displacement
The specific taps of depositor, are allowed to output and arrive opposite side ethernet physical layer interface, realize desired delay simulation；
Step (5), by the EBI of MCU, two MUX control words is arranged to same value, realizes symmetrical
Link delay is simulated；Two MUX control words are arranged to different value, realize asymmetric link delay simulation,
Selection end input value sn of described MUX, obtains according to formula (4),
Sn=Tx/Ts(4)
Wherein, TxFor desired delay value, TsSingle tapped delay for digital delay chain.
2. a kind of programmable networks chronotron according to claim 1 implementation method it is characterised in that：Described numeral is prolonged
When chain shifted by multi-tap shift register and realize, the bit wide of shift register be ethernet physical layer interface data width with
1 control line sum, mobile one of each reception clock (RXCLK) of shift register, the series of shift register is by desired
Delay value Tdelay, determined by formula (1),
Tdelay=N Tclk(1)
Wherein, N is the series of shift register, TclkFor the clock cycle.
3. a kind of programmable networks chronotron according to claim 1 and 2 implementation method it is characterised in that：Described shifting
Interval M between bit register tap, is determined by formula (2),
M=Ts/Tclk(2)
Wherein, TsSingle tapped delay (regulation step pitch) for digital delay chain, then overall length is that the shift register of N is divided into K
Level, and K tap will become the input quantity of rear class MUX, be determined by formula (3),
K=N/M (3).
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| CN109143186A (en) * | 2018-08-17 | 2019-01-04 | 电子科技大学 | A kind of remote simulator of wideband-radar signal multiple target and method |
| CN110297790B (en) * | 2019-06-12 | 2023-02-14 | 深圳市三旺通信股份有限公司 | System and method for realizing multi-channel serial data transmission based on Ethernet PHY chip |
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| CN1965282A (en) * | 2004-04-05 | 2007-05-16 | 米克伦技术公司 | Delay line synchronizer apparatus and method |
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