[go: up one dir, main page]

CN103873141B - Optical fiber and digital OTDR detection method and device - Google Patents

Optical fiber and digital OTDR detection method and device Download PDF

Info

Publication number
CN103873141B
CN103873141B CN201210531731.XA CN201210531731A CN103873141B CN 103873141 B CN103873141 B CN 103873141B CN 201210531731 A CN201210531731 A CN 201210531731A CN 103873141 B CN103873141 B CN 103873141B
Authority
CN
China
Prior art keywords
module
configuration
receiving
data
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201210531731.XA
Other languages
Chinese (zh)
Other versions
CN103873141A (en
Inventor
吴旭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanechips Technology Co Ltd
Original Assignee
ZTE Corp
Shenzhen ZTE Microelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ZTE Corp, Shenzhen ZTE Microelectronics Technology Co Ltd filed Critical ZTE Corp
Priority to CN201210531731.XA priority Critical patent/CN103873141B/en
Publication of CN103873141A publication Critical patent/CN103873141A/en
Application granted granted Critical
Publication of CN103873141B publication Critical patent/CN103873141B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Optical Communication System (AREA)

Abstract

本发明涉及一种光纤数字OTDR检测方法及装置,该装置设置在光网主控芯片上,包括接收模块、发送模块、配置模块及内存模块,配置模块为接收模块配置接收控制参数,为发送模块配置发送控制参数;接收模块接收来自外部的光接收及A/D转换模块发送的并行数据并缓存,根据接收控制参数,对并行数据进行采样,并将采样数据保存至内存模块;发送模块根据发送控制参数,从配置模块中获取配置数据进行并串转换、奇偶控制及通路选择,以发送序列发送至外部的光发送模块。本发明以数字模块的方式,在光网络的主控芯片上即可实现OTDR功能,满足了光网络的建设需求,节省了光纤检测装置开发时间及成本,提高了光纤检测装置的灵活度、准确度。

The invention relates to an optical fiber digital OTDR detection method and device. The device is arranged on an optical network main control chip and includes a receiving module, a sending module, a configuration module and a memory module. The configuration module configures receiving control parameters for the receiving module and is a sending module Configure the sending control parameters; the receiving module receives and buffers the parallel data sent by the external optical receiving and A/D conversion modules, samples the parallel data according to the receiving control parameters, and saves the sampled data to the memory module; the sending module sends Control parameters, obtain configuration data from the configuration module to perform parallel-to-serial conversion, parity control and channel selection, and send to the external optical transmission module in a transmission sequence. The present invention can realize the OTDR function on the main control chip of the optical network in the form of a digital module, which meets the construction requirements of the optical network, saves the development time and cost of the optical fiber detection device, and improves the flexibility and accuracy of the optical fiber detection device. Spend.

Description

光纤数字OTDR检测方法及装置Optical fiber digital OTDR detection method and device

技术领域 technical field

本发明涉及光纤通信技术领域,尤其涉及一种光纤数字OTDR检测方法及装置。The invention relates to the technical field of optical fiber communication, in particular to an optical fiber digital OTDR detection method and device.

背景技术 Background technique

目前光网络例如GPON、EPON的光网已大力普及,因此对所铺设的光纤的质量检测则成为一个很重要的问题。At present, optical networks such as GPON and EPON have been greatly popularized, so the quality inspection of laid optical fibers has become a very important issue.

目前很多光纤检测的方法都是在现有设备外部添加OTDR(Optical Time Domain Reflectometer,光时域反射仪)设备。传统OTDR是利用光线在光纤中传输时的瑞利散射和菲涅尔反射所产生的背向散射而制成的精密光电一体化仪表,它被广泛应用于光缆线路的维护、施工之中,可进行光纤长度、光纤的传输衰减、接头衰减和故障定位等的测量。但是,现有的这种OTDR设备比较昂贵,操作起来也不方便,增加运行维护成本。At present, many optical fiber detection methods are to add OTDR (Optical Time Domain Reflectometer, Optical Time Domain Reflectometer) equipment outside the existing equipment. The traditional OTDR is a precision optoelectronic integrated instrument made of Rayleigh scattering and Fresnel reflection when the light is transmitted in the optical fiber. It is widely used in the maintenance and construction of optical cable lines. Measure the fiber length, fiber transmission attenuation, joint attenuation and fault location. However, the existing OTDR equipment is relatively expensive, inconvenient to operate, and increases operation and maintenance costs.

发明内容 Contents of the invention

本发明的主要目的在于提供一种成本低且操作方便的光纤数字OTDR检测方法及装置。The main purpose of the present invention is to provide a low-cost and easy-to-operate optical fiber digital OTDR detection method and device.

为了达到上述目的,本发明提出一种光纤数字OTDR检测装置,设置在光网主控芯片上,包括:接收模块、发送模块、配置模块及内存模块,其中:In order to achieve the above object, the present invention proposes a kind of optical fiber digital OTDR detection device, is arranged on the main control chip of optical network, comprises: receiving module, sending module, configuration module and memory module, wherein:

所述配置模块用于为所述接收模块配置接收控制参数,为所述发送模块配置发送控制参数;The configuration module is used to configure receiving control parameters for the receiving module, and configure sending control parameters for the sending module;

所述接收模块用于接收来自外部的光接收及A/D转换模块发送的并行数据并缓存,根据所述接收控制参数,对所述并行数据进行采样,并将采样数据保存至所述内存模块;The receiving module is used to receive and buffer the parallel data sent by the external light receiving and A/D conversion module, sample the parallel data according to the receiving control parameters, and save the sampled data to the memory module ;

所述发送模块用于根据所述发送控制参数,从配置模块中获取配置数据进行并串转换、奇偶控制及通路选择,以发送序列发送至外部的光发送模块。The sending module is used to obtain configuration data from the configuration module to perform parallel-serial conversion, parity control and channel selection according to the sending control parameters, and send it to an external optical sending module in a sending sequence.

优选地,所述发送模块还用于根据所述发送控制参数选择的内部还回通路,将所述发送序列发送至所述接收模块。Preferably, the sending module is further configured to send the sending sequence to the receiving module according to the internal return path selected by the sending control parameter.

优选地,所述配置模块设有用户访问接口,所述配置模块还用于通过所述用户访问接口接收用户输入信息进行参数配置。Preferably, the configuration module is provided with a user access interface, and the configuration module is further configured to receive user input information through the user access interface for parameter configuration.

优选地,所述接收控制参数至少包括:接收RAM深度、接收延迟点及软复位配置信息;所述发送控制参数至少包括:发送起始点、发送序列内容、发送序列长度、发送序列速率、内外部通路及发送奇偶配置信息。Preferably, the receiving control parameters at least include: receiving RAM depth, receiving delay point, and soft reset configuration information; the sending control parameters include at least: sending start point, sending sequence content, sending sequence length, sending sequence rate, internal and external Channel and send parity configuration information.

优选地,所述接收模块还用于在所述发送模块启动发送时开始计数,在计数值达到接收延迟点配置的数值时打开采样窗口进行数据采样。Preferably, the receiving module is further configured to start counting when the sending module starts sending, and open a sampling window for data sampling when the count value reaches the value configured for the receiving delay point.

优选地,所述接收模块还用于当写RAM地址小于接收RAM深度配置的数值时,向内存模块的接收RAM保存数据;当写RAM地址等于接收RAM深度配置的数值时停止保存数据,并输出保存完成的信号供用户查询。Preferably, the receiving module is also used to save data to the receiving RAM of the memory module when the write RAM address is less than the value of the receiving RAM depth configuration; stop saving data when the writing RAM address is equal to the value of the receiving RAM depth configuration, and output Save the completed signal for user query.

本发明还提出一种光纤数字OTDR检测方法,包括:The present invention also proposes a kind of optical fiber digital OTDR detection method, comprising:

接收来自外部的光接收及A/D转换模块发送的并行数据并缓存,根据配置的接收控制参数,对所述并行数据进行采样,并将采样数据保存至内存模块;receiving and buffering the parallel data sent by the external optical receiving and A/D conversion modules, sampling the parallel data according to the configured receiving control parameters, and saving the sampled data to the memory module;

根据所述配置的发送控制参数,从配置模块中获取配置参数进行并串转换、奇偶控制及通路选择,以发送序列发送至外部的光发送模块。According to the configured transmission control parameters, the configuration parameters are obtained from the configuration module to perform parallel-to-serial conversion, parity control and channel selection, and are sent to the external optical transmission module in a transmission sequence.

优选地,该方法还包括:Preferably, the method also includes:

根据所述发送控制参数选择的内部还回通路,将所述发送序列发送至所述接收模块。Sending the sending sequence to the receiving module according to the internal return path selected by the sending control parameter.

优选地,所述接收来自外部的光接收及A/D转换模块发送的并行数据并缓存的步骤之前还包括:Preferably, before the step of receiving and buffering the parallel data sent by the external light receiving and A/D conversion module, it also includes:

通过所述用户访问接口接收用户输入信息进行参数配置。The parameter configuration is performed by receiving user input information through the user access interface.

优选地,所述接收控制参数至少包括:接收RAM深度、接收延迟点及软复位配置信息;所述发送控制参数至少包括:发送起始点、发送序列内容、发送序列长度、发送序列速率、内外部通路及发送奇偶配置信息。Preferably, the receiving control parameters at least include: receiving RAM depth, receiving delay point, and soft reset configuration information; the sending control parameters include at least: sending start point, sending sequence content, sending sequence length, sending sequence rate, internal and external Channel and send parity configuration information.

优选地,所述对并行数据进行采样的步骤包括:在启动发送数据时开始计数,在计数值达到接收延迟点配置的数值时打开采样窗口进行数据采样。Preferably, the step of sampling the parallel data includes: starting counting when starting to send data, and opening a sampling window for data sampling when the count value reaches the value configured for the receiving delay point.

优选地,所述将采样数据保存至内存模块的步骤包括:Preferably, the step of saving the sampling data to the memory module includes:

当写RAM地址小于接收RAM深度配置的数值时,向内存模块的接收RAM保存数据;当写RAM地址等于接收RAM深度配置的数值时停止保存数据,并输出保存完成的信号供用户查询。When the write RAM address is less than the value of the receiving RAM depth configuration, save the data to the receiving RAM of the memory module; when the writing RAM address is equal to the value of the receiving RAM depth configuration, stop saving the data, and output a save completion signal for the user to query.

本发明提出的一种光纤数字OTDR检测方法及装置,以数字模块的方式,在光网络的主控芯片上即可实现OTDR的功能,无需要外部传统光纤检测装置,不仅操作简便,且满足了日益快速发展的光网络的建设需求;相比现有技术,取得了在数字模块设计方面的进步,达到了灵活多变满足客户定制的效果,节省了光纤检测装置开发的时间及成本,提高了光纤检测装置的灵活度、准确度等。An optical fiber digital OTDR detection method and device proposed by the present invention can realize the function of OTDR on the main control chip of the optical network in the form of a digital module, without the need of an external traditional optical fiber detection device, which is not only easy to operate, but also satisfies The construction needs of the increasingly fast-growing optical network; compared with the existing technology, it has made progress in the design of digital modules, achieved the effect of being flexible and changeable to meet customer customization, saved the time and cost of developing optical fiber detection devices, and improved The flexibility and accuracy of the optical fiber detection device.

附图说明 Description of drawings

图1是本发明光纤数字OTDR检测装置一实施例的结构示意图;Fig. 1 is the structural representation of an embodiment of optical fiber digital OTDR detection device of the present invention;

图2是本发明光纤数字OTDR检测方法一实施例的流程示意图。Fig. 2 is a schematic flowchart of an embodiment of an optical fiber digital OTDR detection method of the present invention.

具体实施方式 detailed description

本发明实施例的解决方案主要思路是:由于现有的光网主控芯片多是ASIC或者FPGA芯片,可根据用户添加额外的数字模块,因此可以考虑在主控芯片上添加数字模块(即本发明所述的光纤数字OTDR检测装置),模拟OTDR的功能。The main idea of the solution in the embodiment of the present invention is: since most of the existing optical network main control chips are ASIC or FPGA chips, additional digital modules can be added according to the user, so it can be considered to add digital modules on the main control chip (that is, this The optical fiber digital OTDR detection device described in the invention) simulates the function of OTDR.

如图1所示,本发明一实施例提出的一种光纤数字OTDR检测装置,设置在光网主控芯片上,包括:接收模块101、发送模块104、配置模块103及内存模块102,其中:As shown in Figure 1, a kind of optical fiber digital OTDR detection device that one embodiment of the present invention proposes is arranged on the main control chip of the optical network, including: receiving module 101, sending module 104, configuration module 103 and memory module 102, wherein:

接收模块101与外部的光接收及A/D转换模块105连接,发送模块104与外部的光发送模块106连接。The receiving module 101 is connected to an external optical receiving and A/D conversion module 105 , and the transmitting module 104 is connected to an external optical transmitting module 106 .

所述配置模块103用于为所述接收模块101配置接收控制参数,为所述发送模块104配置发送控制参数;The configuration module 103 is configured to configure receiving control parameters for the receiving module 101, and configure sending control parameters for the sending module 104;

所述接收模块101用于接收来自外部的光接收及A/D转换模块发送的并行数据并缓存,根据所述接收控制参数,对所述并行数据进行采样,并将采样数据保存至所述内存模块102;The receiving module 101 is used to receive and buffer the parallel data sent by the external light receiving and A/D conversion modules, sample the parallel data according to the receiving control parameters, and save the sampled data to the internal memory module 102;

所述发送模块104用于根据所述发送控制参数,从配置模块103中获取配置数据进行并串转换、奇偶控制及通路选择,以发送序列发送至外部的光发送模块106。The sending module 104 is used to obtain configuration data from the configuration module 103 to perform parallel-to-serial conversion, parity control and channel selection according to the sending control parameters, and send it to the external optical sending module 106 in a sending sequence.

具体地,本实施例光纤数字OTDR检测装置可以以数字模块的设计方式添加在光网络的主控芯片上,本实施例是以硬件描述语言对该数字模块进行设计,具体可以Verilog HDL语言进行设计,该数字模块可灵活分成上述几个小模块,包括发送模块104、接收模块101、配置模块103和内存模块102。Specifically, the optical fiber digital OTDR detection device in this embodiment can be added on the main control chip of the optical network in the design mode of a digital module. In this embodiment, the digital module is designed with a hardware description language, which can be specifically designed in Verilog HDL language , the digital module can be flexibly divided into the above-mentioned several small modules, including a sending module 104 , a receiving module 101 , a configuration module 103 and a memory module 102 .

每个小模块具体设计方法及功能如下:The specific design method and function of each small module are as follows:

配置模块103提供用户访问接口及内部配置寄存器,例如图1所示的CPU接口模块,也可以改为其他接口,以方便用户进行一些参数的配置。The configuration module 103 provides user access interfaces and internal configuration registers, such as the CPU interface module shown in FIG. 1 , and can also be changed to other interfaces to facilitate the configuration of some parameters by the user.

其中CPU接口模块提供与外部芯片进行通信的接口,一般是CPU总线接口。通过该模块,用户可配置一些内部的寄存器,如图1所示的发送起始点配置0、发送序列内容1、发送序列长度配置2、发送序列速率配置3、内外部通路配置4、接收RAM深度配置5、接收延迟点配置6、软复位配置7及发送奇偶配置8。The CPU interface module provides an interface for communicating with external chips, generally a CPU bus interface. Through this module, the user can configure some internal registers, as shown in Figure 1, the sending start point configuration 0, the sending sequence content 1, the sending sequence length configuration 2, the sending sequence rate configuration 3, the internal and external path configuration 4, and the receiving RAM depth Configuration 5, receiving delay point configuration 6, soft reset configuration 7 and sending parity configuration 8.

发送模块104包含发送模块1040、发送模块1041、发送模块1042,每个模块由配置模块103里面的参数独立控制,例如控制光信号发送的长度、内容、速率、起始点等;发送模块1040可用状态机实现,并串转换部分可使用移位寄存器实现;发送模块1041用1个2选1选择器实现;发送模块1042用1个2选1选择器实现,用户通过配置内外部通路配置4可以选择使用外部硬件通路或者内部环回通路。The sending module 104 includes a sending module 1040, a sending module 1041, and a sending module 1042. Each module is independently controlled by parameters in the configuration module 103, such as controlling the length, content, rate, and starting point of optical signal transmission; the available status of the sending module 1040 The parallel-to-serial conversion part can be realized by using a shift register; the sending module 1041 is realized by a 2-to-1 selector; the sending module 1042 is realized by a 2-to-1 selector, and the user can select 4 by configuring internal and external channels Use either an external hardware path or an internal loopback path.

接收模块101可分为接收模块1010、接收模块1011、接收模块1012,每个模块也是由配置模块103里面的参数控制,例如控制采样所接收的光信号的采样长度、采样时间点等。The receiving module 101 can be divided into receiving module 1010, receiving module 1011, and receiving module 1012. Each module is also controlled by parameters in the configuration module 103, such as controlling the sampling length and sampling time point of the received optical signal.

其中,接收模块1010用1个buffer实现,图1所示的接收并行数据0及接收并行数据1的时钟频率数值应该一样,相位可不同;接收模块1011可使用1个计数器实现,当发送模块1040启动发送的时候开始计数,在计数值达到接收延迟点配置6的数值的时候打开采样窗口,允许采样数据保存到接收RAM里面;接收模块1012可使用1个比较器实现,当写RAM地址小于接收RAM深度配置5的时候继续往RAM保存数据;当写RAM地址等于接收RAM深度配置5的时候停止保存数据,并给出一个保存完成的信号write_done,当用户通过CPU接口查询到该信号置1的时候,即可读取接收RAM的数据进行分析。Wherein, the receiving module 1010 is implemented with one buffer, the clock frequency values of receiving parallel data 0 and receiving parallel data 1 shown in FIG. Start counting when sending is started, and open the sampling window when the count value reaches the value of receiving delay point configuration 6, allowing the sampling data to be saved in the receiving RAM; the receiving module 1012 can be implemented using a comparator, when the write RAM address is less than the receiving When the RAM depth configuration is 5, continue to save data in RAM; when the write RAM address is equal to the receiving RAM depth configuration 5, stop saving data, and give a save completion signal write_done, when the user queries the signal through the CPU interface and sets it to 1 Time, you can read the data receiving RAM for analysis.

内存模块102,使用1个或者多个假双口RAM实现,不需要外部的存储芯片,其深度可以根据实际需求设计,例如要保存1024×32bit的数据,则需要设计一个地址宽度为10位、数据宽度为32位的假双口RAM。The memory module 102 is realized by using one or more fake dual-port RAMs, no external memory chips are needed, and its depth can be designed according to actual needs. The data width is a false dual-port RAM of 32 bits.

本实施例通过上述方案,取得了在数字模块设计方面的进步,达到了灵活多变满足客户定制的效果,节省了光纤检测装置开发的时间及成本,提高了光纤检测装置的灵活度、准确度等;而且这种模块化的设计方法,更容易开发及维护。另外,该装置可使用FPGA逻辑芯片设计,能够更快实现光纤检测装置的各种功能。Through the above scheme, this embodiment has made progress in the design of digital modules, achieved the effect of being flexible and changeable to meet customer customization, saved the time and cost of developing the optical fiber detection device, and improved the flexibility and accuracy of the optical fiber detection device etc.; and this modular design method is easier to develop and maintain. In addition, the device can be designed using an FPGA logic chip, which can realize various functions of the optical fiber detection device faster.

如图2所示,本发明较佳实施例提出一种光纤数字OTDR检测方法,依据上述实施例的装置而实施,该方法包括:As shown in Figure 2, the preferred embodiment of the present invention proposes a kind of optical fiber digital OTDR detection method, implements according to the device of above-mentioned embodiment, this method comprises:

步骤S201,接收来自外部的光接收及A/D转换模块发送的并行数据并缓存,根据配置的接收控制参数,对所述并行数据进行采样,并将采样数据保存至内存模块;Step S201, receiving and buffering the parallel data sent by the external light receiving and A/D conversion module, sampling the parallel data according to the configured receiving control parameters, and saving the sampled data to the memory module;

步骤S202,根据所述配置的发送控制参数,从配置模块中获取配置数据进行并串转换、奇偶控制及通路选择,以发送序列发送至外部的光发送模块。Step S202, according to the configured transmission control parameters, obtain configuration data from the configuration module to perform parallel-to-serial conversion, parity control and path selection, and send it to an external optical transmission module in a transmission sequence.

其中,接收控制参数至少包括:接收RAM深度、接收延迟点及软复位配置信息;所述发送控制参数至少包括:发送起始点、发送序列内容、发送序列长度、发送序列速率、内外部通路及发送奇偶配置信息。Among them, the receiving control parameters at least include: receiving RAM depth, receiving delay point and soft reset configuration information; the sending control parameters include at least: sending start point, sending sequence content, sending sequence length, sending sequence rate, internal and external paths and sending Parity configuration information.

具体地,本实施例方法所采用的光纤数字OTDR检测装置可以以数字模块的设计方式添加在光网络的主控芯片上,本实施例是以硬件描述语言对该数字模块进行设计,具体可以Verilog HDL语言进行设计,该数字模块可灵活分成几个小模块,包括发送模块、接收模块、配置模块和内存模块。Specifically, the optical fiber digital OTDR detection device adopted in the method of this embodiment can be added on the main control chip of the optical network in the design mode of a digital module, and this embodiment is designed with a hardware description language for the digital module, specifically Verilog HDL language design, the digital module can be flexibly divided into several small modules, including sending module, receiving module, configuration module and memory module.

每个小模块具体设计方法及功能如下:The specific design method and function of each small module are as follows:

配置模块提供用户访问接口及内部配置寄存器,例如图1所示的CPU接口模块,也可以改为其他接口,以方便用户进行一些参数的配置。The configuration module provides user access interfaces and internal configuration registers. For example, the CPU interface module shown in Figure 1 can also be changed to other interfaces to facilitate the configuration of some parameters by the user.

其中CPU接口模块提供与外部芯片进行通信的接口,一般是CPU总线接口。通过该模块,用户可配置一些内部的寄存器,如图1所示的发送起始点配置0、发送序列内容1、发送序列长度配置2、发送序列速率配置3、内外部通路配置4、接收RAM深度配置5、接收延迟点配置6、软复位配置7及发送奇偶配置8。The CPU interface module provides an interface for communicating with external chips, generally a CPU bus interface. Through this module, the user can configure some internal registers, as shown in Figure 1, the sending start point configuration 0, the sending sequence content 1, the sending sequence length configuration 2, the sending sequence rate configuration 3, the internal and external path configuration 4, and the receiving RAM depth Configuration 5, receiving delay point configuration 6, soft reset configuration 7 and sending parity configuration 8.

发送模块包含发送模块0、发送模块1、发送模块2,每个模块由配置模块里面的参数独立控制,例如控制光信号发送的长度、内容、速率、起始点等;发送模块0可用状态机实现,并串转换部分可使用移位寄存器实现;发送模块1用1个2选1选择器实现;发送模块2用1个2选1选择器实现,用户通过配置内外部通路配置4可以选择使用外部硬件通路或者内部环回通路。The sending module includes sending module 0, sending module 1, and sending module 2. Each module is independently controlled by the parameters in the configuration module, such as controlling the length, content, rate, starting point, etc. of optical signal transmission; sending module 0 can be implemented with a state machine , the parallel-to-serial conversion part can be realized by using a shift register; the sending module 1 is realized by a 2-to-1 selector; the sending module 2 is realized by a 2-to-1 selector, and the user can choose to use the external channel configuration 4 by configuring the internal and external channels. Hardware path or internal loopback path.

接收模块可分为接收模块0、接收模块1、接收模块2,每个模块也是由配置模块里面的参数控制,例如控制采样所接收的光信号的采样长度、采样时间点等。The receiving module can be divided into receiving module 0, receiving module 1, and receiving module 2. Each module is also controlled by parameters in the configuration module, such as controlling the sampling length and sampling time point of the received optical signal.

其中,接收模块0用1个buffer实现,图1所示的接收并行数据0及接收并行数据1的时钟频率数值应该一样,相位可不同;接收模块1可使用1个计数器实现,当发送模块0启动发送的时候开始计数,在计数值达到接收延迟点配置6的数值的时候打开采样窗口,允许采样数据保存到接收RAM里面;接收模块2可使用1个比较器实现,当写RAM地址小于接收RAM深度配置5的时候继续往RAM保存数据;当写RAM地址等于接收RAM深度配置5的时候停止保存数据,并给出一个保存完成的信号write_done,当用户通过CPU接口查询到该信号置1的时候,即可读取接收RAM的数据进行分析。Among them, receiving module 0 is implemented with one buffer. The clock frequency values of receiving parallel data 0 and receiving parallel data 1 shown in Figure 1 should be the same, but the phases can be different; Start counting when sending is started, and open the sampling window when the count value reaches the value of receiving delay point configuration 6, allowing the sampling data to be saved in the receiving RAM; receiving module 2 can be implemented using a comparator, when the write RAM address is less than receiving When the RAM depth configuration is 5, continue to save data in RAM; when the write RAM address is equal to the receiving RAM depth configuration 5, stop saving data, and give a save completion signal write_done, when the user queries the signal through the CPU interface and sets it to 1 Time, you can read the data receiving RAM for analysis.

内存模块,使用1个或者多个假双口RAM实现,不需要外部的存储芯片,其深度可以根据实际需求设计,例如要保存1024×32bit的数据,则需要设计一个地址宽度为10位、数据宽度为32位的假双口RAM。The memory module is realized by using one or more fake dual-port RAMs. It does not require external memory chips. Its depth can be designed according to actual needs. For example, if you want to save 1024×32bit data, you need to design a False dual-port RAM with a width of 32 bits.

本发明实施例光纤数字OTDR检测方法及装置,以数字模块的方式,在光网络的主控芯片上即可实现OTDR的功能,无需要外部传统光纤检测装置,不仅操作简便,而且满足了日益快速发展的光网络的建设需求;相比现有技术,取得了在数字模块设计方面的进步,达到了灵活多变满足客户定制的效果,节省了光纤检测装置开发的时间及成本,提高了光纤检测装置的灵活度、准确度等。The optical fiber digital OTDR detection method and device of the embodiment of the present invention can realize the function of OTDR on the main control chip of the optical network in the form of a digital module, without the need for an external traditional optical fiber detection device, which is not only easy to operate, but also satisfies the increasingly fast The construction needs of the developing optical network; Compared with the existing technology, it has made progress in the design of digital modules, achieved the effect of being flexible and changeable to meet customer customization, saved the time and cost of developing optical fiber detection devices, and improved the quality of optical fiber detection. The flexibility and accuracy of the device, etc.

以上所述仅为本发明的优选实施例,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或流程变换,或直接或间接运用在其它相关的技术领域,均同理包括在本发明的专利保护范围内。The above is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or process transformation made by using the description of the present invention and the contents of the accompanying drawings, or directly or indirectly used in other related technical fields , are all included in the scope of patent protection of the present invention in the same way.

Claims (10)

1. optical fiber and digital OTDR detects a device, is arranged on light net main control chip, it is characterised in that Including: receiver module, sending module, configuration module and memory modules, wherein:
Described configuration module controls parameter, for described sending module for receiving for the configuration of described receiver module Configuration sends and controls parameter;
Described receiver module is for receiving send and line number from outside light-receiving and A/D modular converter According to and cache, control parameter according to described reception, described parallel data sampled, and by hits According to preserving to described memory modules;
Described sending module, for controlling parameter according to described transmission, obtains configuration data from configuration module Carry out parallel-serial conversion, odd even controls and path selects, to send sequence transmission to outside optical transmission module;
Wherein, described receive control parameter at least include: receive the RAM degree of depth, receive postpone point and soft multiple Position configuration information;The described control parameter that sends at least includes: sends starting point, transmission sequence content, send out Send sequence length, send sequence rate, inside and outside path and send odd even configuration information.
Device the most according to claim 1, it is characterised in that described sending module is additionally operable to basis Path is returned in the inside of described transmission selection of control parameter, sends described transmission sequence to described reception mould Block.
Device the most according to claim 1, it is characterised in that described configuration module is provided with user and visits Ask that interface, described configuration module are additionally operable to receive user's input information by described user's access interface and carry out Parameter configuration.
Device the most according to claim 1, it is characterised in that described receiver module is additionally operable in institute State when sending module starts transmission and start counting up, beat when count value reaches and receives the numerical value postponing some configuration Open sampling window and carry out data sampling.
Device the most according to claim 1, it is characterised in that described receiver module is additionally operable to when writing During the numerical value that address ram configures less than the reception RAM degree of depth, preserve to the reception RAM of memory modules Data;Stop preserving data when writing address ram equal to the numerical value receiving the configuration of the RAM degree of depth, and defeated Go out the signal preserved to inquire about for user.
6. an optical fiber and digital OTDR detection method, it is characterised in that including:
Receive the parallel data sent from outside light-receiving and A/D modular converter and cache, according to joining The reception put controls parameter, samples described parallel data, and preserves sampled data to internal memory mould Block;
According to configuration transmission control parameter, from configuration module obtain configuration parameter carry out parallel-serial conversion, Odd even controls and path selects, to send sequence transmission to outside optical transmission module;
The described control parameter that receives at least includes: receive the RAM degree of depth, reception postpones point and warm reset configures Information;The described control parameter that sends at least includes: sends starting point, send sequence content, transmission sequence Length, transmission sequence rate, inside and outside path and transmission odd even configuration information.
Method the most according to claim 6, it is characterised in that also include:
Path is returned in inside according to described transmission selection of control parameter, sends described transmission sequence to connecing Receive module.
Method the most according to claim 6, it is characterised in that described reception connects from outside light Receive and also include before parallel data that A/D modular converter sends the step that caches:
Receive user's input information by user's access interface and carry out parameter configuration.
Method the most according to claim 8, it is characterised in that described parallel data is sampled Step include: start send data time start counting up, count value reach receive postpone some configuration Open sampling window during numerical value and carry out data sampling.
Method the most according to claim 8, it is characterised in that described by sampled data preserve extremely The step of memory modules includes:
When writing address ram less than the numerical value receiving the configuration of the RAM degree of depth, to the reception of memory modules RAM preserves data;Stop preserving when writing address ram equal to the numerical value receiving the configuration of the RAM degree of depth Data, and export the signal preserved for user's inquiry.
CN201210531731.XA 2012-12-11 2012-12-11 Optical fiber and digital OTDR detection method and device Active CN103873141B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210531731.XA CN103873141B (en) 2012-12-11 2012-12-11 Optical fiber and digital OTDR detection method and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210531731.XA CN103873141B (en) 2012-12-11 2012-12-11 Optical fiber and digital OTDR detection method and device

Publications (2)

Publication Number Publication Date
CN103873141A CN103873141A (en) 2014-06-18
CN103873141B true CN103873141B (en) 2016-12-07

Family

ID=50911308

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210531731.XA Active CN103873141B (en) 2012-12-11 2012-12-11 Optical fiber and digital OTDR detection method and device

Country Status (1)

Country Link
CN (1) CN103873141B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106160853B (en) * 2015-04-01 2019-01-18 索尔思光电(成都)有限公司 A kind of multi-functional LD driving circuit, module and method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102158280A (en) * 2011-04-02 2011-08-17 王健 Method for modulating and superposing optical time domain reflectometer (OTDR) testing signals in data transmission optical signals and OTDR testing method
CN202077027U (en) * 2011-04-02 2011-12-14 王健 Optical transmission module with OTDR (optical time domain reflectometer) function and optical communication equipment with OTDR function
CN102761375A (en) * 2012-07-10 2012-10-31 青岛海信宽带多媒体技术有限公司 Optical line terminal optical terminal used in Gigabit passive optical network

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7369219B2 (en) * 2005-04-21 2008-05-06 Fundacao Cpqd-Centro De Pesquisa E Desenvolvimento Em Telecominicacoes Active wavelength converter for use with an optical time-domain reflectometer (OTDR) and method for increasing OTDR supervision distance range

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102158280A (en) * 2011-04-02 2011-08-17 王健 Method for modulating and superposing optical time domain reflectometer (OTDR) testing signals in data transmission optical signals and OTDR testing method
CN202077027U (en) * 2011-04-02 2011-12-14 王健 Optical transmission module with OTDR (optical time domain reflectometer) function and optical communication equipment with OTDR function
CN102761375A (en) * 2012-07-10 2012-10-31 青岛海信宽带多媒体技术有限公司 Optical line terminal optical terminal used in Gigabit passive optical network

Also Published As

Publication number Publication date
CN103873141A (en) 2014-06-18

Similar Documents

Publication Publication Date Title
JP2011238288A5 (en)
CN102801744B (en) A kind of communication means and system
CN106292409A (en) A kind of real-time emulation system based on FPGA multi tate optical-fibre communications and emulation mode thereof
CN105785335A (en) Automatic digital array reception channel performance test system based on cPCI
CN106469127B (en) A data access device and method
CN104866452A (en) Multi-serial port extension method based on FPGA and TL16C554A
CN111683310B (en) Networking type data acquisition and analysis system and method
CN113141279B (en) Switch mesh test system and method
CN101726452B (en) Photon Correlator Based on Field Programmable Gate Array (FPGA)
CN116990542A (en) A fluid velocity measurement method, equipment, device and medium based on ultrasonic water meter
CN102209110A (en) Online controllable sensing node positioning method
CN113190291A (en) Configurable protocol conversion system and method based on network-on-chip data acquisition
TW200739600A (en) Multi-port memory device with serial input/output interface and control method thereof
CN103970692B (en) RapidIO serial data processing methods
CN112416823A (en) Sensor data read-write control method, system and chip in burst mode
CN103873141B (en) Optical fiber and digital OTDR detection method and device
CN105094743A (en) First input first output (FIFO) data cache and method thereof for performing time delay control
CN110673021B (en) NoC-based boundary scan test control method and controller interface
CN104636151B (en) Fpga chip configuration structure and collocation method based on application memory
CN106713179A (en) Adaptive rate allocation method and network element
CN114416019A (en) Data management method and system
CN201589663U (en) Photon Correlator Based on Field Programmable Gate Array (FPGA)
CN101394453B (en) Power source noise model establishing method and apparatus thereof
Chao et al. Design of instrument control system based on labview
CN118733392A (en) A power consumption detection system and control method based on FPGA on-chip encryption circuit

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20151012

Address after: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice

Applicant after: ZTE Corp.

Applicant after: SANECHIPS TECHNOLOGY Co.,Ltd.

Address before: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice

Applicant before: ZTE Corp.

C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20221205

Address after: 518055 Zhongxing Industrial Park, Liuxian Avenue, Xili street, Nanshan District, Shenzhen City, Guangdong Province

Patentee after: SANECHIPS TECHNOLOGY Co.,Ltd.

Address before: 518057 Ministry of justice, Zhongxing building, South Science and technology road, Nanshan District hi tech Industrial Park, Shenzhen, Guangdong

Patentee before: ZTE Corp.

Patentee before: SANECHIPS TECHNOLOGY Co.,Ltd.

TR01 Transfer of patent right