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CN103840008B - 基于bcd工艺的高压ldmos器件及制造工艺 - Google Patents

基于bcd工艺的高压ldmos器件及制造工艺 Download PDF

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CN103840008B
CN103840008B CN201410126232.1A CN201410126232A CN103840008B CN 103840008 B CN103840008 B CN 103840008B CN 201410126232 A CN201410126232 A CN 201410126232A CN 103840008 B CN103840008 B CN 103840008B
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CN103840008A (zh
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胡浩
宁小霖
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CHENGDU LIXIN MICROELECTRONIC SCIENCE & TECHNOLOGY Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65Lateral DMOS [LDMOS] FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 

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Abstract

本发明公开了一种基于BCD工艺的高压LDMOS器件及制造工艺,高压LDMOS器件包括衬底,衬底为N型衬底,N型衬底上为P型埋层,P型埋层上为N型薄外延层,N阱位于N型薄外延层的一侧,N阱靠近多晶硅的一侧为被场氧化层覆盖的P型轻掺杂顶层,另一侧为N型注入层,N型注入层向上延伸至漏极,P阱位于N型薄外延层的另一侧,P阱的中上部为p型场区,p型场区上有短接N型注入层和短接P型注入层,短接N型注入层和短接P型注入层的连接处向上延伸至源极,N阱和P阱的连接处有栅极氧化层,栅极氧化层上为多晶硅,多晶硅外接栅极。本发明所述LDMOS器件的耐压区长度较小,能在保证击穿电压不变的条件下大幅度减少器件的导通电阻。

Description

基于BCD工艺的高压LDMOS器件及制造工艺
技术领域
本发明涉及一种高压LDMOS器件及制造工艺,尤其涉及一种基于BCD工艺的高压LDMOS器件及制造工艺。
背景技术
BCD是一种单片集成工艺技术,这种技术能够在同一芯片上制作双极管bipolar、CMOS和DMOS器件,称为BCD工艺。LDMOS即横向扩散金属氧化物半导体,高压LDMOS器件是在高压功率集成电路中常采用的器件,用于满足耐高压、实现功率控制等方面的要求,常用于射频功率电路。
现有基于BCD工艺的高压LDMOS器件的衬底材料选择的是p型衬底,在P型衬底上生长N型外延层,并采用singleresurf技术来提高耐压,这种结构的LDMOS器件性能不高,在满足电压的前提下导通电阻较大。
发明内容
本发明的目的就在于为了解决上述问题而提供一种高性能的基于BCD工艺的高压LDMOS器件及制造工艺。
本发明通过以下技术方案来实现上述目的:
一种基于BCD工艺的高压LDMOS器件,包括衬底,所述衬底为N型衬底,N型衬底上为P型埋层,P型埋层上为N型薄外延层,N阱位于N型薄外延层的一侧,N阱靠近多晶硅的一侧为被场氧化层覆盖的P型轻掺杂顶层,另一侧为N型注入层,N型注入层向上延伸至漏极,P阱位于N型薄外延层的另一侧,P阱的中上部为p型场区,p型场区上有短接N型注入层和短接P型注入层,短接N型注入层和短接P型注入层的连接处向上延伸至源极,N阱和P阱的连接处有栅极氧化层,栅极氧化层上为多晶硅,多晶硅外接栅极。
一种基于BCD工艺的高压LDMOS器件采用的制造工艺,包括以下步骤:
(1)选择掺杂为磷的N型衬底,厚度为0~1000um;
(2)进行硼注入以形成P型埋层,能量为0~1000kev,剂量为1e11~1e15/cm2
(3)在P型埋层上进行外延生长得到N型薄外延层,厚度为0~30um;
(4)分别进行磷注入和硼注入,磷注入能量300kev、剂量4e12/cm2,硼注入能量100kev、剂量1e13/cm2,然后在1100度温度下进行氮气退火形成N阱和P阱,阱的深度能够和埋层穿通;
(5)进行硼注入,能量为100Kev,剂量为1e12/cm2,然后在1000度温度下进行氮气退火形成P型轻掺杂顶层;
(6)采用两步离子注入形成p型场区,第一离子注入能量为1~200kev,剂量为1e11~1e15/cm2,第二步离子注入为硼注入,能量为1~300kev,剂量为1e11~1e15/cm2
(7)栅极氧化层生长;
(8)多晶硅淀积,采用LPCVD(LowPressureChemicalVaporDeposition,低压力化学气相沉积)的方式,方块电阻范围为1~100ohm/square;
(9)分别进行N型注入和P型注入,以形成源极、漏极的欧姆接触;
(10)淀积氧化层,作为层间介质;
(11)做源极/漏极的铝电极;
(12)钝化层淀积,膜层结构是PETEOS和PESIN,其中,PETEOS是指采用PECVD(PlasmaEnhancedChemicalVaporDeposition,等离子体增强化学气相沉积)的方式,以TEOS为原材料,来生长出来的硅氧化层薄膜,PESIN是指采用PECVD的方式来生长出来的氮化硅薄膜。
本发明的有益效果在于:
本发明所述LDMOS器件采用N型浓掺杂衬底上再生长轻掺杂的N型外延层,并采用OVLD技术提高耐压,与传统的LDMOS器件相比,在同等耐压的前提下,本发明所述LDMOS器件的耐压区长度较小,能在保证击穿电压不变的条件下大幅度减少器件的导通电阻。
附图说明
图1是传统高压LDMOS器件的结构示意图;
图2是本发明所述高压LDMOS器件的结构示意图;
图3是本发明所述高压LDMOS器件加工过程中在形成N阱和P阱后的结构示意图;
图4是本发明所述高压LDMOS器件加工过程中在形成栅极氧化层和多晶硅后的结构示意图。
具体实施方式
下面结合附图对本发明作进一步说明:
如图2所示,本发明所述基于BCD工艺的高压LDMOS器件,包括衬底,所述衬底为N型衬底N-substrate,N型衬底N-substrate上为P型埋层P-bury,P型埋层P-bury上为N型薄外延层,N阱N-well位于N型薄外延层的一侧,N阱N-well靠近多晶硅poly的一侧为被场氧化层oxide覆盖的P型轻掺杂顶层P-top,另一侧为N型注入层n+,N型注入层n+向上延伸至漏极drain,P阱P-well位于N型薄外延层的另一侧,P阱P-well的中上部为p型场区P-field,p型场区P-field上有短接N型注入层n+和短接P型注入层p+,短接N型注入层n+和短接P型注入层p+的连接处向上延伸至源极source,N阱N-well和P阱P-well的连接处有栅极氧化层gateoxide,栅极氧化层gateoxide上为多晶硅poly,多晶硅poly外接栅极gate。图2中还示出了硅的局部氧化层locos。
本发明所述基于BCD工艺的高压LDMOS器件采用的制造工艺,包括以下步骤:
(1)选择掺杂为磷的N型衬底N-substrate,厚度为0~1000um;
(2)进行硼注入以形成P型埋层P-bury,能量为0~1000kev,剂量为1e11~1e15/cm2
(3)在P型埋层P-bury上进行外延生长得到N型薄外延层,厚度为0~30um;
(4)分别进行磷注入和硼注入,磷注入能量300kev、剂量4e12/cm2,硼注入能量100kev、剂量1e13/cm2,然后在1100度温度下进行氮气退火形成N阱N-well和P阱P-well,阱的深度能够和埋层穿通;形成N阱N-well和P阱P-well后的高压LDMOS器件如图3所示;
(5)进行硼注入,能量为100Kev,剂量为1e12/cm2,然后在1000度温度下进行氮气退火形成P型轻掺杂顶层P-top;
(6)采用两步离子注入形成p型场区P-field,第一离子注入能量为1~200kev,剂量为1e11~1e15/cm2,第二步离子注入为硼注入,能量为1~300kev,剂量为1e11~1e15/cm2
(7)栅极氧化层gateoxide的生长;
(8)多晶硅poly淀积,采用LPCVD的方式,方块电阻范围为1~100ohm/square;形成栅极氧化层gateoxide和多晶硅poly后的高压LDMOS器件如图4所示;
(9)分别进行N型注入和P型注入,以形成源极、漏极的欧姆接触;
(10)淀积氧化层locos,作为层间介质;
(11)做源极/漏极的铝电极;
(12)钝化层淀积,膜层结构是PETEOS和PESIN;最后得到的高压LDMOS器件如图2所示。
如图1所示,传统高压LDMOS器件的衬底材料为p型衬底P-substrate,在p型衬底P-substrate上做p型埋层p-bury,并在p型衬底P-substrate上生长N型外延层N-epi,这种结构的LDMOS器件性能不高,在满足电压的前提下导通电阻较大。

Claims (1)

1.一种基于BCD工艺的高压LDMOS器件采用的制造工艺,所述基于BCD工艺的高压LDMOS器件包括衬底,所述衬底为N型衬底,N型衬底上为P型埋层,P型埋层上为N型薄外延层,N阱位于N型薄外延层的一侧,N阱靠近多晶硅的一侧为被场氧化层覆盖的P型轻掺杂顶层,另一侧为N型注入层,N型注入层向上延伸至漏极,P阱位于N型薄外延层的另一侧,P阱的中上部为p型场区,p型场区上有短接N型注入层和短接P型注入层,短接N型注入层和短接P型注入层的连接处向上延伸至源极,N阱和P阱的连接处有栅极氧化层,栅极氧化层上为多晶硅,多晶硅外接栅极;其特征在于:所述制造工艺包括以下步骤:
(1)选择掺杂为磷的N型衬底,厚度为0~1000um;
(2)进行硼注入以形成P型埋层,能量为0~1000kev,剂量为1e11~1e15/cm2
(3)在P型埋层上进行外延生长得到N型薄外延层,厚度为0~30um;
(4)分别进行磷注入和硼注入,磷注入能量300kev、剂量4e12/cm2,硼注入能量100kev、剂量1e13/cm2,然后在1100度温度下进行氮气退火形成N阱和P阱,阱的深度能够和埋层穿通;
(5)进行硼注入,能量为100Kev,剂量为1e12/cm2,然后在1000度温度下进行氮气退火形成P型轻掺杂顶层;
(6)采用两步离子注入形成p型场区,第一离子注入能量为1~200kev,剂量为1e11~1e15/cm2,第二步离子注入为硼注入,能量为1~300kev,剂量为1e11~1e15/cm2
(7)栅极氧化层生长;
(8)多晶硅淀积,采用LPCVD的方式,方块电阻范围为1~100ohm/square;
(9)分别进行N型注入和P型注入,以形成源极、漏极的欧姆接触;
(10)淀积氧化层,作为层间介质;
(11)做源极/漏极的铝电极;
(12)钝化层淀积,膜层结构是PETEOS和PESIN。
CN201410126232.1A 2014-03-31 2014-03-31 基于bcd工艺的高压ldmos器件及制造工艺 Expired - Fee Related CN103840008B (zh)

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US10229993B2 (en) * 2016-03-14 2019-03-12 Maxin Integrated Products, Inc. LDMOS transistors including resurf layers and stepped-gates, and associated systems and methods
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TWI709196B (zh) * 2018-12-21 2020-11-01 新唐科技股份有限公司 半導體裝置及其形成方法
CN110518070B (zh) * 2019-09-03 2022-11-15 深圳第三代半导体研究院 一种适用于单片集成的碳化硅ldmos器件及其制造方法
CN119653851B (zh) * 2024-12-18 2025-11-18 中国电子科技集团公司第二十四研究所 一种bcd工艺器件及制备方法

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