CN103839812A - Semiconductor device and method for preparing same - Google Patents

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof. The method includes: providing a semiconductor substrate; forming a gate dielectric layer on the substrate; forming a gate material layer and a gate dielectric layer on the gate dielectric layer. Hard mask layer; patterning the hard mask layer and part of the gate material layer to form the upper part of the dummy gate; forming a dummy spacer on the sidewall of the upper part of the dummy gate; etching the A gate material layer is left to form the lower part of the dummy gate, the critical dimension of the lower part of the dummy gate is smaller than the upper part of the dummy gate; the dummy spacer and the hard mask layer are removed to A dummy gate is formed, and finally a metal gate is formed. The method of the invention solves the problems in the prior art, and the process is simpler.

Description

A kind of semiconductor device and its preparation method

technical field

The invention relates to the field of semiconductors, in particular, the invention relates to a semiconductor device and a preparation method thereof.

Background technique

In the field of integrated circuit manufacturing, with the continuous shrinking of MOS transistors, especially in the process below 32nm, various secondary effects caused by the physical limit of the device are inevitable, and the feature size of the device is reduced proportionally. , where the leakage from the gate to the substrate is prone to occur in the field of MOS transistor device and its circuit manufacturing.

The solution to the current process is to use high-K gate materials and metal gates. The current metal gate formation process is to first form a gate oxide, a gate dielectric layer, and a mask layer on a semiconductor substrate to form a stack , and then pattern the stack to form a dummy gate and form a spacer, then etch and remove the dummy gate, and then deposit a metal gate, and the metal gate may include a functional metal layer, a barrier layer and a metal material layer.

In the current fabrication method, in the gate-last process (Gate-last), especially in the high-k metal gate process of the high-k last gate (high-k last), the filling of the metal gate material decreases with the width of the gate trench It becomes more and more difficult, and it is easy to cause incomplete filling when filling, and form voids in the gate structure, which affects the performance during the period. In order to solve this problem, it is reported in the prior art that the wetting layer of the metal material Ti will form a relatively large overhang during PVD, which makes it difficult to fill the subsequent metal Al. This problem can be alleviated by using the Co wetting layer, but the Co wetting layer is a new material for the metal gate process, which brings great difficulties to the pollution control and the metal gate CMP process.

Therefore, although the current conventional process for preparing metal gates is relatively mature, as the size of the period is further reduced, it is easy to cause incomplete filling when filling metal materials in the gate-last process, forming voids in the gate structure, and The method for solving this problem in the prior art will cause other problems, so further improvements to the prior art are required in order to eliminate the problem and improve the performance of the semiconductor device.

Contents of the invention

A series of concepts in simplified form are introduced in the Summary of the Invention, which will be further detailed in the Detailed Description. The summary of the invention in the present invention does not mean to limit the key features and essential technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.

In order to overcome the current existing problems, the present invention provides a method for preparing a semiconductor device, including:

Provide semiconductor substrates;

forming a gate dielectric layer on the substrate;

forming a gate material layer and a hard mask layer on the gate dielectric layer;

patterning the hard mask layer and a portion of the gate material layer to form an upper portion of a dummy gate;

forming a dummy spacer on an upper sidewall of the dummy gate;

etching the remaining gate material layer to form a lower portion of the dummy gate, the lower portion of the dummy gate having a critical dimension smaller than the upper portion of the dummy gate;

removing the dummy spacer and the hard mask layer to form a dummy gate, and finally forming a metal gate.

Preferably, the method further comprises the steps of:

forming a spacer on the dummy gate, and performing source-drain implantation to form a source-drain region;

Depositing and planarizing an interlayer dielectric layer on the source and drain regions to expose the top of the dummy gate;

The dummy gate is removed and a metal material is deposited, and then planarized to form the metal gate.

Preferably, the method further comprises the steps of:

Before forming the gate dielectric layer, a shallow trench isolation structure is formed in the substrate.

Preferably, the gate dielectric layer is oxide.

Preferably, the semiconductor substrate is thermally oxidized to form the gate dielectric layer.

Preferably, the gate material layer is a polysilicon layer.

Preferably, the method for patterning the hard mask layer and part of the gate material layer is:

Forming a patterned photoresist layer on the hard mask layer, using the photoresist layer as a mask to etch the hard mask layer and part of the gate material layer to form the upper part of the dummy gate .

Preferably, the method for forming the lower part of the dummy gate is:

First anisotropically etch the gate material layer to the gate dielectric layer, and then isotropically etch the gate material layer under the virtual spacer to reduce its critical dimension, so as to form a critical dimension smaller than The upper portion of the dummy gate is the lower portion of the dummy gate.

Preferably, when forming the upper part of the dummy gate, the gate material layer removed has a thickness of 5-20 nm.

Preferably, the material of the hard mask layer and the material of the dummy spacers have etch selectivity.

Preferably, the critical dimension of the lower part of the dummy gate is 1-5 nm smaller than that of the upper part of the dummy gate.

Preferably, the forming method of the metal gate is a gate-last process.

Preferably, the method for forming the metal gate is:

The dummy gate and the gate dielectric layer are removed, then an interface layer and a high-K dielectric layer are deposited, and then a metal material is deposited and planarized.

The present invention also provides a semiconductor device, comprising:

semiconductor substrate;

a metal gate structure located on the semiconductor substrate, the metal gate is a structure with a wide top and a narrow bottom;

The source and drain regions are located on both sides of the metal gate structure.

Preferably, the metal gate includes an upper half and a lower half, wherein the critical dimension of the upper half is 1-5 nm larger than that of the lower half.

Preferably, the metal gate structure includes an interface layer, a high-K dielectric layer and a metal material layer.

The present invention provides a new method for forming metal gate filling, in which the formation of the dummy gate is performed twice, the upper half of the wider dummy gate is etched for the first time, and then protected by a dummy spacer The upper half of the dummy gate is wider, and the lower half is etched to etch thinner lines, so that the critical dimension of the lower half of the dummy gate is smaller than that of the upper half, so that the upper part is wider and the lower part is narrower, To form a larger opening, after the larger opening is formed, it is beneficial to the filling of the high-K material layer and the metal material layer, and will not cause holes and voids, which solves the problems in the prior art, and the described The process is simpler.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. Embodiments of the present invention and their descriptions are shown in the drawings to explain the device and principle of the present invention. In the attached picture,

1-8 are schematic diagrams of the preparation of the semiconductor device of the present invention;

FIG. 9 is a flowchart of the preparation of the semiconductor device of the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

For a thorough understanding of the present invention, a detailed description will be presented in the following description to illustrate the semiconductor device and the method of manufacturing the same according to the present invention. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

It should be noted that the terms used herein are for the purpose of describing specific embodiments only, and are not intended to limit exemplary embodiments according to the present invention. As used herein, singular forms are intended to include plural forms unless the context clearly dictates otherwise. In addition, it should also be understood that when the terms "comprising" and/or "comprising" are used in this specification, it indicates the presence of the features, integers, steps, operations, elements and/or components, but does not exclude the presence or One or more other features, integers, steps, operations, elements, components and/or combinations thereof are added.

Now, exemplary embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. These example embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of these exemplary embodiments to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same reference numerals are used to designate the same elements, and thus their descriptions will be omitted.

Below in conjunction with Fig. 1-8, the preparation method of semiconductor device described in the present invention is described further:

Referring to FIG. 1 , a semiconductor substrate 201 is provided, and the semiconductor substrate may be at least one of the materials mentioned below: silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc., other active devices can also be formed in the semiconductor substrate. In the present invention, silicon-on-insulator (SOI) is preferred, and the silicon-on-insulator (SOI) includes a support substrate, an oxide insulating layer, and a semiconductor material layer from bottom to top, wherein the top semiconductor material layer is a single Crystalline silicon layer, polysilicon layer, SiC or SiGe. Since the SOI is made with an oxide insulating layer under the active region of the device, and the oxide insulating layer is buried in the semiconductor base layer, the device has more excellent performance, but is not limited to the above examples.

Then shallow trench isolation 202 is formed on the substrate. The method for forming shallow trench isolation 202 can be a method commonly used in the prior art. For example, firstly, a first oxide layer is sequentially formed on the semiconductor substrate 201 and the first nitride layer. Next, a dry etching process is performed to sequentially etch the first nitride layer, the first oxide layer and the semiconductor substrate 201 to form trenches 202 . Specifically, a patterned photoresist layer may be formed on the first nitride layer, and the first nitride layer is dry-etched using the photoresist layer as a mask to transfer the pattern to the first nitride layer. layer, and using the photoresist layer and the first nitride layer as a mask to etch the first oxide layer and the semiconductor substrate 201 to form trenches. Of course, other methods can also be used to form the trenches, and since this process is well known in the art, no further description is given here.

Then, fill the shallow trench isolation material in the trench to form a first sub-shallow trench isolation structure. Specifically, a shallow trench isolation material may be formed on the first nitride layer and in the trench, and the shallow trench isolation material may be silicon oxide, silicon oxynitride and/or other existing low dielectric constant materials; A chemical mechanical polishing process is performed and stopped on the first nitride layer to form a structure with shallow trench isolation.

Continuing to refer to FIG. 2, forming a gate dielectric layer on the substrate;

Specifically, the gate dielectric layer is an oxide layer 203, specifically, silicon oxide (SiO2) or silicon oxynitride (SiON). The gate dielectric layer made of silicon oxide can be formed by using an oxidation process known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), and the like. Performing a nitriding process on silicon oxide can form silicon oxynitride, wherein the nitriding process can be high temperature furnace tube nitriding, rapid thermal annealing nitriding or plasma nitriding, of course, other nitriding processes can also be used, I won't go into details here. Silicon oxide (SiO2) is preferred in the present invention.

Next, forming a gate material layer 204 and a hard mask layer 205 on the gate dielectric layer;

Wherein, the gate material layer is a monocrystalline silicon layer, a polycrystalline silicon layer, SiC or SiGe, preferably a silicon layer in the present invention, and the semiconductor material layer can be selected from decompression epitaxy, low temperature epitaxy, selective epitaxy, liquid phase epitaxy , heteroepitaxy and molecular beam epitaxy, epitaxy is preferably selected in the present invention.

Wherein, the hard mask layer 205 is a nitride layer, preferably SiN, and the deposition method of the mask layer can be chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). One of low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxial growth (SEG) formed by the method.

Referring to FIG. 2 , patterning the hard mask layer and part of the gate material layer to form an upper portion of a dummy gate;

Specifically, a patterned photoresist layer is formed on the hard mask layer, and the hard mask layer and part of the gate material layer are etched using the photoresist layer as a mask to form a dummy gate. In this step, the hard mask layer and the gate material layer can be etched by dry method, CF ₄ , CHF ₃ can be selected in the dry etching, and N ₂ , CO ₂ , O ₂ as an etching atmosphere, wherein the gas flow is CF ₄ 10-200sccm, CHF ₃ 10-200sccm, N ₂ or CO ₂ or O ₂ 10-400sccm, the etching pressure is 30-150mTorr, etching time 5-120s, preferably 5-60s, more preferably 5-30s.

Preferably, the thickness of the gate material layer removed by etching in this step is 5-20 nm.

Referring to FIG. 3 , a dummy spacer 206 is formed on the upper sidewall of the dummy gate;

Specifically, a dummy spacer (spacer) 206 surrounding the upper part of the dummy gate is formed; the dummy spacer may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. As an optimized implementation of this embodiment, the virtual spacer is composed of silicon oxide and silicon nitride, and the specific process is: forming a first silicon oxide layer, a first silicon nitride layer, and a second silicon nitride layer on a semiconductor substrate. The silicon oxide layer is then etched to form spacers.

The dummy spacer structure, including nitride, oxynitride or their combination, is formed by deposition and etching. The dummy spacer structures can have different thicknesses, but the thickness of the spacer structures is typically 10 to 30 nm measured from the bottom surface.

As an example, spacer structures located on both sides of the gate structure and close to the gate structure may also be formed on the semiconductor substrate. Wherein, the spacer structure may include at least one oxide layer and/or at least one nitride layer.

Referring to FIG. 4, etching the remaining gate material layer to form a lower portion of the dummy gate, the critical dimension of the lower portion of the dummy gate is smaller than the upper portion of the dummy gate;

Specifically, etching the remaining gate material layer using the upper part of the dummy gate as a mask, first anisotropically etching the gate material layer to the gate dielectric layer, and then isotropically etching The critical dimension of the gate material layer under the dummy spacer is reduced to form the lower part of the dummy gate, and preferably, the lower part of the dummy gate is smaller than the critical dimension of the upper part of the dummy gate 1-5nm.

In the present invention, the high-K metal gate is divided into two parts, wherein the critical dimension of the upper half is larger than that of the lower half to form a larger opening. After the larger opening is formed, there are It facilitates the filling of the subsequent high-K material layer and the metal material layer, does not cause holes and voids, and solves the problems existing in the prior art.

Further, in the present invention, the anisotropic etching is alkaline wet etching, and the alkaline etching solution can be KOH, or EDP (ethylenediamine+hydroquinone+water), and TMAH (tetrahydroquinone) One or more of methyl ammonium hydroxide), hydrazine, lithium hydroxide and ammonia water. Wherein the concentration of the etching solution is 15-25%, at this time, the gate material layer and the gate dielectric layer have a larger etching selectivity ratio.

The isotropic etching can be pure chemical reaction etching or other methods, which will not be repeated here.

Referring to FIG. 5, removing the dummy spacer and the mask layer to form a dummy gate;

Specifically, in the present invention, dry or wet etching can be selected to remove the virtual spacer and the mask layer, wherein the material of the hard mask layer and the material of the virtual spacer have etching selectivity . Therefore, in the present invention, the virtual spacer and the mask layer can be removed in two parts.

The lower part of the dummy gate is exposed after removing the dummy spacer and the mask layer, and combined with the upper part of the dummy gate to form a dummy gate.

Referring to FIG. 6, a spacer 207 is formed on the dummy gate, and source-drain implantation is performed to form a source-drain region;

Specifically, a spacer 207 is formed on the dummy gate, and the method for forming the spacer may refer to the method for forming the dummy spacer.

Then perform source-drain implantation on the semiconductor material layer, wherein the ion type and doping concentration of the source-drain implantation can be selected from the range commonly used in the field.

The doping energy selected in the present invention is 2000ev-5kev, preferably 500-100ev, so as to ensure that the doping concentration can reach 5E17~1E25 atoms/cm ³ .

Preferably, an annealing step can be performed after the source-drain implantation. Specifically, after performing the thermal annealing step, the damage on the silicon wafer can be eliminated, and the minority carrier lifetime and mobility will be restored to varying degrees. It will also get a certain proportion of activation, so the device efficiency can be improved.

The annealing step is generally to place the substrate under the protection of high vacuum or high-purity gas, and heat it to a certain temperature for heat treatment. In the present invention, the high-purity gas is preferably nitrogen or an inert gas. The thermal annealing The temperature of the step is 800-1200°C, and the time of the thermal annealing step is 1-200s.

As a further preference, rapid thermal annealing can be selected in the present invention, specifically, one of the following methods can be selected: pulsed laser rapid annealing, pulsed electron beam rapid annealing, ion beam rapid annealing, continuous wave laser rapid annealing And incoherent broadband light sources (such as halogen lamps, arc lamps, graphite heating) rapid annealing, etc. Those skilled in the art can make selections as needed, and are not limited to the examples given.

Continuing to refer to FIG. 6 , an interlayer dielectric layer 208 is deposited on the source and drain regions and planarized to expose the top of the dummy gate;

The interlayer dielectric layer can be a metal interlayer dielectric layer 208, preferably formed of a low dielectric constant dielectric material, such as fluorosilicate glass (FSG), silicon oxide, carbon-containing material (carbon -containing material), porous material (porous-like material) or similar.

The interlayer dielectric layer may be a silicon oxide layer, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high-density plasma (HDP) manufacturing process, for example Undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer can also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS) or boron-doped Tetraethoxysilane (BTEOS).

For the interlayer dielectric layer, SiO2, fluorocarbon (CF), carbon-doped silicon oxide (SiOC), or silicon carbonitride (SiCN) can be used, for example. Alternatively, a thin film of SiCN formed on a fluorocarbon (CF) or the like may be used. Fluorocarbons contain fluorine (F) and carbon (C) as main components. Fluorocarbons can also use those having an amorphous (non-crystalline) structure. The interlayer dielectric layer may also use a porous structure such as carbon-doped silicon oxide (SiOC).

7-8, removing the dummy gate and depositing a metal material, and then planarized to form a metal gate;

Specifically, as shown in FIG. 7 , firstly, the dummy gate is removed to form a trench. The removal method may be photolithography and etching. The gas used in the etching process includes HBr, which is used as the main etching gas; O2 or Ar, which is used as an etching supplementary gas, can improve the etching quality.

Referring to FIG. 8, the metal material is then planarized to form a metal gate. Specifically, the gate of the present invention is a high-K metal gate HKMG (high-k insulating layer + metal gate), and the gate The formation can be a gate-first process or a gate-last process. When the gate-last process is selected in the present invention, the dummy gate is removed, and then an interface layer is deposited and high-K dielectric layers, followed by metal deposition and planarization.

In an embodiment of the present invention, the metal gate is formed by depositing a plurality of thin film stacks. The thin film includes a work interface layer, a high-K material layer and a metal material layer.

The high-K material is used to form the gate dielectric layer, for example, a high-K material obtained by introducing Si, Al, N, La, Ta and other elements into HfO2 and optimizing the ratio of each element. The method for forming the gate dielectric layer may be a physical vapor deposition process or an atomic layer deposition process. In an embodiment of the present invention, a HfAION gate dielectric layer is formed on the SiO2 interface layer with a thickness of 15 to 60 angstroms.

The metal material layer can be deposited by CVD or PVD. After the conductive layer is formed, annealing is performed at a temperature of 300-500 degrees Celsius. The reaction time in nitrogen-containing environment is 10-60 minutes. Finally, the conductive layer is planarized to remove the conductive layer other than the trench to form a metal gate.

The present invention also provides a semiconductor device, comprising:

semiconductor substrate;

a metal gate located on the semiconductor substrate, and the metal gate has a structure with a wide top and a narrow bottom;

The source and drain regions are located on both sides of the metal gate.

Wherein, the metal gate includes an upper half and a lower half, wherein the critical dimension of the upper half is 1-5nm larger than that of the lower half.

The present invention provides a new method for forming metal gate filling, in which the formation of the dummy gate is performed twice, the upper half of the wider dummy gate is etched for the first time, and then protected by a dummy spacer The upper half of the dummy gate is wider, and the lower half is etched to etch thinner lines, so that the critical dimension of the lower half of the dummy gate is smaller than that of the upper half, so that the gate is wide at the top and narrow at the bottom, To form a larger opening, after the larger opening is formed, it is beneficial to the filling of the high-K material layer and the metal material layer, and will not cause holes and voids, which solves the problems in the prior art, and the described The process is simpler.

Fig. 9 is a process flow chart for preparing the semiconductor device of the present invention, including the following steps:

Step 201 provides a semiconductor substrate;

Step 202 forming a gate dielectric layer on the substrate;

Step 203 forming a gate material layer and a hard mask layer on the gate dielectric layer;

Step 204 patterning the hard mask layer and part of the gate material layer to form the upper part of the dummy gate;

Step 205 forming a dummy spacer on the upper sidewall of the dummy gate;

Step 206 etching the remaining gate material layer to form a lower portion of the dummy gate, the critical dimension of the lower portion of the dummy gate being smaller than that of the upper portion of the dummy gate;

Step 207 removes the dummy spacer and the hard mask layer to form a dummy gate, and finally forms a metal gate.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (16)

1. A method for preparing a semiconductor device, comprising: Provide semiconductor substrates; forming a gate dielectric layer on the substrate; forming a gate material layer and a hard mask layer on the gate dielectric layer; patterning the hard mask layer and a portion of the gate material layer to form an upper portion of a dummy gate; forming a dummy spacer on an upper sidewall of the dummy gate; etching the remaining gate material layer to form a lower portion of the dummy gate, the lower portion of the dummy gate having a critical dimension smaller than the upper portion of the dummy gate; removing the dummy spacer and the hard mask layer to form a dummy gate, and finally forming a metal gate. 2. method according to claim 1, is characterized in that, described method also comprises the following steps: forming a spacer on the dummy gate, and performing source-drain implantation to form a source-drain region; Depositing and planarizing an interlayer dielectric layer on the source and drain regions to expose the top of the dummy gate; The dummy gate is removed and a metal material is deposited, and then planarized to form the metal gate. 3. method according to claim 1, is characterized in that, described method also comprises the following steps: Before forming the gate dielectric layer, a shallow trench isolation structure is formed in the substrate. 4. The method according to claim 1, wherein the gate dielectric layer is oxide. 5. The method of claim 1, wherein the semiconductor substrate is thermally oxidized to form the gate dielectric layer. 6. The method according to claim 1, wherein the gate material layer is a polysilicon layer. 7. The method according to claim 1, wherein the method for patterning the hard mask layer and part of the gate material layer is: Forming a patterned photoresist layer on the hard mask layer, using the photoresist layer as a mask to etch the hard mask layer and part of the gate material layer to form the upper part of the dummy gate . 8. The method according to claim 1, wherein the method for forming the lower part of the dummy gate is: First anisotropically etch the gate material layer to the gate dielectric layer, and then isotropically etch the gate material layer under the virtual spacer to reduce its critical dimension, so as to form a critical dimension smaller than The upper portion of the dummy gate is the lower portion of the dummy gate. 9 . The method according to claim 1 , wherein when forming the upper part of the dummy gate, the gate material layer removed has a thickness of 5-20 nm. 10. The method according to claim 1, wherein the material of the hard mask layer and the material of the dummy spacers have etch selectivity. 11. The method according to claim 1, wherein the critical dimension of the lower portion of the dummy gate is 1-5 nm smaller than that of the upper portion of the dummy gate. 12 . The method according to claim 1 , wherein the method of forming the metal gate is a gate-last process. 13 . 13. The method according to claim 12, wherein the method for forming the metal gate is: The dummy gate and the gate dielectric layer are removed, then an interface layer and a high-K dielectric layer are deposited, and then a metal material is deposited and planarized. 14. A semiconductor device comprising: semiconductor substrate; a metal gate structure located on the semiconductor substrate, the metal gate is a structure with a wide top and a narrow bottom; The source and drain regions are located on both sides of the metal gate structure. 15. The device according to claim 14, wherein the metal gate comprises an upper half and a lower half, wherein the critical dimension of the upper half is 1-5 nm larger than that of the lower half. 16. The device according to claim 14, wherein the metal gate structure comprises an interface layer, a high-K dielectric layer and a metal material layer.

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