CN103838533A - Synchronization method for graph signals in tiled display system of computer cluster and synchronization card - Google Patents
Synchronization method for graph signals in tiled display system of computer cluster and synchronization card Download PDFInfo
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Abstract
The invention provides a synchronization method for graph signals in a tiled display system of a computer cluster. The method comprises the steps of receiving the graph signals output by graphics cards of computers in the cluster, and converting each graph signal into a digital graph data stream; writing each graph data stream into a corresponding FIFO memory according to synchronous receiving logic, and reading out each graph data stream from the corresponding FIFO memory according to synchronous output logic on the basis of output synchronous signals and clock signals of the system; converting each read-out graph data stream into the corresponding graph signal and then output each graph signal to corresponding display equipment. The invention further discloses a synchronization card. According to the synchronization method and the synchronization card, by means of a single ultrahigh resolution graph generated by the computer cluster and formed by splicing multiple graphs, the frame rates of all the graph signals output to the display system and the phases of the synchronous signals are accurately consistent, a picture integrally output by the system is smooth and is not torn, and low cost and higher flexibility are achieved compared with a system built on the basis of high-end graphics cards which are in a single model and support external synchronization.
Description
Technical field
The present invention relates to computer graphical process field, more specifically, relate to synchronous method and the sync card of figure signal in a kind of computer cluster splice displaying system.
Background technology
In recent years, in fields such as virtual reality, engineering design, geospatial information are visual, there is increasing system to use multi-display or multi-projector to show the figure of ultrahigh resolution, overlarge area.This type systematic often needs very high data-handling capacity and the processing power to figure, and computer cluster can provide this type systematic needed high-performance, and the task distribution that ultrahigh resolution figure is generated completes on many computing machines.Group system also has extensibility and modular feature, has very high dirigibility and higher cost performance.In these systems, need the key issue solving to be, if many that the task of ultrahigh resolution figure generation is distributed in group system according to screen area have been counted, how to make the multiple figure output signals that result from many computing machines in the time forming single ultrahigh resolution figure, accomplish smooth and seamless, and can the problem such as not tear because the difference of the output frame rate of each display card and synchronizing signal phase place produces picture, in addition, some system also requires the computer graphical signal of output to synchronize with a television image signal, this is also that common computer display system is irrealizable.
At present, the computer display card of a few high-end provides outer synchronous function, make the output timing of display card consistent with external reference signal, by all using such display card in computing machines all in cluster, can generate the single ultrahigh resolution figure of smooth and seamless, but this class display card is all high-end professional display card, expensive, also higher to the configuration requirement of computing machine, increase the cost of system, and, because the computing machine in system can only use special display card, therefore can not make full use of existing multi-purpose computer resource.
In addition, in to the less demanding applied environment of graphical quality, it is unanimous on the whole that some system also realizes the frame per second of the new output frame of each computing machine by software approach, do not consider phase problem, every frame figure of each computer export can not ensure to belong to same picture, the problem that such system unavoidably there will be picture to tear, its application is very limited.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide synchronous method and the sync card of figure signal in a kind of computer cluster splice displaying system, can solve in prior art, exist in the time that many computing machines generate single ultrahigh resolution figure simultaneously, cannot make the problem of the figure signal precise synchronization of each computer export.
For achieving the above object, technical scheme of the present invention is achieved in that
On the one hand, provide the synchronous method of figure signal in a kind of computer cluster splice displaying system, having comprised: received the figure signal of each computer display card output in cluster, and each figure signal is changed into digital figure data stream; Control module writes corresponding first-in first-out FIFO storer according to synchronous receive logic by each graphics streams, and according to synchronous output logic, output synchronizing signal and clock signal based on system are read graphics streams from FIFO storer; After being changed into figure signal, each graphics streams of reading exports corresponding display device to.
Preferably, each graphics streams is write corresponding first-in first-out FIFO storer by the synchronous receive logic of described basis, comprise: in the time that the graph data amount in FIFO storer reaches default upper threshold value, during the vertical flyback of tablet pattern signal, control module sends to suspend to main frame interrupts application, and forbid writing new graph data to FIFO storer, after this, graph data amount in FIFO storer reduces gradually, when graph data amount is lower than default while restarting threshold value, control module sends to restart to main frame interrupts application, and allow to write new graph data to FIFO storer.
Preferably, the synchronous output logic of described basis, output synchronizing signal and clock signal based on system, graphics streams is read from FIFO storer, comprise: when the graph data amount in certain the FIFO storer in cluster is during lower than default lower threshold value, the control module corresponding with this FIFO storer read after whole graph datas of present frame, again read pointer is placed in to the beginning of this frame, repeat to broadcast this frame, simultaneously, during the vertical flyback of the broadcast figure signal before broadcasting repeating frame, the control module corresponding with this FIFO storer can send repeating frame pulse to other all control modules, the start address place that has broadcasted frame before other all control modules are also placed in read pointer, in an ensuing frame time, repeat the frame broadcasting before broadcasting.
Preferably, before receiving the figure signal of each computer display card output in cluster, the method also comprises: the graphic frame that every main frame need to generate and broadcast self is carried out serial number.
Preferably, after sending time-out interruption application to main frame in described control module, the method also comprises: main frame response suspends interruption application, suspends and broadcasts new graphic frame, records the up-to-date numbering of broadcasting graphic frame.
Preferably, described to main frame send restart interrupt application after, the method also comprises: interruption application is restarted in main frame response, again sends new graphic frame to computer display card, and the numbering that is numbered last graphic frame of broadcasting before time-out of new graphic frame adds one.
Preferably, synchronizing signal and clock signal are generated based on reference video input signal or self clock free-running operation by main timing generation module, and synchronizing signal and clock signal are sent to corresponding with it control module.
Preferably, main timing generation module is exported to synchronizing signal and clock signal arbitrary adjacent from timing generation module with it, generate and send to corresponding with it control module with synchronizing signal and the clock signal of the synchronizing signal synchronised receiving from timing generation module, and the synchronizing signal receiving and clock signal are transmitted to adjacent with it another from timing generation module.
On the other hand, a kind of sync card is provided, comprise, figure signal receiver module, timing generation module, control module, first-in first-out FIFO storer and figure signal sending module, wherein, figure signal receiver module, is connected with computer display card and control module respectively, for the figure signal of receiving computer video card output, and after being changed into digital figure data stream, figure signal exports to control module; Timing generation module, is connected with control module, for generating synchronizing signal and clock signal to control module; Control module, be connected with FIFO storer, timing generation module, figure signal receiver module and figure signal sending module, for graphics streams being write to FIFO storer according to synchronous receive logic, and according to synchronous output logic, output synchronizing signal and clock signal based on system, export to figure signal sending module after graphics streams is read from FIFO storer; FIFO storer, is connected with control module, for the control based on control module, and buffer memory graphics streams; Figure signal sending module, is connected with control module and display device respectively, the graphics streams transmitting for receiving control module, and export described display device to after graphics streams is changed into figure signal.
Preferably, described graphics streams is write described FIFO storer by the synchronous receive logic of described basis, and according to synchronous output logic, output synchronizing signal and clock signal based on system, described graphics streams is read and comprised from described FIFO storer: in the time that the graph data amount in FIFO storer reaches default upper threshold value, during the vertical flyback of tablet pattern signal, control module sends to suspend to main frame interrupts application, and forbid writing new graph data to FIFO storer, after this, graph data amount in FIFO storer reduces gradually, when graph data amount is lower than default while restarting threshold value, control module sends to restart to main frame interrupts application, and allow to write new graph data to described FIFO storer, when the graph data amount in certain the FIFO storer in cluster is during lower than default lower threshold value, the control module corresponding with this FIFO storer read after whole graph datas of present frame, again read pointer is placed in to the beginning of this frame, repeat to broadcast this frame, simultaneously, during the vertical flyback of the broadcast figure signal before broadcasting repeating frame, the control module corresponding with this FIFO storer can send repeating frame pulse to other all control modules, the start address place that has broadcasted frame before other all control modules are also placed in read pointer, in an ensuing frame time, repeat the frame broadcasting before broadcasting.
Preferably, control module also comprises gating pulse input/output interface, is connected, for sending starting impulse or repeating frame pulse to other all control modules with other all control modules.
Preferably, when timing generation module is main timing generation module, synchronizing signal and clock signal are based on reference video input signal or according to self clock free-running operation and generate, timing generation module be during from timing generation module, and synchronizing signal and clock signal synchronizing signal and the clock signal based on carrying out the generation of autonomous timing generation module self generates.
Preferably, timing generation module also comprises: figure synchronizing signal output interface and figure synchronizing signal input interface, wherein:
Figure synchronizing signal output interface, in the time that timing generation module is main timing generation module, export to adjacent from timing generation module for synchronizing signal and clock signal that self is occurred, when timing generation module is during from timing generation module, adjacent from timing generation module for the synchronizing signal of input and clock signal are transmitted to.
Figure synchronizing signal input interface, for receiving synchronizing signal and the clock signal from adjacent timing generation module.
Preferably, sync card also comprises computer external interface, is connected, is connected with main frame by computer bus interface with control module, and main frame carries out communication by computer external interface and control module.
Technique effect of the present invention:
1. the present invention utilizes the common single ultrahigh resolution figure being formed by multiple graphic joinings that generates of computer cluster, input signal is converted to graph data according to synchronous input logic after the figure signal that receives computer display card output after, store, and according to synchronous output logic, output synchronizing signal and clock signal based on system, graph data is read and is converted to figure signal and transfer to display device, make the frame per second of the each figure signal that outputs to display system accurately consistent with synchronizing signal phase place, entire system output picture is level and smooth without tearing, graphical quality is better than the system synchronous based on software frame per second,
2. because technical scheme of the present invention can be used any computer display card, the system that synchronous high-end video card builds outside the support based on single model, has the dirigibility of lower cost and Geng Gao.
3. because technical scheme of the present invention can realize synchronizeing of computer graphical signal and a television image signal, solved common computer display system in prior art and can not realize the problem of synchronizeing with TV signal.
Brief description of the drawings
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms the application's a part, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 shows according to the process flow diagram of the synchronous method of figure signal in the computer cluster splice displaying system of the embodiment of the present invention one;
Fig. 2 shows according to the concrete processing flow chart of the synchronous method of figure signal in the computer cluster splice displaying system of the embodiment of the present invention two;
Fig. 3 shows according to the synchronous method Computer main frame of figure signal in the computer cluster splice displaying system of the embodiment of the present invention three and interrupts processing flow chart;
Fig. 4 shows according to the structural representation of the sync card of the embodiment of the present invention four;
Fig. 5 shows according to the structural representation of the sync card of the embodiment of the present invention five;
Fig. 6 shows according to the connection diagram of many computing machine sync cards in the cluster splice displaying system of the embodiment of the present invention six;
Fig. 7 shows according to the structural representation of the sync card of the embodiment of the present invention seven.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.
Embodiment mono-
Fig. 1 shows according to the process flow diagram of the synchronous method of figure signal in the computer cluster splice displaying system of the embodiment of the present invention one, and as shown in Figure 1, the method comprises:
Step S101, receives the figure signal of each computer display card output in cluster, and each figure signal is changed into digital figure data stream;
Wherein, the figure signal receiving can be: the forms such as VGA, DVI, HDMI; Before step S101, the method also comprises: the graphic frame that every main frame need to generate and broadcast self is carried out serial number, for example, in system, a ultrahigh resolution figure is exported respectively by the figure output software in N platform computing machine, figure output software in every computing machine is responsible for generating and an output part of corresponding whole ultrahigh resolution figure with it, and, the graphic frame that every computing machine need to generate and broadcast self is carried out serial number, since the 1st frame, to N frame, N+1 frame
Step S102, control module writes corresponding first-in first-out FIFO storer according to synchronous receive logic by each graphics streams, and according to synchronous output logic, output synchronizing signal and clock signal based on system are read graphics streams from FIFO storer;
Concrete, each FIFO storer presets a upper threshold value, restart threshold value and lower threshold value, when the output frame rate of computer display card is during faster than the output frame rate of sync card, it is full that FIFO storer will become, in the time that the graph data amount in FIFO storer reaches default upper threshold value, during the vertical flyback of tablet pattern signal, control module sends to suspend to main frame interrupts application, and forbid writing new graph data to FIFO storer, after this, graph data amount in FIFO storer reduces gradually, when graph data amount is lower than default while restarting threshold value, control module sends to restart to main frame interrupts application, and allow to write new graph data to FIFO storer.
In the time that the output frame rate of computer display card is slower than the output frame rate of sync card, it is empty that FIFO storer can become, when the graph data amount in certain the FIFO storer in cluster is during lower than default lower threshold value, the control module corresponding with this FIFO storer read after whole graph datas of present frame, again read pointer is placed in to the beginning of this frame, repeat to broadcast this frame, simultaneously, during the vertical flyback of the broadcast figure signal before broadcasting repeating frame, the control module corresponding with this FIFO storer can send repeating frame pulse to other all control modules, the start address place that has broadcasted frame before other all control modules are also placed in read pointer, in an ensuing frame time, repeat the frame broadcasting before broadcasting.That is, when certain sync card is in the time repeating to broadcast N frame figure, other all sync cards all repeat to broadcast N frame, have ensured that the broadcast frame number of all sync cards is identical all the time.
Synchronizing signal and clock signal are generated based on reference video input signal or self clock free-running operation by main timing generation module, and synchronizing signal and clock signal are sent to corresponding with it control module.
Main timing generation module is exported to synchronizing signal and clock signal arbitrary adjacent from timing generation module with it, generate and send to corresponding with it control module with synchronizing signal and the clock signal of the synchronizing signal synchronised receiving from timing generation module, and the synchronizing signal receiving and clock signal are transmitted to adjacent with it another from timing generation module.
Step S103, exports corresponding display device to after each graphics streams of reading is changed into figure signal.
Embodiments of the invention utilize the common single ultrahigh resolution figure being formed by multiple graphic joinings that generates of computer cluster, input signal is converted to graph data according to synchronous input logic after the figure signal that receives computer display card output after, store, and according to synchronous output logic, output synchronizing signal and clock signal based on system, graph data is read and is converted to figure signal and transfer to display device, make the frame per second of the each figure signal that outputs to display system accurately consistent with synchronizing signal phase place, entire system output picture is level and smooth without tearing, graphical quality is better than the system synchronous based on software frame per second.
Embodiment bis-
Fig. 2 shows according to the concrete processing flow chart of the synchronous method of figure signal in the computer cluster splice displaying system of the embodiment of the present invention two, as shown in Figure 2, in system, actual output frame rate based on each computer display card is different, therefore, some computer display card output frame rates are faster than the output frame rate of sync card, some computer display card output frame rates are slower than the output frame rate of sync card, in order to make all figure sync cards synchronously broadcast the graphic frame that sequence number is identical, each sync card need to synchronously be processed the figure signal of input, synchronous treatment step is as follows:
The logic that writes of FIFO storer is carried out odd number step, and the logic of reading of FIFO storer is carried out even number step; After system starts, the execution step that FIFO storer writes logic is
Step S201, FIFO storer allows to write graph data, graphic frame numbering N=1, FIFO storer write pointer resets, and, FIFO storer is write to logic initialization that is;
Step S203, does figure incoming frame start? if so, perform step S205, if not, return to step S201;
Does step S205, allow graphic frame to write? if so, perform step S207, if not, execution step S217;
Step S207, writes graph data and flows to FIFO storer;
Step S209, does vertical trace finish? if so, perform step S211, if not, return to step S207;
Step S211, frame number N=N+1;
Step S213, does FIFO memory data amount reach upper threshold value? if so, perform step S215, now send to suspend to main frame and interrupt application, if not, return to step S201;
Step S215, FIFO storer forbids writing graphics streams, after this step completes, returns to step S201;
Step S217, does vertical flyback start? if so, perform step S219; If not, return to step S205;
Step S219, does the data volume of FIFO storer reaches restart threshold value? if so, perform step S223, if not, execution step S221;
Step S221, does vertical flyback finish? if so, return to step S201, if not, execution step S219;
Step S223, FIFO storer allows to write graphics streams, now sends to restart to main frame and interrupts application.
After system starts, the execution step that FIFO storer is read logic is
Step S202, removes repeating frame mark, and FIFO storer read pointer resets, and, FIFO storer is read to logic initialization that is;
Does is step S204 main sync card? if so, perform step S204-1, if not, execution step S204-2; Does step S204-1, reach startup threshold value? if so, perform step S204-11, that is, send starting impulse, execution step S206; Return to if not step S204; Does step S204-2, receive starting impulse? if so, perform step S206, if not, return to step S204;
Polylith sync card need to start output simultaneously, and restarts after need to making FIFO storer fill a part of graph data, avoids occurring very soon FIFO storer sky, and makes write pointer forever be ahead of read pointer.
Step S206, does figure output frame start? if so, perform step S208, if not, return to step S204-11 for main sync card, for returning to step S204-2 from sync card;
Step S208, is repeating frame mark effective? if so, perform step S210, if not, execution step S212;
Step S210, read pointer points to the start address of previous frame, removes repeating frame mark;
Step S212, reads graphics streams from FIFO storer;
Step S214, does vertical trace finish? if so, perform step S216, if not, return to step S212;
Step S216, does FIFO storer reach lower threshold value? if so, perform step S218, if not, execution step S220;
Step S218, puts repeating frame mark, sends repeating frame pulse, returns to step S204-11;
Step S220, does vertical flyback finish? if so, return to step S204-11 for main sync card, for returning to step S204-2 from sync card, if not, execution step S222;
Does step S222, receive repeating frame pulse? if so, perform step S224, if not, return to step S220;
Step S224, puts repeating frame pulse, returns to step S204-2.
Above-mentioned steps has completed the synchronous processing of arbitrary sync card to tablet pattern signal in system.
Embodiment tri-
Fig. 3 shows according to the synchronous method Computer main frame of figure signal in the computer cluster splice displaying system of the embodiment of the present invention three and interrupts processing flow chart; As shown in Figure 3, it is as follows that main frame interrupts treatment step:
Step S301, system starts;
Step S302, broadcasts graphic frame;
Step S303, is main frame received to suspend and is interrupted application? if so, perform step S304, return to if not step S302;
Step S304, records the up-to-date numbering N that broadcasts graphic frame;
Step S305, stops broadcasting new graphic frame;
Step S306, is computing machine received to restart and is interrupted application? if so, perform step S307, if not, return to step S305;
Step S307, sends new graphic frame to computer display card again, and the numbering that is numbered last graphic frame of suspending front broadcast of new graphic frame adds one, restarts broadcast graphic frame since N+1 frame.
Embodiment tetra-
Fig. 4 shows according to the structural representation of the sync card of the embodiment of the present invention four, as shown in Figure 4, this sync card comprises: figure signal receiver module 10, timing generation module 20, control module 30, first-in first-out FIFO storer 40 and figure signal sending module 50, wherein
Figure signal receiver module 10, is connected with computer display card and control module 30 respectively, for the figure signal of receiving computer video card output, and exports to control module 30 after figure signal is changed into digital figure data stream;
Wherein, the figure signal receiving can be: the forms such as VGA, DVI, HDMI; In addition, the display mode information that figure signal receiver module 10 is also stored sync card support reads for computer display card;
Timing generation module 20, is connected with control module 30, for generating synchronizing signal and clock signal to control module 30;
Wherein, when timing generation module is main timing generation module, synchronizing signal and clock signal generate (the reference video input shown in accompanying drawing 4 is optional) based on reference video input signal or according to self clock free-running operation, timing generation module be during from timing generation module, and synchronizing signal and clock signal synchronizing signal and the clock signal based on carrying out the generation of autonomous timing generation module self generates.
Control module 30, respectively with FIFO storer 40, figure signal receiver module 10 and figure signal sending module 50 are connected, for graphics streams being write to FIFO storer 40 according to synchronous receive logic, and according to synchronous output logic, output synchronizing signal and clock signal based on system, export to figure signal sending module 50 after graphics streams is read from FIFO storer 40; Concrete operations are:
In the time that the graph data amount in FIFO storer 40 reaches default upper threshold value, during the vertical flyback of tablet pattern signal, control module 30 sends to suspend to main frame interrupts application, and forbid writing new graph data to FIFO storer 40, after this, graph data amount in FIFO storer 40 reduces gradually, when graph data amount is lower than default while restarting threshold value, control module 30 sends to restart to main frame interrupts application, and allows to write new graph data to FIFO storer 40, when the graph data amount in certain the FIFO storer 40 in cluster is during lower than default lower threshold value, the control module 30 corresponding with this FIFO storer 40 read after whole graph datas of present frame, again read pointer is placed in to the beginning of this frame, repeat to broadcast this frame, simultaneously, during the vertical flyback of the broadcast figure signal before broadcasting repeating frame, the control module 30 corresponding with this FIFO storer 40 can send repeating frame pulse to other all control modules 30, the start address place that has broadcasted frame before other all control modules 30 are also placed in read pointer, in an ensuing frame time, repeat the frame broadcasting before broadcasting.
FIFO storer 40, is connected with control module 30, for the control based on control module 30, and buffer memory graphics streams;
Figure signal sending module 50, be connected with control module 30 and display device respectively, for receiving the graphics streams that control module 30 transmits, and after being changed into figure signal, graphics streams exports described display device to, in addition, the display mode information that all right reading displayed equipment of figure signal sending module 50 is supported, for control module 30.
In embodiments of the invention, utilize the common single ultrahigh resolution figure being formed by multiple graphic joinings that generates of computer cluster, input signal is converted to graph data according to synchronous input logic after the figure signal that receives computer display card output after, store, and according to synchronous output logic, output synchronizing signal and clock signal based on system, graph data is read and is converted into figure signal and transfer to display device, make the frame per second of the each figure signal that outputs to display system accurately consistent with synchronizing signal phase place, entire system output picture is level and smooth without tearing, graphical quality is better than the system synchronous based on software frame per second, can use any computer display card, the system that synchronous high-end video card builds outside the support based on single model, has the dirigibility of lower cost and Geng Gao simultaneously.
Embodiment five
Fig. 5 shows according to the structural representation of the sync card of the embodiment of the present invention five; As shown in Figure 5, control module 30 also comprises: gating pulse input/output interface 302, is connected with other all control modules 30, for sending starting impulse or repeating frame pulse to other all control modules 30.Wherein, allly start from sync card in order to make as the control module 30 of main sync card simultaneously, can send starting impulse to all control modules 30 from sync card, but no matter the control module of main sync card or the control module from sync card, according to synchronous output logic and based on synchronizing signal and clock signal, can send the control module of repeating frame pulse to other all sync cards.
Embodiment six
Fig. 6 shows according to the connection diagram of many computer graphical sync cards in the group system of the embodiment of the present invention six; As shown in Figure 6, we illustrate signal input/output relation and connected mode between sync card taking three computer graphical sync cards as example:
First, timing generation module 20 also comprises: figure synchronizing signal output interface 202 and figure synchronizing signal input interface 204, wherein:
Figure synchronizing signal output interface 202, in the time that timing generation module is main timing generation module, export to adjacent from timing generation module for synchronizing signal and clock signal that self is occurred, when timing generation module is during from timing generation module, adjacent from timing generation module for the synchronizing signal of input and clock signal are transmitted to.
Figure synchronizing signal input interface 504, for receiving synchronizing signal and the clock signal from adjacent timing generation module.
Wherein, figure synchronizing signal output interface 202 and figure synchronizing signal input interface 204 are bidirectional interfaces, both can work as input interface and also can work as output interface, if sync card is as main sync card, its figure synchronizing signal input interface 204 is when output interface use, , main sync card is exported to figure synchronizing signal respectively that it is adjacent from sync card, figure synchronizing signal input interface from sync card receives the figure synchronizing signal from adjacent sync card, figure synchronizing signal output interface from sync card goes out the figure synchronizing signal ring receiving, be transmitted to an other adjacent sync card.
Allly start from sync card in order to make as the control module 30 of main sync card simultaneously, can send starting impulse to all control modules 30 from sync card, but no matter the control module of main sync card or the control module from sync card can send the control module of repeating frame pulse to other all sync cards according to synchronous output logic and based on synchronizing signal and clock signal.
Embodiments of the invention utilize the common single ultrahigh resolution figure being formed by multiple graphic joinings that generates of computer cluster, every computing machine in cluster is installed a sync card, the figure signal of computer display card output is connected to corresponding sync card, the output signal of sync card is connected to corresponding display device, sync cards all in system synchronously broadcast the graphic frame that sequence number is identical, after every sync card carries out synchronous processing to the figure signal of input, output pattern signal is to display device corresponding to this computing machine, sync card is also to corresponding computing machine feedback operation state, and accept the control of computing machine, make the frame per second of the each figure signal that outputs to display system accurately consistent with synchronizing signal phase place, entire system output picture is level and smooth without tearing, graphical quality is better than the system synchronous based on software frame per second.
Embodiment seven
Fig. 7 shows according to the structural representation of the sync card of the embodiment of the present invention seven; As shown in Figure 7, sync card also comprises: computer external interface 60, be connected with control module 30, be connected with main frame by computer bus interfaces such as PCI, PCIe, main frame carries out communication by computer external interface 60 and control module 30, query facility state, configuration device parameter, the interrupt request that reception and response module produce etc.
In addition, in the time that bus bandwidth is enough, sync card can also gather graph data into computing machine as capture card, or the graph data in computing machine is transferred on sync card and is broadcasted.
Embodiments of the invention utilize the common single ultrahigh resolution figure being formed by multiple graphic joinings that generates of computer cluster, every computing machine in cluster is installed a sync card, the figure signal of computer display card output is connected to corresponding sync card, the output signal of sync card is connected to corresponding display device, sync cards all in system synchronously broadcast the graphic frame that sequence number is identical, after every sync card carries out synchronous processing to the figure signal of input, output pattern signal is to display device corresponding to this computing machine, sync card is also to corresponding computing machine feedback operation state, and accept the control of computing machine, make the frame per second of the each figure signal that outputs to display system accurately consistent with synchronizing signal phase place, entire system output picture is level and smooth without tearing, graphical quality is better than the system synchronous based on software frame per second, because technical scheme of the present invention can be used any computer display card, the system that synchronous high-end video card builds outside the support based on single model, has the dirigibility of lower cost and Geng Gao.Because technical scheme of the present invention can realize synchronizeing of computer graphical signal and a television image signal, solve common computer display system in prior art and can not realize the problem of synchronizeing with TV signal.
Obviously, those skilled in the art should be understood that, above-mentioned of the present invention each module or each step can realize with general calculation element, they can concentrate on single calculation element, or be distributed on the network that multiple calculation elements form, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in memory storage and be carried out by calculation element, or they are made into respectively to each integrated circuit modules, or the multiple modules in them or step are made into single integrated circuit module to be realized.Like this, the present invention is not restricted to any specific hardware and software combination.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (14)
1. a synchronous method for figure signal in computer cluster splice displaying system, is characterized in that, comprising:
Receive the figure signal of each computer display card output in cluster, and described each figure signal is changed into digital figure data stream;
Control module writes corresponding first-in first-out FIFO storer according to synchronous receive logic by described each graphics streams, and according to synchronous output logic, output synchronizing signal and clock signal based on system are read described graphics streams from described FIFO storer;
After being changed into figure signal, described each graphics streams of reading exports corresponding display device to.
2. the synchronous method of figure signal in computer cluster splice displaying system according to claim 1, is characterized in that, described each graphics streams is write corresponding first-in first-out FIFO storer by the synchronous receive logic of described basis, comprising:
In the time that the graph data amount in described FIFO storer reaches default upper threshold value, during the vertical flyback of tablet pattern signal, described control module sends to suspend to main frame interrupts application, and forbid writing new graph data to described FIFO storer, after this, graph data amount in described FIFO storer reduces gradually, when described graph data amount is lower than default while restarting threshold value, described control module sends to restart to main frame interrupts application, and allows to write new graph data to described FIFO storer.
3. the synchronous method of figure signal in computer cluster splice displaying system according to claim 1, it is characterized in that the synchronous output logic of described basis, output synchronizing signal and clock signal based on system, described graphics streams is read from described FIFO storer, being comprised:
When the graph data amount in FIFO storer described in certain in cluster is during lower than default lower threshold value, the described control module corresponding with this FIFO storer read after whole graph datas of present frame, again read pointer is placed in to the beginning of this frame, repeat to broadcast this frame, simultaneously, during the vertical flyback of the broadcast figure signal before broadcasting repeating frame, the described control module corresponding with this FIFO storer can send repeating frame pulse to other all control modules, the start address place that has broadcasted frame before other all control modules are also placed in read pointer, in an ensuing frame time, repeat the frame broadcasting before broadcasting.
4. the synchronous method of figure signal in computer cluster splice displaying system according to claim 1, is characterized in that, in described reception cluster, before the figure signal of each computer display card output, the method also comprises:
The graphic frame that every main frame need to generate and broadcast self is carried out serial number.
5. the synchronous method of figure signal in computer cluster splice displaying system according to claim 2, is characterized in that, after sending time-out interruption application to main frame in described control module, the method also comprises:
Main frame responds described time-out and interrupts application, suspends and broadcasts new graphic frame, records the up-to-date numbering of broadcasting graphic frame.
6. the synchronous method of figure signal in computer cluster splice displaying system according to claim 2, is characterized in that, in described control module, after interruption application is restarted in main frame transmission, the method also comprises:
Described in main frame response, restart and interrupt application, again send new graphic frame to computer display card, the numbering that is numbered last graphic frame of broadcasting before time-out of new graphic frame adds one.
7. according to the synchronous method of figure signal in the computer cluster splice displaying system described in claim 1 or 3, it is characterized in that, described synchronizing signal and clock signal are generated based on reference video input signal or self clock free-running operation by main timing generation module, and described synchronizing signal and clock signal are sent to corresponding with it control module.
8. the synchronous method of figure signal in computer cluster splice displaying system according to claim 7, it is characterized in that, described main timing generation module is exported to described synchronizing signal and clock signal arbitrary adjacent from timing generation module with it, describedly generate and send to corresponding with it control module with synchronizing signal and the clock signal of the described synchronizing signal synchronised receiving from timing generation module, and the described synchronizing signal receiving and clock signal are transmitted to adjacent with it another from timing generation module.
9. a sync card, is characterized in that, comprising: figure signal receiver module, timing generation module, control module, first-in first-out FIFO storer and figure signal sending module, wherein,
Described figure signal receiver module, is connected with computer display card and described control module respectively, for receiving the figure signal of described computer display card output, and exports to described control module after described figure signal is changed into digital figure data stream;
Described timing generation module, is connected with described control module, for generating synchronizing signal and clock signal to described control module;
Described control module, be connected with described FIFO storer, described timing generation module, described figure signal receiver module and described figure signal sending module, for described graphics streams being write to described FIFO storer according to synchronous receive logic, and according to synchronous output logic, output synchronizing signal and clock signal based on system, export to described figure signal sending module after described graphics streams is read from described FIFO storer;
Described FIFO storer, is connected with described control module, for the control based on described control module, and graphics streams described in buffer memory;
Described figure signal sending module, is connected with described control module and display device respectively, the graphics streams transmitting for receiving described control module, and export described display device to after described graphics streams is changed into figure signal.
10. sync card according to claim 9, it is characterized in that, described graphics streams is write described FIFO storer by the synchronous receive logic of described basis, and according to synchronous output logic, output synchronizing signal and clock signal based on system, described graphics streams is read and comprised from described FIFO storer:
In the time that the graph data amount in described FIFO storer reaches default upper threshold value, during the vertical flyback of tablet pattern signal, described control module sends to suspend to main frame interrupts application, and forbid writing new graph data to described FIFO storer, after this, graph data amount in described FIFO storer reduces gradually, when described graph data amount is lower than default while restarting threshold value, described control module sends to restart to main frame interrupts application, and allows to write new graph data to described FIFO storer;
When the graph data amount in FIFO storer described in certain in cluster is during lower than default lower threshold value, the described control module corresponding with this FIFO storer read after whole graph datas of present frame, again read pointer is placed in to the beginning of this frame, repeat to broadcast this frame, simultaneously, during the vertical flyback of the broadcast figure signal before broadcasting repeating frame, the described control module corresponding with this FIFO storer can send repeating frame pulse to other all control modules, the start address place that has broadcasted frame before other all control modules are also placed in read pointer, in an ensuing frame time, repeat the frame broadcasting before broadcasting.
11. sync cards according to claim 10, is characterized in that, described control module also comprises gating pulse input/output interface, are connected, for sending starting impulse or described repeating frame pulse to other all control modules with other all control modules.
12. sync cards according to claim 9, it is characterized in that, when described timing generation module is main timing generation module, described synchronizing signal and clock signal are based on reference video input signal or according to self clock free-running operation and generate, described timing generation module is during from timing generation module, and described synchronizing signal and clock signal synchronizing signal and the clock signal based on occurring from described main timing generation module self generates.
13. sync cards according to claim 12, is characterized in that, described timing generation module also comprises: figure synchronizing signal output interface and figure synchronizing signal input interface, wherein:
Described figure synchronizing signal output interface, in the time that described timing generation module is main timing generation module, export to adjacent described from timing generation module for synchronizing signal and clock signal that self is occurred, when described timing generation module is during from timing generation module, adjacent from timing generation module for the synchronizing signal of input and clock signal are transmitted to.
Described figure synchronizing signal input interface, for receiving synchronizing signal and the clock signal from adjacent described timing generation module.
14. sync cards according to claim 9, it is characterized in that, also comprise computer external interface, be connected, be connected with main frame by computer bus interface with described control module, main frame carries out communication by described computer external interface and described control module.
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