CN103824883B - Groove MOSFET with terminal voltage-withstanding structure and manufacturing method of groove MOSFET - Google Patents

Abstract

The present invention proposes a trench MOSFET with a terminal withstand voltage structure and its manufacturing method. The trench MOSFET has trenches formed in the cell area and the terminal area respectively, and the trenches in the terminal area are at least two surrounding The closed annular groove of the cell area, at least one annular groove close to the cell area is an isolation ring, and the isolation ring is connected to zero potential, and at least one annular groove close to the scribing track is a stop ring, and the stop ring is connected with the scribe Track connection. The isolating ring of the trench MOSFET with a terminal withstand voltage structure of the present invention is connected to zero potential, which can effectively suppress leakage; the stop ring is connected to the scribe track, so that carriers will not accumulate along the stop ring, and the terminal withstand voltage is improved The isolation effect and pressure resistance effect of the structure. The manufacturing method of the present invention solves the withstand voltage and leakage problems of the trench MOSFET prepared by the three-layer photolithography process without increasing the complexity of the process, reduces the lateral leakage of the trench MOSFET, and improves the withstand voltage of the device. The process is simplified and the manufacturing cost is reduced.

Description

A trench MOSFET with terminal withstand voltage structure and its manufacturing method

technical field

The invention belongs to the field of basic electrical components and relates to the preparation of semiconductor devices, in particular to a terminal withstand voltage structure of a trench MOSFET and a manufacturing method thereof.

Background technique

Trench MOSFET is a new generation of power semiconductor device that integrates microelectronics technology and power electronics technology. It is widely used in DC- DC converters, voltage regulators, power management modules, automotive electronics and electromechanical control and other fields.

Trench MOSFET was proposed as early as the early 1980s. In the development of trench MOSFET, research on reducing product development costs revolves around obtaining higher cell density, lower on-resistance, more reliable structure and simpler The technological process and other aspects are expanded.

In terms of improving cell density and reducing product cost, with the development of process equipment and technology, by choosing more advanced hardware equipment, such as choosing a lithography machine with a shorter wavelength to achieve small-scale coating exposure, using controlled injection energy to achieve more A new low-level ion implanter is used to form a shallower source to ensure the channel length, thereby reducing the critical dimension of the process, reducing the cell size, and integrating more devices in the same area. However, the problem of increasing the cell density is that the cell size of the current low-voltage trench MOSFET has been reduced to 1um, and the space for further decline is getting smaller and smaller, and the reduction in size will lead to an increase in local field strength, which will inevitably bring Reduction of device reliability lifetime.

Another widely used method to reduce costs is to simplify the process steps. The method for manufacturing a trench MOSFET by a traditional process, as shown in FIG. 2, usually forms a lightly doped N-type epitaxial layer 2 on a semiconductor substrate 1, and grows a layer of silicon dioxide on the epitaxial layer 2. The first P-well (P-well) mask defines the P-type body region; then a thick silicon dioxide layer is grown on the surface of the silicon wafer, and the second trench mask is used to define the trench area. - A series of trenches are formed on the epitaxial layer, and a gate oxide layer 7 is grown in the trenches by thermal oxidation, polysilicon is deposited on the gate oxide layer 7, and then the polysilicon is etched back to form a gate electrode 6; then defined before In the P-type body region, perform the implantation of the first P-type impurity ions, diffuse to form the P-type body region 5; then use the third N+ mask to define the N+ source contact region 4 in the P-well region, Perform the implantation and diffusion of the second N-type impurity ions; then deposit an insulating dielectric layer 3 on the chip surface, use the fourth contact hole mask to define the contact hole pattern, photolithographically source hole 2, and fill the hole with a barrier layer Metal, and then sputter the top metal on the surface; finally use the fifth metal layer photomask to define the gate metal area and source metal area, and use dry etching to form the gate metal electrode and source metal electrode, in N A metal layer is deposited on the surface of the highly doped substrate to form the drain metal electrode 10 .

This process step includes 5 layers of photolithography mask, including trench mask layer (Poly layer), P well mask layer (P-well layer), N+ mask layer (N+ layer), contact hole mask The film layer (Contact layer) and the metal mask layer (Metal layer), that is to say, in the device manufacturing process, it needs to go through 5 photolithography processes. Photolithography is to transfer the pattern on the mask plate to the wafer, and each photolithography needs to go through at least 8 process steps, including vapor phase base film formation, spin coating, baking, exposure, post-exposure baking, Development, hard film baking and development inspection, these steps occupy a very large proportion of machines and time in wafer manufacturing.

In the trench MOSFET shown in Figure 1, the surface of the cells in the inner layer of the wafer is at the same potential, and there is no concentration of electric field, but there is a large potential difference between the cells at the wafer boundary, the substrate and the scribe lane , it is necessary to solve the problem of electric field concentration in the design, that is, to reduce the local strong electric field at the junction terminal, so as to improve the surface breakdown voltage tolerance. Figure 3 is a cross-sectional structure diagram along the AA' direction in Figure 2, and Figure 4 is a cross-sectional structure diagram along the BB' direction in Figure 2, because the breakdown voltage of this trench MOSFET is only 20-30V , the design of the edge terminal pressure ring does not need to be very complicated, and the gate metal can be used as the field plate of the P junction to meet the requirements.

In order to further simplify the manufacturing process of the trench MOSFET and reduce the manufacturing cost, novel processes such as the self-alignment process can also be used to reduce the number of exposures to reduce the cost. For example, Korean Jongdae Kim and others improved the structure and process of the trench MOSFET in 2001. Although this improvement can greatly reduce the production time and manufacturing cost of the device, thereby reducing the production cost. However, as shown in Figure 5, this process step cannot limit the P-well region and N+ region, and it is impossible to follow the traditional method of forming a P-type annular pressure-resistant ring on the periphery of the chip to improve the withstand voltage and reduce leakage. New methods need to be proposed. Termination design addresses reduced breakdown voltage and increased leakage.

Contents of the invention

The present invention aims at at least solving the technical problems existing in the prior art, and particularly innovatively proposes a trench MOSFET terminal withstand voltage structure and a manufacturing method thereof.

In order to achieve the above object of the present invention, according to the first aspect of the present invention, the present invention provides a trench MOSFET with a terminal withstand voltage structure, including a substrate and an epitaxial layer formed thereon, the conductive layer of the epitaxial layer The conductivity type of the substrate is the same as that of the substrate. An active region and a well region are sequentially formed in the epitaxial layer from top to bottom. The conductivity type of the well region is opposite to that of the substrate. The source The conductivity type of the region is the same as that of the substrate, and the upper surface of the source region is in the same plane as the upper surface of the epitaxial layer; the epitaxial layer is divided into a cell region and a terminal region, and the terminal region Surrounding the cell region, a gate lead region is formed in the terminal region, trenches are respectively formed in the cell region and the terminal region, and the depth of the trench is greater than that of the source region and the well The sum of the thicknesses of the region, the groove of the terminal region is at least two closed annular grooves surrounding the cell region, and the annular grooves are not connected to each other; a first A dielectric layer and a gate; a second dielectric layer is formed on the epitaxial layer, and a contact hole is formed in the second dielectric layer, and the contact hole includes a gate contact hole, a source contact hole and a stop ring contact hole ; A gate metal layer, a source metal layer and a stop ring metal layer are formed on the surface of the second dielectric layer, the gate metal layer is connected to the gate through a gate contact hole, and the source metal layer It is connected with the source region through a source contact hole, and the stop ring is connected with the stop ring metal layer through a stop ring contact hole; and a drain metal layer is formed under the substrate.

The terminal withstand voltage structure of the present invention uses a plurality of separation trenches to form an isolated terminal, replaces the traditional P-type injection junction terminal, and solves the problems of low withstand voltage and leakage without increasing the number of layers of the photolithography plate and the difficulty of the process, reducing the The leakage current of the trench MOSFET is reduced, and the withstand voltage of the device is improved.

In order to achieve the above object of the present invention, according to a second aspect of the present invention, the present invention provides a method for manufacturing a trench MOSFET with a terminal withstand voltage structure, comprising the following steps:

S1: provide the substrate;

S2: Form an epitaxial layer on the substrate, the conductivity type of the epitaxial layer is the same as that of the substrate, and sequentially form a well region and a source region in the epitaxial layer, the conductivity type of the well region Contrary to the conductivity type of the substrate, the conductivity type of the source region is the same as the conductivity type of the substrate, and the upper surface of the source region is on the same plane as the upper surface of the epitaxial layer;

S3: dividing the epitaxial layer to form a cell area and a terminal area, the terminal area surrounds the cell area, the terminal area includes a gate lead area, and trenches are formed in the cell area and the terminal area, The depth of the groove is greater than the sum of the thicknesses of the source region and the well region, and the groove in the termination region is at least two closed annular grooves surrounding the cell region, and the annular grooves are not separated from each other. connected, a first dielectric layer and a gate are formed in the trench, a second dielectric layer is formed on the epitaxial layer and the trench, a contact hole is formed on the second dielectric layer, and the contact The holes include a gate contact hole, a source contact hole and a stop ring contact hole, and a gate metal layer, a source metal layer and a stop ring metal layer are formed on the surface of the second dielectric layer, and the gate metal layer passes through the gate The contact hole is connected to the gate, the source metal layer is connected to the source region through the source contact hole, and the stop ring and the scribe track are respectively connected to the stop ring metal layer through the stop ring contact hole;

S4: forming a drain metal layer under the substrate.

The manufacturing method of the trench MOSFET with the terminal withstand voltage structure of the present invention solves the withstand voltage and leakage problems of the trench MOSFET prepared by the three-layer photolithography process without increasing the complexity of the process, and reduces the cost of the trench MOSFET. The lateral leakage improves the withstand voltage of the device, simplifies the process, and reduces the manufacturing cost.

In a preferred embodiment of the present invention, along the direction from inside to outside, at least one annular groove close to the cell region is an isolation ring, and the isolation ring is connected to zero potential.

In another preferred embodiment of the present invention, along the direction from outside to inside, at least one annular groove close to the scribe lane is a stop ring, and the stop ring is connected to the scribe lane.

In the trench MOSFET with terminal withstand voltage structure of the present invention, the isolation ring is connected to zero potential, the potential of the isolation ring is lower than the potential of the inner well region, and an inversion channel will not be formed in the well region, thereby effectively suppressing leakage The stop ring is connected to the scribe track, the potential of the stop ring is the same as that of the scribe track, and carriers will not accumulate along the stop ring, which improves the isolation effect and withstand voltage effect of the terminal withstand voltage structure.

In a preferred embodiment of the present invention, the distance between the isolation ring and the gate metal layer is the minimum distance allowed by the photolithography process, and the distance between the stop ring and the scribe lane is the minimum distance allowed by the photolithography process . This design saves chip area and improves chip utilization.

In another preferred embodiment of the present invention, an electric field extension ring is formed between the isolation ring and the stop ring, and the electric field extension ring is at least one closed annular groove that surrounds the isolation ring and is not connected to each other. Potential floating.

In the present invention, at least one electric field expansion ring is formed between the isolation ring and the stop ring, which is used for the isolation of the isolation ring and the stop ring and the extension of the electric field, and improves the lateral withstand voltage of the device.

Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and comprehensible from the description of the embodiments in conjunction with the following drawings, wherein:

Fig. 1 is a sectional view of a cell region and a terminal region of a trench MOSFET prepared by a five-layer photolithography process in the prior art;

Figure 2 shows the layout of the cell area and terminal area of the trench MOSFET in the prior art shown in Figure 1;

Fig. 3 is the sectional structure diagram along A-A ' direction shown in Fig. 2;

Fig. 4 is the sectional structure diagram along B-B ' direction shown in Fig. 2;

Fig. 5 is a sectional view of a cell region and a terminal region of a trench MOSFET prepared by a three-layer photolithography process in the prior art;

Fig. 6 is a schematic diagram of leakage when the first annular trench of the trench MOSFET with terminal withstand voltage structure of the present invention is suspended;

7 is a schematic diagram of leakage when the outermost annular groove of the trench MOSFET with a terminal withstand voltage structure is suspended in the present invention;

Fig. 8 is a schematic diagram of the layout of the cell region and the terminal region of the first preferred embodiment of the trench MOSFET with a terminal withstand voltage structure according to the present invention;

Fig. 9 is a schematic cross-sectional structure diagram of the C-C' direction cell region and terminal region shown in Fig. 8;

Fig. 10 is a schematic cross-sectional structure diagram of the D-D' direction cell region and terminal region shown in Fig. 8;

Fig. 11 is a schematic diagram of the layout of the cell region and the terminal region of the second preferred embodiment of the trench MOSFET with a terminal withstand voltage structure of the present invention;

Fig. 12 is a schematic cross-sectional structure diagram of the cell region and terminal region in the E-E' direction shown in Fig. 11;

Fig. 13 is a schematic cross-sectional structure diagram of the cell region and terminal region in the F-F' direction shown in Fig. 11;

Reference signs:

1 substrate; 2 epitaxial layer; 3 well region; 4 source region; 5 first dielectric layer; 6 gate;

71 source contact hole; 72 gate contact hole; 73 stop ring contact hole; 8 second dielectric layer;

91 source metal layer; 92 gate metal layer; 93 drain metal layer; 94 stop ring metal layer;

10 isolation ring; 11 cut-off ring; 12 cell area; 13 terminal area; 14 scribe lane;

15 electric field expansion ring; 16 interdigitated structure; 17 grid finger; 18 grid lead area.

detailed description

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

In describing the present invention, it should be understood that the terms "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", The orientation or positional relationship indicated by "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than Nothing indicating or implying that a referenced device or element must have a particular orientation, be constructed, and operate in a particular orientation should therefore not be construed as limiting the invention.

In the description of the present invention, unless otherwise specified and limited, it should be noted that the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be mechanical connection or electrical connection, or two The internal communication of each element may be directly connected or indirectly connected through an intermediary. Those skilled in the art can understand the specific meanings of the above terms according to specific situations.

The present invention proposes an embodiment of a trench MOSFET with a terminal withstand voltage structure, as shown in Figure 6 and Figure 7, the trench MOSFET includes a substrate 1 and an epitaxial layer 2 formed thereon, the substrate 1 is Any substrate material for preparing the MOSFET may specifically be but not limited to SOI, silicon, germanium, gallium arsenide, and in this embodiment, silicon is preferably used. The material of the epitaxial layer 2 may specifically be, but not limited to, silicon, germanium, and gallium arsenide. In this embodiment, the material preferably used is silicon, the substrate 1 is heavily doped, and the epitaxial layer 2 is lightly doped. The conductivity type is the same as that of the substrate 1 . In the epitaxial layer 2, an active region 4 and a well region 3 are sequentially formed from top to bottom, the conductivity type of the well region 3 is opposite to that of the substrate 1, and the conductivity type of the source region 4 is the same as that of the substrate 1, The upper surface of the source region 4 is in the same plane as the upper surface of the epitaxial layer 2 .

The epitaxial layer 2 is divided into a cell area 12 and a terminal area 13, and a gate lead area 18 is formed in the terminal area 13. In this embodiment, the cell area 12 is located in the central area, and the gate lead area 18 surrounds the cell area. 12. The terminal area 13 surrounds the gate lead area 18 and the cell area 12. The periphery of the terminal area 13 is a scribe lane 14. Grooves are respectively formed in the cell area 12 and the terminal area 13, and the depth of the groove is greater than The sum of the thickness of the source region 3 and the thickness of the well region 4. The groove of the terminal area 13 is at least two closed annular grooves surrounding the cell area 12, and the annular grooves are not connected to each other, and at least one annular groove close to the cell area along the direction from inside to outside is isolated The ring 10, the isolation ring 10 is connected to zero potential, at least one annular groove along the direction from outside to inside and close to the scribe lane 14 is a stop ring 11, and the stop ring 11 is connected to the scribe lane 14.

A first dielectric layer 5 and a gate 6 are formed in the trenches of the cell region 12 and the terminal region 13. The material of the first dielectric layer 5 can be any material for preparing a gate dielectric layer, specifically, but not limited to The high-K dielectric is silicon dioxide. In this embodiment, silicon dioxide is used for the first dielectric layer 5 . A conductive filling layer is formed on the first dielectric layer 5 in the trench as a gate 6, and the filling layer fills the trench. The material of the filling layer can be any material for preparing a gate, specifically but not limited to Polysilicon or metal. In this embodiment, polysilicon is preferably used for the filling layer.

A second dielectric layer 8 is formed on the epitaxial layer 2 and the trench. On the one hand, the second dielectric layer 8 is used to prevent external impurities from entering and affecting the performance of the MOSFET. On the other hand, it has the ability to fill holes to make the surface of the silicon wafer flat. The material of the second dielectric layer 8 may be but not limited to borophosphosilicate glass. Contact holes are formed on the second dielectric layer 8 , and the contact holes include a gate contact hole 72 , a source contact hole 71 and a stop ring contact hole 73 . In this embodiment, the gate contact hole 72 penetrates the second dielectric layer 8 above the gate 6, the source contact hole 71 penetrates the second dielectric layer 8 above the source region 4 on both sides of the trench, and the stop ring The contact hole 73 penetrates through the second dielectric layer 8 above the stop ring 11 . A gate metal layer 92, a source metal layer 91 and a stop ring metal layer 94 are formed on the surface of the second dielectric layer 8. The gate metal layer 92 is connected to the gate 6 through the gate contact hole 72, and the source metal layer 91 passes through The source contact hole 71 is connected to the source region 4 , the stop ring 11 is connected to the stop ring metal layer 94 through the stop ring contact hole 73 , and a drain metal layer 93 is formed under the substrate 1 . It should be noted that, in this embodiment, as shown in FIG. 8 or FIG. 11 , since the gate metal layer 92 of the gate wiring region 18 is disposed on the periphery of the cell region, the gate metal layer 92 needs to pass through the gate fingers 17 Connected to the gate 6 , a gate contact hole 72 is provided on the second dielectric layer 8 on the gate finger 17 , and the gate finger 17 is connected to the gate metal layer 92 through the gate contact hole 72 .

The trench MOSFET of the present invention adopts at least two sets of closed ring-shaped groove terminals on the periphery of the cell area to realize leakage isolation and electric field expansion. In order to prevent leakage channels, all grooves are closed ring-shaped grooves. Along the direction from the inside to the outside, that is, along the direction from the center of the cell area 12 to the terminal area 13, at least one annular groove close to the cell area 12 is an isolation ring 10, and the isolation ring 10 is connected to zero potential. In one aspect of the present invention In a preferred embodiment, only the annular groove closest to the cellular region 12 is the isolation ring 10. In this embodiment, the potential of the isolation ring 10 cannot be suspended. As shown in FIG. 6, if the potential of the isolation ring 10 is suspended, The expansion of the electric field makes the potential of the isolation ring 10 higher than the potential of the inner well region 4 , which will cause the well region 4 to invert and form a leakage channel. Along the direction from outside to inside, that is, along the direction from the terminal area 13 to the center of the cell area 12, at least one annular groove close to the scribe lane 14 is a stop ring 11, and the stop ring 11 is connected to the scribe lane 14. In this embodiment , only an annular groove closest to the scribe track 14 is the stop ring 11 , and its potential is short-circuited with the scribe track 14 . The potential of the stop ring 11 cannot be suspended either. If the potential of the stop ring 11 is suspended, as shown in FIG. Accumulation will lead to deterioration of the isolation effect, and the potential of the stop ring 11 is fixed to the potential of the scribe line 14, so that carriers will not accumulate along the stop ring 11, and the isolation effect and withstand voltage effect of the terminal withstand voltage structure are improved. It should be noted that the zero potential in the present invention refers to the lowest potential in each conductive region of the trench MOSFET, not a potential with a value of zero.

In this embodiment, in order to save area and improve chip utilization, the position of the isolation ring 10 is close to the gate metal layer 92 , and the position of the stop ring 11 is as close as possible to the scribe lane 14 . A specific solution that can be adopted is that the distance between the isolation ring 10 and the gate metal layer 92 is the minimum distance allowed by the photolithography process, and the distance between the stop ring 11 and the scribe line 14 is the minimum distance allowed by the photolithography process. It should be noted that the minimum distance allowed by the lithography process of the present invention refers to the minimum distance in the lithography process commonly used to prepare MOSFETs at present. With the progress of the process, this value will continue to shrink, but its determination method is the same, still Within the protection scope of the present invention.

In this embodiment, an electric field extension ring 15 is formed between the isolation ring 10 and the stop ring 11. The electric field extension ring 15 is at least one closed annular groove surrounding the isolation ring that is not connected to each other. The electric field extension ring 15 The potential of is suspended, which is used for the isolation of the isolation ring 10 and the stop ring 11 and the extension of the electric field.

In a preferred embodiment of the present invention, as shown in Figure 8, Figure 9 and Figure 10, the peripheral terminal design consists of four closed annular grooves, as shown in Figure 10, the innermost annular groove , that is, the isolation ring 10 is connected to the source metal layer 91 through the interdigitated structure 16 and the source contact hole 71 on the periphery of the cell area, and the outermost annular groove is the stop ring 11, which is connected to the scribed ring through the stop ring contact hole 73 The dicing track 14 is at the same potential. In the figure, the stop ring 11 is at the same potential as the scribing track 14 through the two stop ring contact holes 73 , so that the high potential is limited to the position of the stop ring 11 . It should be noted that the four annular grooves shown in the figure are only examples, and it is only necessary to ensure that the innermost ring has at least one annular groove connected to the low potential of the source metal layer 91, and the outermost ring has at least one annular groove The groove is at the same potential as the scribing track 14, and the equipotential annular groove is as close as possible to the scribing track 14, so as to limit high potential and save area. The suspended annular groove in the middle can adopt multiple rings to isolate and extend the electric field.

In another preferred embodiment of the present invention, as shown in Figure 11, Figure 12 and Figure 13, the peripheral terminal design is also composed of four closed annular grooves, as shown in Figure 13, the innermost annular groove The trench is the isolation ring 10 , the isolation ring 10 is connected to the gate finger 17 , and the isolation ring 10 is connected to the gate metal layer 92 through the gate contact hole 72 . The outermost annular groove, that is, the stop ring 11, is equipotential with the scribe track 14 through the stop ring contact hole 73. In the figure, the stop ring 11 is equipotential with the scribe track 14 through two stop ring contact holes 73, and the high potential is limited. at the position of the cut-off ring. It should be noted that the four annular grooves shown in the figure are only examples, and it is only necessary to ensure that the innermost ring has at least one annular groove connected to the low potential of the gate metal layer 92, and the outermost ring has at least one annular groove The groove is at the same potential as the scribing track 14, and the equipotential annular groove is as close as possible to the scribing track, so as to limit the high potential and save the area. The suspended annular groove in the middle can adopt multiple rings to isolate and extend the electric field.

The present invention also proposes a method for manufacturing a trench MOSFET with a terminal withstand voltage structure, which includes the following steps:

S1: providing substrate 1;

S2: Form an epitaxial layer 2 on the substrate 1. The conductivity type of the epitaxial layer 2 is the same as that of the substrate 1. A well region 3 and a source region 4 are sequentially formed in the epitaxial layer 2. The conductivity type of the well region 3 is the same as that of the substrate. The conductivity type of the bottom 1 is opposite, the conductivity type of the source region 4 is the same as that of the substrate 1, and the upper surface of the source region 4 is on the same plane as the upper surface of the epitaxial layer 2;

S3: Divide the epitaxial layer to form a cell area 12 and a terminal area 13, the terminal area 13 includes a gate lead area 18, in this embodiment, the cell area 12 is located in the central area, and the gate lead area 18 surrounds the cell area 12 , the terminal region 13 surrounds the gate lead region 18 and the cell region 12, and a trench is formed in the cell region 12 and the terminal region 13, the depth of the trench is greater than the sum of the thicknesses of the source region 3 and the well region 4, and the terminal region 13 The groove is at least two closed annular grooves surrounding the cell region 12, and the grooves are not connected to each other, along the direction from inside to outside, at least one annular groove close to the cell region 12 is an isolation ring 10, Along the direction from outside to inside, at least one annular groove close to the scribe line 14 is a stop ring 11, a first dielectric layer 5 and a gate 6 are formed in the groove, and a second dielectric layer is formed on the epitaxial layer 2 and the groove 8. Form a contact hole on the second dielectric layer 8, the contact hole includes a gate contact hole 72, a source contact hole 71 and a stop ring contact hole 73, and form a gate metal layer 92, a source contact hole 73 on the surface of the second dielectric layer 8 The pole metal layer 91 and the stop ring metal layer 94, the gate metal layer 92 is connected to the gate 6 through the gate contact hole 92, the source metal layer 91 is connected to the source region 4 through the source contact hole 71, and the stop ring 11 is connected to the gate through the stop ring 11. The ring contact hole 73 is connected to the stop ring metal layer 94;

S4: forming a drain metal layer 93 under the substrate 1 .

In this embodiment, step S3 specifically includes the following steps:

S41: On the epitaxial layer 2, photolithography, etch the cell region 12 and the terminal region 13 to form a groove, the depth of the groove is greater than the sum of the thicknesses of the source region 3 and the well region 4, and the groove of the terminal region 13 is at least two A closed annular groove around the cell area, along the direction from inside to outside, at least one annular groove close to the cell area 12 is an isolation ring 10, along the direction from outside to inside, at least one annular groove close to the scribing road 14 The groove is a stop ring 11;

S42: forming a first dielectric layer 5 along the inner surface of the trench, forming a gate 6 on the first dielectric layer 5 in the trench, and the gate 6 fills the trench;

S43: Form the second dielectric layer 8 on the epitaxial layer 2 and the trench, photolithography, etch the second dielectric layer 8 to form contact holes, the contact holes include gate contact holes 72, source contact holes 71 and stop ring contact holes 73;

S44: Form a metal layer on the surface of the second dielectric layer 8, photolithography, form the gate metal layer 92, the source metal layer 91 and the stop ring metal layer 94, the gate metal layer 92 is connected to the gate through the gate contact hole 72 6, the source metal layer 91 is connected to the well region 4 through the source contact hole 71, and the stop ring 11 is connected to the stop ring metal layer 94 through the stop ring contact hole 73.

In a preferred embodiment of the present invention, the preparation of the trench MOSFET of the present invention requires the following steps:

The first step: provide a substrate 1, the material of the substrate 1 is any substrate material for preparing MOSFET, specifically, it can be but not limited to SOI, silicon, germanium, gallium arsenide, in this embodiment, silicon is preferably used, The substrate 1 is heavily doped.

The second step: forming an epitaxial layer 2 on the substrate 1, the material of the epitaxial layer 2 can be but not limited to silicon, germanium, gallium arsenide, in this embodiment, the preferred material is silicon, the epitaxial layer 2 is lightly doped, and its conductivity type is the same as that of the substrate 1. The specific method for forming the epitaxial layer 2 may be but not limited to chemical vapor deposition.

Step 3: Form a well region 3 and a source region 4 sequentially in the epitaxial layer 2, the conductivity type of the well region 3 is opposite to that of the substrate 1, the conductivity type of the source region 4 is the same as that of the substrate 1, and The upper surface of the source region 3 is on the same plane as the upper surface of the epitaxial layer 2 . In this embodiment, the specific method of forming the well region 3 and the source region 4 may be, but not limited to, ion implantation.

Step 4: On the epitaxial layer 2, grooves are formed on the epitaxial layer 2 through the first photolithography, etching the cell region 12 and the terminal region 13, specifically using a mask, coating photoresist, and exposing and developing to expose the grooves that need to be etched. The upper surface of the etched groove area is etched to form a groove. The specific etching method can be but not limited to wet etching and dry etching, preferably dry etching. In this embodiment, the groove The depth is greater than the sum of the thicknesses of the source region 4 and the well region 3, and the groove of the terminal region 13 is at least two closed annular grooves surrounding the cell region 12, along the direction from inside to outside, close to the cell region 12 At least one annular groove is a spacer ring 10, along the direction from outside to inside, at least one annular groove close to the scribe line 14 is a stop ring 11, in another preferred embodiment of the present invention, between the spacer ring 10 and the stop ring 11 An electric field extension ring 15 may be formed therebetween. The electric field extension ring 15 is at least one annular groove surrounding the isolation ring 10 that is not connected to each other. The potential of the electric field extension ring 15 is suspended.

Step 5: Form a first dielectric layer 5 on the inner surface of the trench. The material of the first dielectric layer 5 can be any material for preparing a gate dielectric layer, specifically, it can be but not limited to silicon dioxide. In this embodiment The first dielectric layer 5 is made of silicon dioxide, and a gate oxide layer is formed after annealing. A conductive filling layer is formed on the first dielectric layer 5 in the trench, and the filling layer fills the trench. The material of the filling layer can be any material for preparing gates, specifically but not limited to polysilicon or metal. In this embodiment, polysilicon is preferably used as the filling layer, and the method of forming the first dielectric layer and the gate can be but not limited to chemical vapor deposition.

Step 6: Form a second dielectric layer 8 on the epitaxial layer 2 and the trench, perform second photolithography, etch the second dielectric layer 8 to form a contact hole, the contact hole includes a gate contact hole 72, a source electrode The contact hole 71 and the stop ring contact hole 73 . On the one hand, the second dielectric layer 8 is used to prevent external impurities from entering to affect the performance of the MOSFET. On the other hand, it has the ability to fill holes to planarize the surface of the silicon wafer. The material of the second dielectric layer 8 can be but not limited to borophosphosilicate glass. In this embodiment, the gate contact hole 72 penetrates the second dielectric layer 8 above the gate 6, the source contact hole 71 penetrates the second dielectric layer 8 above the source region 4 on both sides of the trench, and the stop ring contacts The hole 73 penetrates through the second dielectric layer 8 above the stop ring 11 . In another preferred embodiment of the present invention, the gate contact hole 72 penetrates the second dielectric layer 8 above the gate 6 and penetrates deep into the gate 6, and the source contact hole 71 penetrates the source regions 4 on both sides of the trench. The second dielectric layer 8 above and deep into the inside of the source region 4 , and the stop ring contact hole 73 penetrates through the second dielectric layer 8 above the stop ring 11 and goes deep into the inside of the stop ring 11 . In this embodiment, the method for forming the second dielectric layer 8 may be but not limited to chemical vapor deposition, and the method for forming contact holes on the second dielectric layer may be but not limited to wet etching and dry etching. In this embodiment, dry etching is preferably used.

Step 7: Form a metal layer on the surface of the second dielectric layer 8. The method of forming the metal layer can be but not limited to ion beam sputtering or evaporation process, and then perform a third photolithography to etch the metal layer to form a gate For the metal layer 92 , the source metal layer 91 and the stop ring metal layer 94 , specific etching methods may be, but not limited to, wet etching and dry etching. In this embodiment, wet etching is preferably used. The gate metal layer 92 is connected to the gate 6 through the gate contact hole 72, the source metal layer 91 is connected to the well region 4 through the source contact hole 71, and the stop ring 11 is connected to the stop ring metal layer 94 through the stop ring contact hole 73. . In a preferred embodiment of the present invention, the isolation ring 10 is connected to the source metal layer 91 through the interdigitated structure 16 and the source contact hole 71 , and the interdigitated structure 16 and the isolation ring 10 are formed simultaneously by the same steps. In another preferred embodiment of the present invention, the isolation ring 10 is connected to the gate metal layer 92 through the gate contact hole 72 .

Step 8: forming a drain metal layer 93 under the substrate 1 .

According to the preparation method of the trench MOSFET of the present invention, in a preferred embodiment of the present invention, only the trench MOSFET prepared on the n-type substrate is used as an example for illustration, and for the device prepared on the p-type bottom, according to the opposite The type of doping can be doped. The specific steps are as follows: firstly, an n-type lightly doped epitaxial layer 2 is fabricated on an n-type heavily doped substrate 1 . Then, a p-type lightly doped well region 3 and an n-type heavily doped source region 4 are sequentially formed in the epitaxial layer 2 by ion implantation, and the upper surface of the source region 4 is on the same plane as the upper surface of the epitaxial layer 2 . Then, use a mask on the epitaxial layer 2 to coat photoresist, expose and develop the upper surface of the groove to be etched, and use dry etching to etch the cell area and terminal area to form Grooves, the grooves in the terminal area are four closed annular grooves surrounding the cell area. Subsequently, an oxide layer is deposited in the trench by chemical vapor deposition, and a gate oxide layer with a thickness of 800 angstroms is formed after high temperature annealing, and the gate oxide layer is used as the first dielectric layer 5 . Afterwards, polysilicon is deposited on the first dielectric layer 5 in the trench as a filling layer, and the polysilicon forms the gate 6 of the MOSFET. Then, borophosphosilicate glass is deposited as the second dielectric layer 8, the contact hole area is defined on the surface of the second dielectric layer 8 by photolithography, and the contact hole is formed by etching. Subsequently, metal is deposited on the upper surface of the second dielectric layer 8 and the contact hole area by sputtering; the gate metal layer 92 , the source metal layer 91 and the stop ring metal layer 94 are formed by photolithography and etching. Finally, a drain metal layer 93 is formed under the substrate 1 .

The manufacturing method of the trench MOSFET with the terminal withstand voltage structure of the present invention solves the withstand voltage and leakage problems of the trench MOSFET prepared by the three-layer photolithography process without increasing the complexity of the process, and reduces the cost of the trench MOSFET. The lateral leakage improves the withstand voltage of the device, simplifies the process, and reduces the manufacturing cost.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described, those skilled in the art can understand that various changes, modifications, substitutions and modifications can be made to these embodiments without departing from the principle and spirit of the present invention. The scope of the invention is defined by the claims and their equivalents.

Claims (12)

1. A trench MOSFET with a terminal withstand voltage structure, characterized in that it comprises: A substrate and an epitaxial layer formed thereon, the conductivity type of the epitaxial layer is the same as that of the substrate, an active region and a well region are sequentially formed in the epitaxial layer from top to bottom, and the well region The conductivity type of the substrate is opposite to that of the substrate, the conductivity type of the source region is the same as that of the substrate, and the upper surface of the source region is on the same plane as the upper surface of the epitaxial layer; The epitaxial layer is divided into a cell area and a terminal area, the terminal area surrounds the cell area, a gate lead area is formed in the terminal area, and a gate lead area is formed in the cell area and in the terminal area, respectively. There are grooves, the depth of the grooves is greater than the sum of the thicknesses of the source region and the well region, the grooves of the terminal region are at least two closed annular grooves surrounding the cell region, and the annular The grooves are not connected to each other, and along the direction from inside to outside, at least one annular groove close to the cell area is an isolation ring, and the isolation ring is connected to zero potential; A first dielectric layer and a gate are formed in the trench; A second dielectric layer is formed on the epitaxial layer, and a contact hole is formed in the second dielectric layer, and the contact hole includes a gate contact hole, a source contact hole and a stop ring contact hole; A gate metal layer, a source metal layer and a stop ring metal layer are formed on the surface of the second dielectric layer, the gate metal layer is connected to the gate through a gate contact hole, and the source metal layer is connected to the gate through a gate contact hole. a source contact hole is connected to the source region, and the stop ring is connected to the stop ring metal layer through the stop ring contact hole; and A drain metal layer is formed under the substrate. 2. The trench MOSFET with terminal withstand voltage structure as claimed in claim 1, characterized in that, along the direction from outside to inside, at least one annular groove close to the scribe lane is a stop ring, and the stop ring and the scribe lane connect. 3. The trench MOSFET with a terminal withstand voltage structure as claimed in claim 2, wherein the distance between the isolation ring and the gate metal layer is the minimum distance allowed by the photolithography process, and the stop ring and the The distance of the scribe lane is the minimum distance allowed by the photolithography process. 4 . The trench MOSFET with terminal withstand voltage structure according to claim 1 , wherein the isolation ring is connected to the source metal layer through an interdigitated structure and a source contact hole. 5 . The trench MOSFET with terminal withstand voltage structure according to claim 1 , wherein the isolation ring is connected to the gate metal layer through a gate contact hole. 6. The trench MOSFET with a terminal withstand voltage structure as claimed in claim 2, wherein an electric field expansion ring is formed between the isolation ring and the stop ring, and the electric field expansion ring is at least one surrounding the isolation The closed ring grooves of the rings are not connected to each other, and the potential of the electric field expansion ring is suspended. 7. A method for manufacturing a trench MOSFET with a terminal withstand voltage structure, characterized in that, comprising the steps: S1: provide the substrate; S2: Form an epitaxial layer on the substrate, the conductivity type of the epitaxial layer is the same as that of the substrate, and sequentially form a well region and a source region in the epitaxial layer, the conductivity type of the well region Contrary to the conductivity type of the substrate, the conductivity type of the source region is the same as the conductivity type of the substrate, and the upper surface of the source region is on the same plane as the upper surface of the epitaxial layer; S3: dividing the epitaxial layer to form a cell area and a terminal area, the terminal area surrounds the cell area, the terminal area includes a gate lead area, and trenches are formed in the cell area and the terminal area, The depth of the groove is greater than the sum of the thicknesses of the source region and the well region, and the groove in the termination region is at least two closed annular grooves surrounding the cell region, and the annular grooves are not separated from each other. connected, along the direction from inside to outside, at least one annular groove close to the cell region is an isolation ring, the isolation ring is connected to zero potential, and a first dielectric layer and a gate are formed in the groove, A second dielectric layer is formed on the epitaxial layer and the trench, and a contact hole is formed on the second dielectric layer, the contact hole includes a gate contact hole, a source contact hole and a stop ring contact hole. A gate metal layer, a source metal layer and a stop ring metal layer are formed on the surface of the second dielectric layer, the gate metal layer is connected to the gate through a gate contact hole, and the source metal layer is connected to the gate through a source The contact hole is connected to the source region, and the stop ring is connected to the stop ring metal layer through the stop ring contact hole; S4: forming a drain metal layer under the substrate. 8. The method for manufacturing a trench MOSFET with a terminal withstand voltage structure as claimed in claim 7, wherein said step S3 comprises the following steps: S31: Lithographically and etch the cell region and the terminal region on the epitaxial layer to form a groove, the depth of the groove is greater than the sum of the thicknesses of the source region and the well region, and the groove of the terminal region The grooves are at least two closed annular grooves surrounding the cell region; S32: Form a first dielectric layer along the inner surface of the trench, form a gate on the first dielectric layer in the trench, and fill the trench with the gate; S33: Form a second dielectric layer on the epitaxial layer and the trench, perform photolithography, etch the second dielectric layer to form a contact hole, and the contact hole includes a gate contact hole, a source contact hole and a stopper ring contact hole; S34: forming a metal layer on the surface of the second dielectric layer, and performing photolithography to form a gate metal layer, a source metal layer and a stop ring metal layer, and the gate metal layer is connected to the gate through a gate contact hole , the source metal layer is connected to the well region through a source contact hole, and the stop ring is connected to the stop ring metal layer through a stop ring contact hole. 9. The method for manufacturing a trench MOSFET with terminal withstand voltage structure as claimed in claim 7 or 8, characterized in that, along the direction from outside to inside, at least one annular groove close to the scribe lane is a stop ring, said The stop ring is connected to the scribe lane. 10. The method for manufacturing a trench MOSFET with a terminal withstand voltage structure according to claim 7 or 8, wherein the isolation ring is connected to the source metal layer through an interdigitated structure and a source contact hole. 11. The method for manufacturing a trench MOSFET with a voltage-resistant terminal structure according to claim 7 or 8, wherein the isolation ring is connected to the gate metal layer through a gate contact hole. 12. The method for manufacturing a trench MOSFET with a terminal withstand voltage structure as claimed in claim 9, wherein an electric field extension ring is formed between the isolation ring and the stop ring, and the electric field extension ring is at least one The ring grooves surrounding the isolation ring are not connected to each other, and the potential of the electric field extension ring is suspended.