CN103811408B - A kind of deep silicon etching method for forming through hole - Google Patents

Abstract

The invention provides a deep-hole silicon etching method. The silicon wafer to be processed is placed in a plasma processing chamber, the surface of the silicon wafer includes a patterned mask layer, and a first reaction gas is introduced to etch the silicon wafer to form a The undercut feature opens to a first depth. Then enter the main etching stage of alternately performing etching and sidewall protection, and form sidewalls with substantially vertical sidewall morphology after the main etching stage is completed.

Description

A deep silicon via etching method

technical field

The invention relates to the field of plasma processing, in particular to a deep hole silicon etching method to obtain better sidewall morphology.

Background technique

In the field of semiconductor manufacturing technology, in the fields of MEMS (Micro-Electro-Mechanical Systems, micro-electro-mechanical systems) and 3D packaging technology, it is usually necessary to etch deep via holes in materials such as silicon. For example, in crystalline silicon etching technology, deep through silicon vias (Through-Silicon-Via, TSV) have a depth of hundreds of microns, and their aspect ratio is even much greater than 10, and are usually etched by deep reactive ion etching. Bulk silicon is formed. Said silicon material is mainly monocrystalline silicon. After the etching is completed, conductive materials such as copper are filled into the holes or grooves formed by etching. The filling method can be chemical vapor deposition (CVD) or physical vapor deposition (PVD) process. Since the above-mentioned deposited copper material is deposited from top to bottom, the optimal shape of the opening of the TSV hole formed by etching requires a trapezoidal opening, or an opening with vertical sidewalls.

The existing typical etching technology uses alternate etching-deposition steps to rapidly etch silicon, and this etching method is also called Bosch etching method. When the bosch etching method is used for etching, the sidewall of the formed hole is slightly bowed. As shown in the cross-sectional view of Figure 1a, the holes formed by etching are smaller in diameter at the upper and lower ends than in the middle section. The enlarged view of the uppermost opening is shown in Figure 1b. The structure of the etching material layer includes: a mask layer 10 (such as photoresist PR), and below the mask layer 10 is a crystalline silicon material layer 20 to be etched. Holes 200 are formed. Such an opening structure is not conducive to the deposition of conductive materials in the next step. The smaller opening sidewalls above will block the further deposition of conductive materials in the holes below. It is likely that there will still be cavities in the holes after the step of filling the holes with conductive materials. The existence of these cavities will not only deteriorate the conductive characteristics, but even cause disconnection of the lines that need to be conducted. This unfavorable sidewall morphology cannot be eliminated by adjusting the adjustable parameters in the traditional Bosch etching method. This causes the holes formed by the traditional Bosch etching method to cause problems in subsequent processing, and eventually leads to the discarding of the entire product, resulting in great waste and loss. Therefore, the industry needs a simple and effective etching method to improve the deep hole silicon etching method.

Contents of the invention

The purpose of the present invention is to provide a deep hole silicon etching method to make the hole morphology formed by etching more suitable for subsequent filling of conductive materials. The deep-hole silicon etching method is used to etch a silicon substrate, and the silicon substrate includes a patterned mask layer, and the etching method includes: a first etching stage, using the patterned mask layer The film layer etches the silicon substrate to form an opening with a first depth, and the distance between the sidewalls on both sides of the opening gradually decreases from the top down, and enters the main etching stage after the first etching stage is completed. The main etching stage includes alternate etching and deposition steps. In the etching step, an etching gas is fed to etch the silicon substrate. For protection, the main etching stage etches the silicon substrate from the first depth to a second depth while increasing the sidewall spacing at the first depth.

Wherein the patterned mask layer has a first critical dimension, and after completing the main etching stage, the mask layer has a second critical dimension, the second critical dimension is larger than the first critical dimension, and the first critical dimension The size is selected from 4-6um, and the second critical dimension is selected from 7-8um.

The etching gas in the first etching stage includes SF6, C4F8, O2. The distance between the upper end sidewalls of the opening of the first depth is larger than the first critical dimension.

Wherein said second etching depth in the main etching stage is greater than 30um. The etching gas introduced in the etching step in the main etching stage is selected from one of SF6 and NF3.

The sidewall spacing of the opening at the first depth is less than 1.1 times the spacing between the sidewalls at the upper end of the opening, wherein the first depth is greater than 1 um and less than 6 um.

Description of drawings

Fig. 1a is an overall schematic cross-sectional view of deep TSVs formed by etching in the prior art;

Fig. 1b is a partially enlarged schematic diagram of the upper end of a deep TSV formed by etching in the prior art;

Fig. 2 is a partially enlarged schematic diagram of the upper end of the deep TSV formed in the middle of the etching process by using the etching method provided by the present invention;

3 is a partially enlarged schematic diagram of the upper end of the deep TSV when the etching is completed using the etching method provided by the present invention;

Fig. 4 is a partial cross-sectional view of the upper end of the deep through-silicon via when the etching method provided by the present invention is used to complete the etching.

detailed description

The present invention will be described in detail below through preferred specific embodiments with reference to FIG. 2 to FIG. 4 .

As shown in Figure 2, compared with the prior art, the present invention first performs pre-correction etching of the sidewall topography during the etching process, and etches to form an undercut topography (undercut) before performing subsequent deep hole silicon etching. ), the undercut has a suitable size, and lateral etching with a certain depth is formed on both sides of the hole on the lower surface of the mask layer. The mask layer 10 has a distance D1 at the sidewall of the opening, that is, the CD dimension of the mask layer at this time is D1, and the upper end of the hole formed by etching, that is, the distance between the sidewalls on both sides of the opening close to the mask layer is D20, wherein D20 is greater than D1. The specific value of D20 greater than D1 can be adjusted according to the overall processing technology, and the difference between D20-D1 is at least greater than 1um to ensure that the offset of the morphology formed in the subsequent etching can be compensated. For example, the difference between D20-D1 can be greater than 1um and less than 6um, and the optimal value can be 2-4um. The selection of the depth is appropriate to offset the depth of the opening protruding from the bowing sidewall topography formed in the subsequent main etching stage. After the etching of the undercut topography is completed, an opening with a certain depth is formed on the silicon substrate. This depth can be selected by adjusting the etching process according to the needs. Generally, it must be large enough such as greater than 2um. The formed opening contacts the mask at the upper end. The distance between the sidewalls on both sides of the layer is greater than the opening distance of the upper mask layer. The distance between the sidewalls on both sides of the opening decreases gradually from top to bottom, and there is a first distance D21 at the first depth H1 near the bottom. A variety of etching processes can be used when etching to form an undercut shape, mainly using SF6 as the etching gas, or NF3 and other etching gases, and other fluorocarbons such as C4F8 and O2 as auxiliary etching gases. For example, if the above gas is used at a pressure of 50 mTorr, 1000 sccm of SF6 gas, 150 sccm of C4F8 gas and 50 sccm of O2 gas are introduced into the reaction chamber, and the plasma is ignited after the above reaction gas is introduced into the reaction chamber, and the plasma shown in Figure 2 can be formed for 10 seconds. undercut shape. In addition to the above etching process, many other etching processes can be used to form the undercut morphology such as: (1) The gas pressure is set to 100mT, and 500 sccm of SF6 gas and 920 sccm of O2 are fed into 200 sccm of C4F8 at the same time The gas lasts for 15 seconds; (2) the air pressure is 150mt, and 1500sccm of SF6 gas, 800sccm of C4F8 gas and 600sccm of O2 are introduced for 15 seconds; (3) the pressure of 150mT is maintained, and 500sccm of SF6, 800sccm of O2 and 900sccm of C4F8 was maintained for 15s.

After forming the undercut topography shown in Figure 2, enter the main etching step, use the traditional deep through silicon via etching method such as Bosch etching method to etch downward, alternately use etching gas downward, etc. The tropism is etched to a certain depth, and then the sidewall of the hole formed by the entire etching is protected with fluorocarbon, and then enters the next etching-sidewall protection cycle until the etching reaches the required depth. The etching and deposition steps can be completed alternately within 2 seconds to reduce the roughness of the sidewall. The sidewall of the hole 200 in FIG. 2 actually includes a large number of alternately concave and convex tiny stripes formed by alternate etching, which are not shown in the figure because it does not affect the method of the present invention. As shown in Figure 2, in the process of etching the underlying silicon with the photoresist as a mask, the pattern opening distance on the photoresist is etched downward from the initial D1, which is the critical dimension D1 (critical dimension), due to the process It is necessary that during the downward etching process, the opening distance needs to gradually increase to D2 in the final etching completion state as shown in FIG. 3 . D1 can be 5um at the beginning, and D2 can be 7um when the etching is completed. This requires that the polymer deposition layer formed on the mask layer 10 surface during the etching process can not be too thick, so the C4F8 in the etching gas The gas content cannot be very high. While the polymer layer on the surface of the mask layer 10 is not thick, the polymer layer protecting the sidewalls of the holes formed by etching is also not very thick, so part of the sidewalls may be etched. During the process of etching extending downward from the upper opening of the hole 200 , the distance of the upper opening of the mask layer also gradually extends from D1 to D2 . This will cause the opening of the mask to be small when etching the upper silicon material layer, so the diameter of the hole formed by the corresponding etching will be smaller, and the opening of the mask will become larger when further etching is performed subsequently, and the diameter of the hole formed accordingly will become larger. Finally, the desired sidewall morphology with a small diameter of the upper opening and a larger diameter of the lower opening is formed during the etching process. After applying the method of the present invention, due to the pre-correction of the sidewall topography, the opening of the undercut topography shown in Figure 2 is formed, so the main etching step is at the first depth H1 shown in Figure 2 Etching down is started, and the sidewall spacing at the first depth is still D21 at the beginning of etching. As the etching proceeds until the entire etching is completed at the second depth. Since the critical dimension of the upper mask layer becomes larger during the long-term etching process, bowing sidewalls still appear in the main etching stage. The undercut topography formed in one-step etching compensates each other, until the etching is completed, the sidewall spacing at the first depth reaches D22, D22 is greater than the aforementioned D21, and D22 is close to the size of the upper and lower sidewall spacing . Therefore, the overall shape of the side wall of the opening is basically vertically downward, which will not cause a negative effect on the subsequent deposition steps. Since the above arc-shaped sidewall morphology is gradually formed, it will be more obvious only when the etching depth is sufficiently large. The etching depth of the present invention can reach greater than 100um, or even greater. Of course, when the depth is greater than 30um, the above-mentioned arc-shaped sidewall can be observed, and the invention can also be applied to solve the problem of incomplete filling in the subsequent filling stage by adjusting the etching process parameters.

As shown in FIG. 3, it is a schematic diagram of the structure when the etching is completed using the present invention. Fig. 4 is a cross-sectional view of a material layer etched by actually applying the method of the present invention. From Fig. 3 or 4, it can be seen that the traditional etching is carried out after the first step is performed to form the undercut shape, and then the superposition of the two effects on the silicon material layer 200 can eliminate the inward extension of the opening end of the etching hole 200 in the prior art. This prevents the formation of cavities in the filling material during the subsequent conductive material filling process. Since the step of forming the undercut etching adopts the traditional deep-hole silicon etching gas, and the time is very short, only about 10 seconds, and there is no additional requirement compared with the existing system hardware, so the present invention can be used basically without A simple method is used to correct the sidewall topography at the expense of additional cost and time.

The present invention can be applied to a capacitive coupling (CCP) type plasma processing device or an inductive coupling type (ICP) plasma processing device

Although the content of the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description should not be considered as limiting the present invention. Various modifications and alterations to the present invention will become apparent to those skilled in the art upon reading the above disclosure. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (9)

1. a deep hole silicon etching method, is used for etching silicon chip, described silicon chip includes one patterned covers Film layer, described lithographic method includes

First etch stages, forms first with described patterned mask layer for mask etching silicon chip deep The opening of degree (H1), the spacing of described opening both sides sidewall is gradually reduced from top down, and First depth has the first side wall spacing (D21),

Terminate laggard etch stages of becoming owner of in the first etch stages, the described main etching stage include replacing into The etching of row and deposition step, be passed through etching gas in etch step and perform etching silicon chip, Deposition step is passed through fluorocarbon gases the opening sidewalls of etching formation is protected, described master Etch stages, described opening to second degree of depth, makes described first deep from described first deep etching simultaneously The first side wall spacing at degree increases to the second spacing (D22)；

Described patterned mask layer has the first critical size in the first etch stages, completes main quarter After the erosion stage, described mask layer has the second critical size, and described second critical size is more than described first Critical size.

2. lithographic method as claimed in claim 1, it is characterised in that the etching gas of described first etch stages Body includes SF6, C4F8, O2.

3. lithographic method as claimed in claim 1, it is characterised in that the of described main etching stage etching Two degree of depth are more than 30um.

4. lithographic method as claimed in claim 1, it is characterised in that the etching step in the described main etching stage Suddenly the etching gas being passed through is selected from one of SF6 and NF3.

5. lithographic method as claimed in claim 1, it is characterised in that described first etch stages formed the Spacing (D20) between one degree of depth open upper end sidewall is more than described first critical size (D1) 1um Above.

6. lithographic method as claimed in claim 1, it is characterised in that described first etch stages formed the Spacing between one degree of depth open upper end sidewall is more than described first critical size, and difference is more than 1um Less than 6um.

7. lithographic method as claimed in claim 1, it is characterised in that described first critical size is selected from 4-6um, Second critical size is selected from 7-8um.

8. lithographic method as claimed in claim 1, it is characterised in that the hypomere side of described first degree of depth opening Wall is smaller than the spacing between the open upper end sidewall of 1.1 times.

9. lithographic method as claimed in claim 1, it is characterised in that described first degree of depth is more than 2um.