CN103761456B - A kind of anti-method cracking of monolithic microcomputer kernel code - Google Patents

Abstract

The invention discloses a method for preventing cracking of the core code of a single-chip microcomputer. It comprises the following steps: in the single-chip microcomputer execution code process, when executing to the specific storage area where the ciphertext code is located, the MPU memory protection module generates an interrupt, and in the interrupt, the ciphertext code is decrypted into a plaintext code by the AES module, CRC After the verification is correct, the plaintext code is returned to the specific storage area, the interrupt returns, and the MCU executes the plaintext code in the specific storage area. After the code is executed, the AES module encrypts the plaintext code in the specific storage area into a ciphertext code, and the CRC check After being correct, return the ciphertext code to a specific storage area. The invention enables the core code in the single-chip microcomputer to exist in the form of cipher text, even if the cracker uses an intrusive method to crack the single-chip microcomputer and reads the core code in the single-chip microcomputer, the core code in the form of cipher text cannot be translated into plain text, thereby protecting core code.

Description

A method for anti-cracking of single-chip microcomputer core code

technical field

The invention relates to the technical field of code protection of single-chip microcomputers, in particular to a method for preventing cracking of core codes of single-chip microcomputers.

Background technique

Now there are endless cracking technologies for single-chip microcomputers on the market, and there are mainly two methods: non-intrusive and immersion. The non-intrusive method is to crack the chip by exploiting certain loopholes in the chip design or chip programming sequence. Of course, with the development of the chip design industry, such situations will become less and less. The intrusive way is to destroy the package of the chip, use semiconductor testing equipment, microscopes and micropositioners and other instruments to find the position of the chip protection fuse and repair it, making it an unencrypted chip, and then use a special programmer to reset Program reading, or directly put the probe on the internal bus of the chip to read the program in the memory.

Chinese Patent Publication No. CN1971470A, published on May 30, 2007, the name of the invention is a system encryption method using a multi-purpose auxiliary single-chip microcomputer, the application discloses a system encryption method using a multi-purpose auxiliary single-chip microcomputer, which is In a multi-bit processor system, the auxiliary microprocessor with relatively simple functions and small software programs is replaced by a single-chip microcomputer with a built-in burn-out program memory, and a password according to the agreed encryption protocol algorithm is added to the main processor program and the auxiliary single-chip computer program. Verification, so that the program cannot be read and cannot be copied, so as to achieve the purpose of system encryption. Its shortcoming is that the code in the single-chip microcomputer is a clear code, and the cracker can crack it in an intrusive way to read the plain text code in the single-chip microcomputer, thereby restoring it to a high-level language and mastering the core technology.

Contents of the invention

The purpose of the present invention is to overcome the technical problem that the current single-chip microcomputer is easily cracked by an intrusive method, and provides a method for preventing the core code of the single-chip microcomputer from cracking, which makes the core code in the single-chip microcomputer exist in the form of cipher text, even if the cracker uses an intrusive method The method cracked the single-chip microcomputer, and the core code in the single-chip microcomputer was read out, and the core code in the form of cipher text could not be translated into plain text, thereby protecting the core code.

In order to solve the above problems, the present invention adopts the following technical solutions to achieve:

A kind of anti-cracking method of single-chip microcomputer core code, described single-chip microcomputer has MPU memory protection module, AES file acceleration module, DMA module and CRC module, comprises the following steps:

S1: Initially encrypt the core code that needs to be protected in the microcontroller in advance, encrypt the core code into a ciphertext code through the AES encryption algorithm, and back up the ciphertext code at the same time, and the backup ciphertext code is stored in the non-volatile memory of the microcontroller on memory;

S2: During the execution of the code by the single-chip microcomputer, when the specific storage area where a piece of ciphertext code is executed, the MPU memory protection module generates an interrupt;

S3: The code currently executed by the MCU enters an interrupt, and the DMA module transfers the ciphertext code to the designated area on the volatile memory of the MCU, and the AES file acceleration module decrypts the ciphertext code in the designated area into a plaintext code, and the CRC module checks the Verify the plaintext code, if the verification is wrong, then perform step S4, if the verification is correct, then perform step S5;

S4: The original ciphertext code remains unchanged, and the DMA module will not return the plaintext code to the specific storage area where the original ciphertext code is located. The code currently executed by the microcontroller is always interrupted, and the interrupt cannot return;

S5: The DMA module returns the plaintext code to the specific storage area where the original ciphertext code is located to cover the original ciphertext code. After all the plaintext codes are returned, the interrupt returns, and the single-chip microcomputer executes the plaintext code;

S6: After the plaintext code is executed, the DMA module transfers the plaintext code to the specified area on the volatile memory of the single-chip microcomputer, and the AES file acceleration module encrypts the plaintext code in the specified area into a ciphertext code, and the CRC module verifies the ciphertext code, if the verification is wrong, step S7 is executed, and if the verification is correct, step S8 is executed;

S7: The DMA module transfers the backup ciphertext code to the specific storage area where the original ciphertext code is located to cover the plaintext code. After the ciphertext code is transmitted, the single-chip microcomputer executes the following code;

S8: The DMA module returns the ciphertext code to the specific storage area where the original ciphertext code is located to cover the plaintext code. After all the ciphertext codes are returned, the single-chip microcomputer executes the following code;

In the process of executing steps S2 to S8, if the stand-alone chip is powered off, the DMA module will transfer the backup ciphertext code to the specific storage area where the original ciphertext code is located, and overwrite the current code in the specific storage area.

In this technical solution, MPU (MemoryProtectionUnit; memory protection unit) memory protection module: can configure specific area memory read, write and code execution, when single-chip microcomputer chip executes the ciphertext core code of specific area, MPU produces an interruption. AES (Advanced Encryption Standard; Advanced Encryption Standard) file acceleration module: AES file acceleration module can easily calculate the AES algorithm, greatly reducing the time of AES encryption/decryption, AES can use 128/192/256bits key. DMA (DirectMemoryAccess; direct memory access unit) module: a data transmission module that can transmit data while the CPU is sleeping, reducing power consumption and data transmission time. CRC (CyclicRedundancyCheck; Cyclic Redundancy Check Code) module: a data verification module that can verify the data encrypted/decrypted by the AES module.

During the whole process of the operation of the single-chip microcomputer chip, the core code exists in the form of ciphertext code most of the time. Only when it is executed, the decryption and verification are correct, the plaintext code will appear, and the plaintext code is executed. After that, it will be re-encrypted into a ciphertext code, and the plaintext code appears for a very short time. Even if competitors use the immersion method to obtain the binary code of the single-chip microcomputer, the core code we want to protect in the binary code is an encrypted ciphertext code, and the competitor cannot restore the source code to get the core code we want to protect, the value of chip cracking Greatly reduced.

In the process of performing steps S2 to S8, if the single-chip microcomputer is powered off, the specific storage area where the original ciphertext code is located may retain all plaintext codes or a part of plaintext codes, which will cause data confusion and make the single-chip microcomputer unable to run normally next time. There is a risk of the code being cracked and read out. Therefore, when the single-chip microcomputer is powered off, the backup ciphertext code is transferred to the specific storage area where the corresponding original ciphertext code is located, and the current code in the specific storage area is overwritten to prevent power failure in the plaintext stage of the specific storage area from causing data loss. Confused.

As preferably, the core code is divided into several sections before the initial encryption of the core code in the step S1, and the data length of each section of the core code is 0 to 1024bytes, and then each section of the core code is encrypted into ciphertext by the AES encryption algorithm code. Whenever a specific storage area where a piece of ciphertext code is located is executed, the MPU memory protection module generates an interrupt, and then steps S3 to S8 are executed. Control the data length of each core plaintext code within 1024bytes. Since the ciphertext code is the same as the corresponding plaintext code data length, the data length of the ciphertext code is also within 1024bytes, so that the single-chip computer executes the plaintext code and encrypts and decrypts the plaintext code every time. The time is very short, thereby reducing the time that each plaintext code exists, increasing the difficulty of cracking, and improving the security of the core code. At the same time, even if the data length of the core code is long, the volatile memory for temporarily storing the plaintext code and the ciphertext code does not need to be too large.

As preferably, the initial encryption of the core code in the single-chip microcomputer in the step S1 includes the following steps: use the computer host computer to encrypt the plaintext core code in the single-chip microcomputer code into a ciphertext code through the AES encryption algorithm, and transmit the ciphertext code to the single-chip microcomputer binary The storage area where the plaintext core code is located in the burning file will cover the plaintext core code, and at the same time add the plaintext CRC key and ciphertext CRC key generated by the computer host computer to the single chip binary burning file.

Preferably, in the step S6, after the DMA module transfers the plaintext code to the specified area on the volatile memory of the single-chip microcomputer, clear the plaintext code on the specific storage area where the original ciphertext code is located. Reduce the existence time of a piece of plaintext code, increase the difficulty of cracking, and improve the security of the core code.

Preferably, the AES document acceleration module uses a 256bits key.

The substantive effects of the present invention are: (1) make the core code in the single-chip microcomputer exist in the form of ciphertext, even if the cracker uses an intrusive method to crack the single-chip microcomputer, the core code in the single-chip microcomputer is read out, and the ciphertext form cannot be read out. The core code is translated into plain text, thus protecting the core code. (2) The core code is divided into several sections, and the data length of each section of core code is 0 to 1024bytes, so that the single-chip microcomputer executes the plaintext code and encrypts and decrypts the plaintext code each time. The time is shorter, thereby reducing the time that each section of plaintext code exists. It increases the difficulty of cracking and improves the security of the core code.

Description of drawings

Fig. 1 is a kind of flowchart of the present invention.

detailed description

The technical solutions of the present invention will be further specifically described below through the embodiments and in conjunction with the accompanying drawings.

Embodiment: the anti-cracking method of a kind of single-chip microcomputer core code of the present embodiment, single-chip microcomputer has MPU memory protection module, AES convenient document acceleration module, DMA module and CRC module, as shown in Figure 1, comprises the following steps:

S1: Divide the plaintext core code in the single-chip microcomputer into several pieces of plaintext code in advance. The data length of each piece of plaintext code is 0 to 1024bytes. Use the computer host computer to encrypt each piece of plaintext code into ciphertext code through AES encryption algorithm, and convert each piece of plaintext code into ciphertext code. A section of ciphertext code is transmitted to the storage area corresponding to a section of plaintext code in the microcontroller, and the corresponding section of plaintext code is covered, and the plaintext CRC key and ciphertext CRC key are sent to the microcontroller, and these ciphertext codes are transmitted to the non- The backup storage area of the volatile memory for backup;

S2: During the code execution process of the single-chip microcomputer, when a specific storage area where a section of ciphertext code is executed (the first address of the storage area of the ciphertext code), the MPU memory protection module generates an interrupt;

S3: The code currently executed by the MCU enters an interrupt, and the DMA module transfers the ciphertext code to the designated area on the volatile memory of the MCU, and the AES file acceleration module decrypts the ciphertext code in the designated area into a plaintext code, and the CRC module checks the Verify the plaintext code, if the verification is wrong, then perform step S4, if the verification is correct, then perform step S5;

S4: The original ciphertext code remains unchanged, the DMA module will not return the plaintext code to the specific storage area where the original ciphertext code is located, the decrypted plaintext code remains in the specified area on the volatile memory, The code is always interrupted, the interrupt cannot return, and the microcontroller cannot work normally;

S5: The DMA module returns the plaintext code to the specific storage area where the original ciphertext code is located to cover the original ciphertext code, and the original ciphertext code is completely cleared. After all the plaintext codes are returned, the interrupt returns, and the single-chip microcomputer executes the plaintext code;

S6: After the plaintext code is executed, the DMA module transfers the plaintext code to the specified area on the volatile memory of the single-chip microcomputer. After the transmission is completed, the plaintext code on the specific storage area where the original ciphertext code is located is cleared, and the AES file acceleration module will The plaintext code in the specified area is encrypted into a ciphertext code, and the CRC module verifies the ciphertext code. If the verification is wrong, then perform step S7, and if the verification is correct, then perform step S8;

S7: The DMA module transfers the backup ciphertext code to the specific storage area where the original ciphertext code is located to cover the plaintext code. After the ciphertext code is transmitted, the single-chip microcomputer executes the following code;

S8: The DMA module returns the ciphertext code to the specific storage area where the original ciphertext code is located to cover the plaintext code. After all the ciphertext codes are returned, the single-chip microcomputer executes the following code;

In the process of executing steps S2 to S8, if the stand-alone chip is powered off, the DMA module will transfer the backup ciphertext code to the specific storage area corresponding to the original ciphertext code to overwrite the current code in the specific storage area.

MPU (MemoryProtectionUnit; memory protection unit) memory protection module: can configure specific area memory reading, writing and code execution, when the single-chip microcomputer chip executes the ciphertext core code of a specific area, the MPU generates an interrupt. AES (Advanced Encryption Standard; Advanced Encryption Standard) file acceleration module: AES file acceleration module can easily calculate the AES algorithm, greatly reducing the time of AES encryption/decryption, AES can use 128/192/256bits key. DMA (DirectMemoryAccess; direct memory access unit) module: a data transmission module that can transmit data while the CPU is sleeping, reducing power consumption and data transmission time. CRC (CyclicRedundancyCheck; Cyclic Redundancy Check Code) module: a data verification module that can verify the data encrypted/decrypted by the AES module.

During the whole process of the operation of the single-chip microcomputer chip, the core code exists in the form of ciphertext code most of the time. Only when it is executed, the decryption and verification are correct, the plaintext code will appear, and the plaintext code is executed. After that, it will be re-encrypted into a ciphertext code, and the plaintext code appears for a very short time. Even if competitors use the immersion method to obtain the binary code of the single-chip microcomputer, the core code we want to protect in the binary code is an encrypted ciphertext code, and the competitor cannot restore the source code to get the core code we want to protect, the value of chip cracking Greatly reduced.

In this embodiment, the main frequency of the single-chip microcomputer is 8MHz, the AES acceleration module adopts a 256bits key, and the data length of the core code of the single-chip microcomputer to be protected is 2304bytes. In step S1, it is divided into 5 sections of plaintext codes. The data lengths of the 5 sections of plaintext codes are 512bytes, 512bytes, 512bytes, 512bytes, and 256bytes respectively. The data length of each section of plaintext code does not exceed 512bytes. The data length of the plaintext code is the same, so the data length of each ciphertext code does not exceed 512bytes.

In the case that the main frequency of the single-chip microcomputer is 8MHz, and the AES file acceleration module adopts a 256bits key, for a code with a data length of 512bytes: the decryption time is 1.35ms, the encryption time is 1.35ms, and the code execution time is 0.1ms. The single-chip microcomputer executes the plaintext code and encrypts and decrypts the plaintext code every time for a very short time, thereby reducing the existence time of each plaintext code, increasing the difficulty of cracking, and improving the security of the core code. At the same time, even if the data length of the core code is long, the volatile memory for temporarily storing the plaintext code and the ciphertext code does not need to be too large.

In the process of performing steps S2 to S8, if the single-chip microcomputer is powered off, the specific storage area where the original ciphertext code is located may retain all plaintext codes or a part of plaintext codes, which will cause data confusion and make the single-chip microcomputer unable to run normally next time. There is a risk of the code being cracked and read out. Therefore, when the single-chip microcomputer is powered off, the backup ciphertext code is transferred to the specific storage area where the corresponding original ciphertext code is located, and the current code in the specific storage area is overwritten to prevent power failure in the plaintext stage of the specific storage area from causing data loss. Confused.

Claims (4)

1. a single-chip microcomputer core code anti-cracking method, said single-chip microcomputer has MPU memory protection module, AES hardware acceleration module, DMA module and CRC module, it is characterized in that, may further comprise the steps: S1: Initially encrypt the core code that needs to be protected in the microcontroller in advance, encrypt the core code into a ciphertext code through the AES encryption algorithm, and back up the ciphertext code at the same time, and the backup ciphertext code is stored in the non-volatile memory of the microcontroller on memory; S2: During the execution of the code by the microcontroller, when the execution reaches a specific storage area where a piece of ciphertext code is located, the MPU memory protection module generates an interrupt; S3: The code currently executed by the MCU enters an interrupt, the DMA module transfers the ciphertext code to the designated area on the volatile memory of the MCU, the AES hardware acceleration module decrypts the ciphertext code in the designated area into a plaintext code, and the CRC module checks Plain text code, if the verification is wrong, then execute step S4, if the verification is correct, then execute step S5; S4: The original ciphertext code remains unchanged, and the DMA module will not return the plaintext code to the specific storage area where the original ciphertext code is located. The code currently executed by the MCU is always interrupted, and the interrupt cannot return; S5: The DMA module returns the plaintext code to the specific storage area where the original ciphertext code is located to overwrite the original ciphertext code. After all the plaintext codes are returned, the interrupt returns, and the microcontroller executes the plaintext code; S6: After the plaintext code is executed, the DMA module transfers the plaintext code to the specified area on the volatile memory of the microcontroller, the AES hardware acceleration module encrypts the plaintext code in the specified area into a ciphertext code, and the CRC module verifies the ciphertext code , if the verification is wrong, step S7 is executed, and if the verification is correct, step S8 is executed; S7: The DMA module transfers the backup ciphertext code to the specific storage area where the original ciphertext code is located to overwrite the plaintext code. After the ciphertext code is transmitted, the MCU executes the following code; S8: The DMA module returns the ciphertext code to the specific storage area where the original ciphertext code is located to overwrite the plaintext code. After all the ciphertext codes are returned, the MCU executes the following code; In the process of executing steps S2 to S8, if the stand-alone chip is powered off, the DMA module will transfer the backup ciphertext code to the specific storage area where the original ciphertext code is located to overwrite the current code in the specific storage area; In the step S1, before the initial encryption of the core code, the core code is divided into several sections, the data length of each section of the core code is 0 to 1024 bytes, and then each section of the core code is encrypted into a ciphertext code through the AES encryption algorithm. 2. the method for anti-cracking of a kind of single-chip microcomputer core code according to claim 1, it is characterized in that, in described step S1, the core code initial encryption in the single-chip microcomputer comprises the following steps: use computer upper computer to convert the plaintext core in the single-chip microcomputer code The code is encrypted into a ciphertext code through the AES encryption algorithm, and the ciphertext code is transmitted to the storage area where the plaintext core code is located in the binary burning file of the microcontroller to cover the plaintext core code, and at the same time, the plaintext CRC key and password generated by the computer host computer are The text CRC key is added to the binary programming file of the microcontroller. 3. according to claim 1 or 2 described a kind of method for anti-cracking of single-chip microcomputer core code, it is characterized in that: in described step S6, after DMA module transfers plaintext code to the specified area on the volatile memory of single-chip microcomputer, Clear the plaintext code on the specific storage area where the original ciphertext code is located. 4. the method for preventing cracking of a kind of single-chip microcomputer core code according to claim 1 or 2, is characterized in that: described AES hardware acceleration module adopts 256bits key.