CN103745999B - Groove power field-effect transistor with insulating buried layer - Google Patents
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- 230000005669 field effect Effects 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/63—Vertical IGFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
- H10D62/107—Buried supplementary regions, e.g. buried guard rings
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Abstract
本发明提供了一种带有绝缘埋层的沟槽栅功率场效应晶体管，包括：源极层和漏极层，所述源极层设置在衬底的第一表面，所述漏极层设置在衬底与第一表面相对的第二表面；掺杂阱层，所述掺杂阱层设置在所述源极层和漏极层之间，且与所述源极层和漏极层贴合，所述源极层和漏极层具有第一导电类型，所述掺杂阱层具有第二导电类型；栅极，所述衬底的第一表面进一步具有一第一沟槽，所述第一沟槽内填充栅介质层，所述栅介质层中进一步具有一第二沟槽，所述栅极设置在所述沟槽内；进一步包括一辅助耗尽层，所述辅助耗尽层设置在所述栅介质层与漏极层在第一沟槽底面的交界处，且在垂直于衬底表面的方向上与所述栅极不交叠，所述辅助耗尽层具有第二导电类型。
The invention provides a trench gate power field effect transistor with an insulating buried layer, comprising: a source layer and a drain layer, the source layer is arranged on the first surface of the substrate, and the drain layer is arranged On the second surface of the substrate opposite to the first surface; a doped well layer, the doped well layer is arranged between the source layer and the drain layer, and is attached to the source layer and the drain layer Combined, the source layer and the drain layer have a first conductivity type, the doped well layer has a second conductivity type; the gate, the first surface of the substrate further has a first groove, the A gate dielectric layer is filled in the first trench, and a second trench is further provided in the gate dielectric layer, and the gate is arranged in the trench; an auxiliary depletion layer is further included, and the auxiliary depletion layer It is arranged at the junction of the gate dielectric layer and the drain layer on the bottom surface of the first trench, and does not overlap with the gate in a direction perpendicular to the substrate surface, and the auxiliary depletion layer has a second conductivity Types of.
Description
技术领域 technical field
本发明涉及半导体器件领域，尤其涉及一种沟槽栅功率场效应晶体管。 The invention relates to the field of semiconductor devices, in particular to a trench gate power field effect transistor.
背景技术 Background technique
绝缘体上硅（SOI）作为一种理想的介质隔离材料，可以有效的实现高、低功率模块, 以及高、低电压器件之间的隔离，彻底消除电干扰，简化器件的结构设计，而且SOI隔离区面积较结隔离小，大大节约了管芯面积，减小了寄生电容，可以方便地集成不同的电路和器件。因此，SOI技术应用于高压器件及功率集成电路具有明显的优势有广泛的应用前景。 Silicon on insulator (SOI), as an ideal dielectric isolation material, can effectively realize the isolation between high and low power modules, as well as high and low voltage devices, completely eliminate electrical interference, simplify the structural design of devices, and SOI isolation The area area is smaller than the junction isolation, which greatly saves the die area, reduces the parasitic capacitance, and can easily integrate different circuits and devices. Therefore, the application of SOI technology to high-voltage devices and power integrated circuits has obvious advantages and broad application prospects.
传统高压器件存在硅极限问题，即比导通电阻与击穿电压2.5次方成正比。超结（Super Junction，SJ）结构打破了“硅极限”，使得器件比导通电阻与击穿电压之间的关系变为导通电阻与击穿电压1.32次方成正比。对于高压器件，器件的比导通电阻等于导通电阻与器件面积的乘积，因此器件面积的大小，对器件的比导通电阻有着至关重要的影响。在横向高压器件，其导通电阻主要由接触电阻、源漏区电阻、沟道电阻、积累区电阻及漂移区电阻构成。较长的漂移区以及其较低的掺杂浓度，使得漂移区电阻在横向高压器件导通电阻中所占的比重较大。沟槽栅技术使得高压器件的沟道区及积累区由横向变为纵向，以缩小沟道区和积累区导致的器件面积的增加。那么如果能使器件的漂移区也实现纵向化，对实现超低比导通电阻的横向高压器件具有较为重要的研究意义。 Traditional high-voltage devices have a silicon limit problem, that is, the specific on-resistance is proportional to the 2.5th power of the breakdown voltage. The Super Junction (SJ) structure breaks the "silicon limit", making the relationship between the specific on-resistance and the breakdown voltage of the device become proportional to the 1.32th power of the on-resistance and the breakdown voltage. For high-voltage devices, the specific on-resistance of the device is equal to the product of the on-resistance and the device area, so the size of the device area has a crucial impact on the specific on-resistance of the device. In lateral high-voltage devices, the on-resistance is mainly composed of contact resistance, source-drain region resistance, channel resistance, accumulation region resistance and drift region resistance. The longer drift region and its lower doping concentration make the resistance of the drift region account for a larger proportion in the on-resistance of the lateral high-voltage device. Trench gate technology makes the channel region and accumulation region of high-voltage devices change from horizontal to vertical, so as to reduce the increase in device area caused by the channel region and accumulation region. Then, if the drift region of the device can also be verticalized, it has important research significance for realizing a lateral high-voltage device with an ultra-low specific on-resistance.
发明内容 Contents of the invention
本发明所要解决的技术问题是，提供一种高性能的沟槽栅功率场效应晶体管。 The technical problem to be solved by the present invention is to provide a high performance trench gate power field effect transistor.
为了解决上述问题，本发明提供了一种带有绝缘埋层的沟槽栅功率场效应晶体管，包括：源极层和漏极层，所述源极层设置在衬底的第一表面，所述漏极层设置在衬底与第一表面相对的第二表面；掺杂阱层，所述掺杂阱层设置在所述源极层和漏极层之间，且与所述源极层和漏极层贴合，所述源极层和漏极层具有第一导电类型，所述掺杂阱层具有第二导电类型；栅极，所述衬底的第一表面进一步具有一第一沟槽，所述第一沟槽内填充栅介质层，所述栅介质层中进一步具有一第二沟槽，所述栅极设置在所述沟槽内；进一步包括一辅助耗尽层，所述辅助耗尽层设置在所述栅介质层与漏极层在第一沟槽底面的交界处，且在垂直于衬底表面的方向上与所述栅极不交叠，所述辅助耗尽层具有第二导电类型。 In order to solve the above problems, the present invention provides a trench gate power field effect transistor with an insulating buried layer, comprising: a source layer and a drain layer, the source layer is arranged on the first surface of the substrate, so The drain layer is arranged on the second surface of the substrate opposite to the first surface; a doped well layer is arranged between the source layer and the drain layer, and is connected to the source layer and the drain layer, the source layer and the drain layer have a first conductivity type, the doped well layer has a second conductivity type; the gate, the first surface of the substrate further has a first A trench, the gate dielectric layer is filled in the first trench, a second trench is further provided in the gate dielectric layer, and the gate is arranged in the trench; an auxiliary depletion layer is further included, the The auxiliary depletion layer is disposed at the junction of the gate dielectric layer and the drain layer on the bottom surface of the first trench, and does not overlap with the gate in a direction perpendicular to the substrate surface, and the auxiliary depletion layer The layer has a second conductivity type.
可选的，所述掺杂阱层在垂直于衬底表面的方向包括由Si1-xGex/Si构成的异质结，其中x大于0且小于1。 Optionally, the doped well layer includes a heterojunction composed of Si 1-x Ge x /Si in a direction perpendicular to the substrate surface, where x is greater than 0 and less than 1.
可选的，所述栅极包括由不同材料构成的第一栅层和第二栅层，所述第一栅层和第二栅层在垂直于衬底表面的方向上堆叠设置；所述第一栅层的材料为N型多晶硅，第二栅层的材料为P型多晶硅 Optionally, the gate includes a first gate layer and a second gate layer made of different materials, and the first gate layer and the second gate layer are stacked in a direction perpendicular to the surface of the substrate; The material of the first gate layer is N-type polysilicon, and the material of the second gate layer is P-type polysilicon
可选的，所述源极层的材料为锗。 Optionally, the material of the source layer is germanium.
可选的，所述第一导电类型为N型，第二导电类型为P型。 Optionally, the first conductivity type is N type, and the second conductivity type is P type.
可选的，所述第一导电类型为P型，第二导电类型为N型。 Optionally, the first conductivity type is P-type, and the second conductivity type is N-type.
本发明的优点在于，在漏极层和栅介质层之间引入辅助耗尽层，在源极层和漏极层之间处于高电压状态时，辅助耗尽层可以漏极层的漂移区进行相互耗尽，起到双重降低表面电场的作用，既可以增大器件的击穿电压，还可以使用更高的漂移区掺杂浓度，降低器件的比导通电阻。 The advantage of the present invention is that an auxiliary depletion layer is introduced between the drain layer and the gate dielectric layer, and when the source layer and the drain layer are in a high voltage state, the auxiliary depletion layer can be depleted in the drift region of the drain layer. Mutual depletion has the effect of double reducing the surface electric field, which can not only increase the breakdown voltage of the device, but also use a higher doping concentration in the drift region to reduce the specific on-resistance of the device.
附图说明 Description of drawings
附图1所示是本发明具体实施方式所述晶体管的结构示意图。 Figure 1 is a schematic structural view of the transistor described in the specific embodiment of the present invention.
附图2是本发明一种另一种具体实施方式的结构示意图。 Accompanying drawing 2 is a structural schematic diagram of another embodiment of the present invention.
具体实施方式 detailed description
下面结合附图对本发明提供的一种带有绝缘埋层的沟槽栅功率场效应晶体管的具体实施方式做详细说明。 The specific implementation of a trench gate power field effect transistor with an insulating buried layer provided by the present invention will be described in detail below with reference to the accompanying drawings.
附图1所示是本发明具体实施方式所述晶体管的结构示意图，包括衬底10中的源极层20、漏极层30、掺杂阱层40、以及栅极50。 FIG. 1 is a schematic structural diagram of a transistor according to a specific embodiment of the present invention, including a source layer 20 , a drain layer 30 , a doped well layer 40 , and a gate 50 in a substrate 10 .
继续参考附图1，所述源极层20设置在衬底10的第一表面，所述漏极层30设置在衬底10与第一表面相对的第二表面。所述掺杂阱层40设置在所述源极层20和漏极层30之间，且与所述源极层20和漏极层30贴合。本具体实施方式中，所述源极层20和漏极层30的导电类型为N型，所述掺杂阱层40的导电类型为P型。在其它的具体实施方式中，上述导电类型也可以互换。 Continuing to refer to FIG. 1 , the source layer 20 is disposed on the first surface of the substrate 10 , and the drain layer 30 is disposed on the second surface of the substrate 10 opposite to the first surface. The doped well layer 40 is disposed between the source layer 20 and the drain layer 30 and bonded to the source layer 20 and the drain layer 30 . In this specific embodiment, the conductivity type of the source layer 20 and the drain layer 30 is N type, and the conductivity type of the doped well layer 40 is P type. In other specific embodiments, the above conductivity types can also be interchanged.
继续参考附图1，所述衬底10的第一表面进一步具有一第一沟槽61，所述第一沟槽61内填充有栅介质层53，所述栅介质层53中进一步具有一第二沟槽62，所述栅极50设置在所述第二沟槽62内。所述源极层20表面具有源电极71，所述漏极层30表面具有漏电极72，所述栅极50表面具有栅电极73，在漏极层30和漏电极72之间还可以进一步包括用于提高欧姆接触效果的欧姆接触层31。在本具体实施方式中，漏极层30的导电类型为N型，欧姆接触层31为N型重掺杂层。上述电极结构用于电学信号的输入与输出。 Continuing to refer to FIG. 1 , the first surface of the substrate 10 further has a first trench 61, the first trench 61 is filled with a gate dielectric layer 53, and the gate dielectric layer 53 further has a first trench 61. The second trench 62 , the gate 50 is disposed in the second trench 62 . The surface of the source layer 20 has a source electrode 71, the surface of the drain layer 30 has a drain electrode 72, the surface of the gate 50 has a gate electrode 73, and may further include Ohmic contact layer 31 for improving the effect of ohmic contact. In this specific embodiment, the conductivity type of the drain layer 30 is N type, and the ohmic contact layer 31 is an N type heavily doped layer. The above electrode structure is used for the input and output of electrical signals.
上述器件是一种垂直结构的晶体管。在栅极50上施加电压，使掺杂阱层40在靠近栅介质层53的表面发生反型，形成导电沟道，将源极层20和漏极层30导通，从而实现器件的开关特性。在本具体实施方式中，进一步包括一辅助耗尽层80，所述辅助耗尽层80设置在所述栅介质层53与漏极层30在第一沟槽61底面的交界处，且在垂直于衬底10表面的方向上与所述栅极50不交叠。所述辅助耗尽层80具有第二导电类型，即与漏极层30的导电类型不同。辅助耗尽层80在垂直于衬底10表面的方向上与所述栅极50不交叠的意义在于防止栅极50上电学信号对辅助耗尽层80的耗尽状态产生影响。在源极层20和漏极层30之间处于高电压状态时，辅助耗尽层80可以漏极层30的漂移区进行相互耗层尽，起到双重降低表面电场的作用，既可以增大器件的击穿电压，还可以使用更高的漂移区掺杂浓度，降低器件的比导通电阻。 The above device is a vertically structured transistor. Applying a voltage to the gate 50 causes the inversion of the doped well layer 40 on the surface close to the gate dielectric layer 53 to form a conductive channel and conduct the source layer 20 and the drain layer 30, thereby realizing the switching characteristics of the device . In this specific embodiment, an auxiliary depletion layer 80 is further included, and the auxiliary depletion layer 80 is disposed at the junction of the gate dielectric layer 53 and the drain layer 30 on the bottom surface of the first trench 61, and vertically It does not overlap with the gate 50 in the direction of the surface of the substrate 10 . The auxiliary depletion layer 80 has a second conductivity type, which is different from that of the drain layer 30 . The meaning that the auxiliary depletion layer 80 does not overlap with the gate 50 in the direction perpendicular to the surface of the substrate 10 is to prevent the electrical signal on the gate 50 from affecting the depletion state of the auxiliary depletion layer 80 . When the source layer 20 and the drain layer 30 are in a high-voltage state, the auxiliary depletion layer 80 can deplete each other in the drift region of the drain layer 30, which doubles the effect of reducing the surface electric field, which can increase The breakdown voltage of the device can also use a higher doping concentration in the drift region to reduce the specific on-resistance of the device.
参考附图2是本发明一种另一种具体实施方式的结构示意图。作为优选的实施方式，所述掺杂阱层40在垂直于衬底表面的方向包括由Si1-xGex层41和Si层42构成的异质结，其中x大于0且小于1。其优点在于，可以通过调整Ge的摩尔百分比来调整异质结的能带结构，实现器件的优化。所述源极层20的材料优选为Ge，且掺杂浓度优选为1×1019至9×1020cm-3。Ge可以有效地抽取掺杂阱层40在靠近栅介质层53的表面的导电沟道中的空穴，抑制附体效应和BJT效应。 Referring to accompanying drawing 2, it is a structural schematic diagram of another specific embodiment of the present invention. As a preferred embodiment, the doped well layer 40 includes a heterojunction composed of a Si 1-x Ge x layer 41 and a Si layer 42 in a direction perpendicular to the substrate surface, where x is greater than 0 and less than 1. The advantage is that the energy band structure of the heterojunction can be adjusted by adjusting the molar percentage of Ge to realize device optimization. The material of the source layer 20 is preferably Ge, and the doping concentration is preferably 1×10 19 to 9×10 20 cm −3 . Ge can effectively extract the holes in the conductive channel of the doped well layer 40 near the surface of the gate dielectric layer 53 , and suppress the attachment effect and the BJT effect.
继续参考附图2，作为优选的实施方式，所述栅极50可以包括由不同材料构成的第一栅层51和第二栅层52，所述第一栅层51和第二栅层52在垂直于衬底10表面的方向上堆叠设置。作为一种可选的实施方式，所述第一栅层51的材料为N型多晶硅，第二栅层52的材料为P型多晶硅，第一栅层51和第二栅层52的掺杂浓度范围均是1×1019至5×1020cm-3。不同材料的第一栅层51和第二栅层52能够在掺杂阱层40在靠近栅介质层53的表面的导电沟道中引入阶梯表面电势分布，进而降低漏极层30附近的电场峰值,确保沟道中的平均电场得以提高，降低漏电阻，增强栅极50对沟道电导的控制能力。 Continuing to refer to FIG. 2 , as a preferred embodiment, the gate 50 may include a first gate layer 51 and a second gate layer 52 made of different materials, and the first gate layer 51 and the second gate layer 52 are in stacked in a direction perpendicular to the surface of the substrate 10 . As an optional implementation mode, the material of the first gate layer 51 is N-type polysilicon, the material of the second gate layer 52 is P-type polysilicon, and the doping concentrations of the first gate layer 51 and the second gate layer 52 are The range is 1×10 19 to 5×10 20 cm -3 . The first gate layer 51 and the second gate layer 52 made of different materials can introduce a stepped surface potential distribution in the conductive channel of the doped well layer 40 close to the surface of the gate dielectric layer 53, thereby reducing the peak value of the electric field near the drain layer 30, It ensures that the average electric field in the channel is increased, the leakage resistance is reduced, and the control ability of the gate 50 on the conductance of the channel is enhanced.
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。 The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications should also be considered Be the protection scope of the present invention.
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| CN1264158A (en) * | 1998-12-28 | 2000-08-23 | 因芬尼昂技术北美公司 | Autoregistered channel injection |
| CN101897028A (en) * | 2007-12-13 | 2010-11-24 | 飞兆半导体公司 | Structure of field effect transistor with low resistance channel region and forming method thereof |
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| CN101897028A (en) * | 2007-12-13 | 2010-11-24 | 飞兆半导体公司 | Structure of field effect transistor with low resistance channel region and forming method thereof |
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