CN103744405B - Towards two axial plane motion control cards and the two axial plane motion control methods of full-automatic surperficial mounting system - Google Patents

Abstract

The invention relates to a two-axis plane motion control card and a two-axis plane motion control method for a fully automatic surface mounting system, and relates to the fields of industrial motion control and plane surveying and mapping. It is to solve the problems of slow transmission speed, low reliability and low precision of the control card of the existing automatic surface mount system, and also to solve the problem that the existing plane motion control method cannot reflect the motion state of the controlled device in real time. It includes bus interface circuit, CPLD module, DSP module, SRAM cache module and lower layer interface circuit. The SRAM cache module is used to support large-capacity data storage. In the software program inside the DSP module, a synchronization algorithm and a speed planning algorithm are adopted. The synchronization algorithm makes the two coaxial motors reach a high degree of synchronization, so that the error of the present invention reaches Micron. The speed planning algorithm makes the motor movement smooth and smooth, the motor moves fast, and the motor is more stable and reliable when it stops. The invention is suitable for surface mounting machines, placement and insertion machines and similar products.

Description

Two-axis planar motion control card and two-axis planar motion control method for fully automatic surface mount system

technical field

The invention relates to the fields of industrial motion control and plane surveying and mapping.

Background technique

Fully automatic surface mount system is a device that uses surface mount technology to complete the task of mounting components on PCB boards. It integrates advanced technologies in multiple fields such as automatic control, mechanical design and manufacturing, image recognition, and digital signal processing. Part of the organic whole has high requirements for performance indicators such as speed and reliability of motion algorithm control, signal processing and transmission. Therefore, the fully automatic placement system has strict requirements on its core motion control card. At present, the motion control card design that cannot take into account both high speed and high reliability is the main problem in the existing technology, and it is also one of the important bottlenecks restricting the development of domestic surface mount technology. Moreover, the existing planar motion control methods for fully automatic surface mount systems cannot reflect the motion state of the controlled device in real time, that is to say, the instructions sent by the host computer cannot be adjusted in real time according to the motion state of the controlled device, so that the controlled device The control device completes the corresponding action.

Contents of the invention

The present invention aims to solve the problems of slow transmission speed, low reliability and low precision of the control card of the existing fully automatic surface mount system, and also to solve the problem that the existing planar motion control method cannot reflect the motion state of the controlled device in real time . A two-axis planar motion control card and a two-axis planar motion control method for fully automatic surface mount systems are now provided.

Two-axis planar motion control card for fully automatic surface mount system, which includes: bus interface circuit, CPLD module, DSP module, SRAM cache module and lower interface circuit;

The address signal input terminal of the bus interface circuit is connected to the CPLD module address output terminal; the data signal input and output terminals of the bus interface circuit are connected to the data signal output and input terminals of the CPLD module;

The RAM access control signal output terminal of the SRAM cache module is connected to the RAM access control signal input terminal of the CPLD module; the RAM data signal input and output terminals of the SRAM cache module are connected to the RAM data signal output and input terminals of the CPLD module; the SRAM address signal input of the SRAM cache module Connect the SRAM address signal output end of the CPLD module; the SRAM data signal input end of the SRAM cache module is connected to the SRAM data signal output end of the CPLD module;

The peripheral enable signal output end of the CPLD module is connected to the peripheral enable signal input end of the DSP module; the processor control signal input end of the CPLD module is connected to the processor control signal output end of the DSP module; the code disk feedback signal input of the CPLD module The terminal is connected to the code disc feedback signal output end of the lower layer interface circuit; the switch state signal input end of the CPLD module is connected to the switch state signal output end of the lower layer interface circuit; the PWM signal input end of the CPLD module is connected to the PWM signal input end of the lower layer interface circuit; CPLD The pulse signal output terminal of the module is the pulse signal input terminal of the DSP module; the pulse signal output terminal of the DSP module is connected to the pulse signal input terminal of the lower interface circuit.

CPLD module includes RAM access control module, address decoder, data exchange latch, pulse command generator, peripheral access control module, code disc feedback input module, switch state input module, PWM input module and pulse output module;

The RAM access control module is used to output the RAM access control signal to the SRAM cache module;

The address decoder is used to analyze the address signal of the bus interface circuit; the address decoder is also used to output the received address signal to the RAM access control module and the peripheral access control module respectively;

The data exchange latch is used for storing the data signal of the bus interface circuit, and is also used for storing the DSP control signal output by the DSP module, the code disc feedback signal output by the code disc feedback input module, the switch status signal output by the switch status input module, The PWM signal of the PWM input module; it is also used to output the pulse command to the pulse command generator;

The pulse command generator is used to output the pulse command to the pulse output module;

The peripheral access control module is used to output the peripheral address signal output by the address decoder to the DSP module;

The code disc feedback input module is used to read the code disc feedback signal output by the lower layer interface circuit;

The switch state input module is used to read the switch state signal output by the lower layer interface circuit;

The PWM input module is used to read the PWM signal output by the lower layer interface circuit;

The pulse output module is used to output the pulse command to the DSP module, and then the DSP module sends the pulse command to the lower layer interface circuit.

A two-axis planar motion control method for a fully automatic surface mount system, the specific steps of the method are as follows:

Step 1, the host computer sends a control signal to the CPLD module through the bus interface circuit, the data exchange latch of the CPLD module receives the control signal, and sends the control signal to the SRAM cache module, and the SRAM cache module transmits the control signal Send to the DSP module; the DSP module starts a timer interrupt or an external interrupt, if it is a timer interrupt, then perform step 2; if it is an external interrupt, then perform step 3;

Step 2, the timer interrupt starts, the DSP module sends the control signal to the data exchange latch of the CPLD module, and the data exchange latch sends the pulse signal to the pulse command generator, and the pulse command generator outputs the pulse signal to the pulse command generator The output module, the pulse output module outputs the pulse signal to the DSP module, and then the DSP module sends the pulse signal to the lower interface circuit, and the lower interface circuit outputs the pulse signal to the photoelectric isolation, and then drives the motor to move through the motor driver;

Step 3, the external interrupt starts, indicating that the host computer sends a control signal to the CPLD module through the bus interface circuit again, and the data exchange latch of the CPLD module receives the control signal, and sends the control signal to the SRAM cache module, and the SRAM cache The module sends the control signal to the DSP module, and the DSP module sends the control signal resent by the host computer to the data exchange latch of the CPLD module, and the data exchange latch sends a pulse signal to the pulse command generator, and the pulse command The generator outputs the pulse signal to the pulse output module, the pulse output module outputs the pulse signal to the DSP module, and then the DSP module sends the pulse signal to the lower interface circuit, and the lower interface circuit outputs the pulse signal to the photoelectric isolation, and then through the motor The driver drives the motor to move.

Step 4. The lower layer interface circuit sends the motion state of the motor to the CPLD module, and the CPLD module sends the code disk feedback signal, switch state signal and PWM signal to the data exchange through the code disk feedback input module, switch state input module and PWM input module respectively. The latch, the data exchange latch stores the code disc feedback signal, the switch state signal and the PWM signal into the SRAM cache module; at the same time, the data exchange latch transfers the code disc feedback signal, the switch state signal and the PWM signal through the bus interface circuit The signal is sent to the host computer for reading by the host computer;

Step 5. The upper computer judges the motion state of the motor according to the read code disc feedback signal, switch state signal and PWM signal, and resends the motor control command, and repeats step 1.

The invention is suitable for surface mounting machines, placement and insertion machines and similar products.

The two-axis planar motion control card for the automatic surface mount system of the present invention includes a bus interface circuit, a CPLD module, a DSP module, an SRAM cache module and a lower layer interface circuit, and the SRAM cache module is used to support large-capacity data Storage can realize DMA transmission function, which greatly improves the speed of large-scale data transmission. Compared with the control card of the existing automatic surface mount system, the transmission speed has increased by more than 50%. The software embedded in the DSP module adopts a synchronization algorithm and a speed planning algorithm. The synchronization algorithm can make the two coaxial motors reach a high degree of synchronization, so that the error of the present invention can reach the micron level, and the accuracy is improved by more than 30%; the speed planning algorithm can The motor moves smoothly, the motor moves fast, and the motor is more stable when it stops, and the reliability is high. Compared with the control card of the existing automatic surface mount system, the reliability is increased by more than 40%. The two-axis planar motion control method of the present invention reflects the motion state of the controlled device in real time, and adjusts the instructions sent by the upper computer in real time according to the motion state of the controlled device.

Description of drawings

Figure 1 is a schematic diagram of the electrical principle of a two-axis planar motion control card for a fully automatic surface mount system;

Figure 2 is a schematic diagram of the electrical principle of the DSP module of the two-axis planar motion control card for a fully automatic surface mount system;

Fig. 3 is the working process flowchart of DSP module;

Fig. 4 is a flow chart of the interruption process during the working process of the DSP module.

detailed description

Specific embodiment one: this embodiment is specifically described with reference to Fig. 1, and the two-axis planar motion control card facing the automatic surface mount system described in this embodiment includes: bus interface circuit 1, CPLD module 2, DSP module 3 , SRAM cache module 4 and lower layer interface circuit 5;

The address signal input terminal of the bus interface circuit 1 is connected to the CPLD module 2 address output terminals; the data signal input and output terminals of the bus interface circuit 1 are connected to the data signal output and input terminals of the CPLD module 2;

The RAM access control signal output end of the SRAM buffer module 4 is connected to the RAM access control signal input end of the CPLD module 2; the RAM data signal input and output ends of the SRAM buffer module 4 are connected to the RAM data signal output and input ends of the CPLD module 2; the SRAM buffer module 4 The SRAM address signal input end of the SRAM address signal is connected to the SRAM address signal output end of the CPLD module 2; the SRAM data signal input end of the SRAM cache module 4 is connected to the SRAM data signal output end of the CPLD module 2;

The peripheral hardware enable signal output end of CPLD module 2 connects the peripheral hardware enable signal input end of DSP module 3; The processor control signal input end of CPLD module 2 connects the processor control signal output end of DSP module 3; CPLD module 2 The code disc feedback signal input end is connected to the code disc feedback signal output end of the lower layer interface circuit 5; the switch state signal input end of the CPLD module 2 is connected to the switch state signal output end of the lower layer interface circuit 5; the PWM signal input end of the CPLD module 2 is connected to the lower layer The PWM signal input end of the interface circuit 5; the pulse signal output end of the CPLD module 2 is connected to the pulse signal input end of the DSP module 3; the pulse signal output end of the DSP module 3 is connected to the pulse signal input end of the lower layer interface circuit 5.

Principle description: The host computer exchanges data with the CPLD module through the bus interface circuit.

The CPLD module sends the command data sent by the host computer to the pulse command generator; the pulse command generator generates a pulse signal for driving the motor, and sends the pulse signal to the DSP module 3 through the pulse output module; the DSP module 3 then passes The lower layer interface circuit completes the data transmission with the motor, so that the motor completes the corresponding action according to the control command of the upper computer.

The DSP module is the control core of the two-axis planar motion control card for the fully automatic surface mount system. Its core program is used to control the working state of the planar motion of the fully automatic surface mount system, so that the placement head can realize the corresponding according to the predetermined process. functions, and provides prompt alarms and error handling mechanisms in various error situations.

The SRAM cache module is an important part of the two-axis planar motion control card for fully automatic surface mount systems. In addition to completing the basic data storage function, it also provides the cache function of data transmission and balances the data between the host computer and the DSP module. In addition, the SRAM cache module can also realize DMA data transmission, which greatly improves the efficiency of data transmission.

Specific Embodiment 2: This embodiment will be described in detail with reference to Fig. 1 and Fig. 2. This embodiment is a further description of the two-axis planar motion control card for fully automatic surface mount system described in Specific Embodiment 1. This embodiment middle,

CPLD module 2 includes RAM access control module 2-1, address decoder 2-2, data exchange latch 2-3, pulse instruction generator 2-4, peripheral access control module 2-5, code disk feedback input Module 2-6, switch state input module 2-7, PWM input module 2-8 and pulse output module 2-9;

The RAM access control module 2-1 is used to output the RAM access control signal to the SRAM cache module 4;

The address decoder 2-2 is used to analyze the address signal of the bus interface circuit 1; the address decoder 2-2 is also used to output the received address signal to the RAM access control module 2-1 and the Peripheral access control module 2-5;

The data exchange latch 2-3 is used to store the data signal of the bus interface circuit 1, and is also used to store the DSP control signal output by the DSP module 3, the code wheel feedback signal output by the code wheel feedback input module 2-6, and the switch The switch state signal output by the state input module 2-7, the PWM signal of the PWM input module 2-8; it is also used to output the pulse command to the pulse command generator 2-4;

The pulse command generator 2-4 is used to output the pulse command to the pulse output module 2-9;

The peripheral access control module 2-5 is used to output the peripheral address signal output by the address decoder 2-2 to the DSP module 3;

The code disc feedback input module 2-6 is used to read the code disc feedback signal output by the lower layer interface circuit 5;

The switch state input module 2-7 is used to read the switch state signal output by the lower layer interface circuit 5;

The PWM input module 2-8 is used to read the PWM signal output by the lower layer interface circuit 5;

The pulse output module 2-9 is used to output the pulse command to the DSP module 3, and then the DSP module 3 sends the pulse command to the lower interface circuit 5.

Principle: The address decoder decodes the address information sent by the host computer, so that the corresponding functional modules and peripherals on the board are in the selected state. The data exchange latch is used to complete the data exchange between the host computer and DSP, and transmit the feedback information to the host computer. The data exchange latch module can schedule the transmission direction of the control signal and complete the data exchange between the upper computer and the DSP module of the bus interface circuit. The peripheral hardware access control module is used to realize the operation timing of peripheral hardware access. The RAM access control module is used to complete the operation sequence of the RAM chip. According to the command of the host computer, the pulse generator makes speed planning through the planning algorithm, generates the pulse signal for controlling the motor, and outputs it to the motor driver. The code disc feedback signal, PWM signal and switch state signal are all read by the host computer through the data exchange latch.

Specific implementation mode three: the two-axis planar motion control method for the fully automatic surface mount system described in this implementation, the specific steps of the method are as follows:

Step 1, host computer sends control signal to CPLD module 2 through bus interface circuit 1, and the data exchange latch 2-3 of described CPLD module 2 receives this control signal, and this control signal is sent to SRAM cache module 4, SRAM The cache module 4 sends the control signal to the DSP module 3; the DSP module 3 starts a timer interrupt or an external interrupt, if the timer is interrupted, then perform step 2; if it is an external interrupt, then perform step 3;

Step 2, timer interrupt start, DSP module 3 sends described control signal to the data exchange latch 2-3 of CPLD module 2, and data exchange latch 2-3 sends pulse signal to pulse instruction generator 2-4, The pulse command generator 2-4 output pulse signal to the pulse output module 2-9, the pulse output module 2-9 output pulse signal to the DSP module 3, then the pulse signal is sent to the lower layer interface circuit 5 by the DSP module 3, The lower layer interface circuit 5 outputs the pulse signal to the photoelectric isolation, and then drives the motor to move through the motor driver;

Step 3, external interrupt starts, shows that host computer sends control signal to CPLD module 2 again by bus interface circuit 1, and the data exchange latch 2-3 of described CPLD module 2 receives this control signal, and this control signal is sent to SRAM cache module 4, SRAM cache module 4 sends the control signal to DSP module 3, and DSP module 3 sends the control signal resent by the host computer to the data exchange latch 2-3 of CPLD module 2, and the data exchange latch The device 2-3 sends the pulse signal to the pulse command generator 2-4, and the pulse command generator 2-4 outputs the pulse signal to the pulse output module 2-9, and the pulse output module 2-9 outputs the pulse signal to the DSP module 3, Then the DSP module 3 sends the pulse signal to the lower layer interface circuit 5, and the lower layer interface circuit 5 outputs the pulse signal to the photoelectric isolation, and then drives the motor to move through the motor driver.

Step 4, the lower layer interface circuit 5 sends the motion state of the motor to the CPLD module 2, and the CPLD module 2 feeds back the code disk through the code disk feedback input module 2-6, the switch state input module 2-7 and the PWM input module 2-8 respectively. signal, switch state signal and PWM signal are sent to the data exchange latch 2-3, and the data exchange latch 2-3 stores the code disc feedback signal, switch state signal and PWM signal into the SRAM buffer module; data exchange The latch 2-3 sends the code disc feedback signal, switch status signal and PWM signal to the host computer through the bus interface circuit for the host computer to read;

Step 5. The upper computer judges the motion state of the motor according to the read code disc feedback signal, switch state signal and PWM signal, and resends the motor control command, and repeats step 1.

Specific embodiment four: this embodiment is specifically described with reference to Fig. 3, and this embodiment is in order to explain the work process of DSP module, and the step of its work process is as follows;

Step 1. Initialize system resources and execute Step 3;

Step 2. Initialize GPIO, event manager and watchdog;

Step 3. Clear the RAM, and then perform step 5;

Step 4. Read the drive status for the first time;

Step 5, set interrupt;

Step 6. Set the watchdog;

Step 7. Wait for an external interrupt to be triggered.

Specific embodiment five: the present embodiment is specifically described with reference to Fig. 4, and present embodiment is in order to illustrate the interruption process in the work process of DSP module, and described interruption process step is as follows:

Step A1, enter the interrupt process, judge whether it is a timer interrupt, if so, then execute step A2, if not, then execute step A10;

Step A2, read the state of the magnetic scale;

Step A3, whether there is a fault message in the DSP self-test, and the DSP judges whether the execution of the control command to the motor by the host computer is completed. If a fault message appears in the DSP self-test, no matter whether the execution of the control command to the motor by the host computer is completed, step A4 is executed;

If there is no fault information in the DSP self-test, and the host computer has completed the execution of the motor control command, then perform step A5; After the host computer completes the execution of the motor control command, execute step A5;

Step A4, set the fault state, and then execute step A6;

Step A5, the motor completes the relevant actions of the control command of the host computer to the motor;

Step A6, motor mark position fault state in DSP, then execute step A7;

Step A7, stop the motor, and then perform step A8;

Step A8, detecting and reporting fault information, and then performing step A9;

Step A9, clear watchdog, end;

Step A10, judging whether it is an external interrupt, if yes, execute step A11, if not, execute step A20;

Step A11, reading instructions;

Step A12, judging whether it is a position command, if yes, then execute the position command, if not, then perform step 13;

Step A13, judging whether it is a position reset command, if yes, then the motor returns to the origin, if not, then execute step A14;

Step A14, judging whether it is a register reset command, if yes, clear and reset all registers, if not, then execute step A15;

Step A15, judging whether it is a sensor clearing instruction, if yes, then clear the sensor value, if not, then execute step A16;

Step A16, judging whether it is an emergency stop command, if yes, stop the motor, if not, then execute step A17;

Step A17, judge whether it is a RAM read and write command, if so, open the RAM and enable it, if not, then perform step A18,

Step A18, judging whether it is an instruction to read and write register parameters, if yes, read and write register parameters, and if not, end.

Principle: During the working process of the DSP module, the initialization operation is first performed and the system interrupt is turned on, and then the interrupt service routine works. The control of the host computer to the motor is completed through the interrupt service program.

The interrupt process of DSP module includes external interrupt and timer interrupt. After entering the interrupt service routine, judge whether to enter the timer interrupt service routine or enter the external interrupt service routine through the interrupt flag.

If the interrupt flag indicates that the timer interrupt service program is entered, it means that the host computer has not sent new program instructions at this time, and the DSP module determines the actions to be performed by the DSP module according to the current command.

If the interrupt flag indicates that it is an external interrupt service program, it indicates that the host computer has issued a new program instruction. According to different instructions, the DSP module sets the corresponding registers, and starts the corresponding peripherals to perform corresponding operations.

The two-axis planar motion control card and the two-axis planar motion control method for the automatic surface mounting system of the present invention can complete the reading and writing of RAM cache, generate motor control pulse commands and obtain state feedback of peripherals. All the instructions of the planar motion of the surface mount system are completed on the basis of these basic instructions.

RAM cache read and write. The RAM cache is used to temporarily store relevant control data, and provides a high-speed and reliable transmission method for the communication between the host computer and the device port.

Generate motor control pulse commands. The main function of the motion control board is motor control, which can generate corresponding control pulse sequences according to the instructions of the host computer, and control the frequency and phase of the pulses through the speed planning algorithm to achieve smooth control of the motor. Basically, reduce the impact on the mechanical structure.

Get status feedback from peripherals. The motion control card can obtain the feedback input of the code disc signal, PWM signal, and switch state signal through the peripheral signal interface, so that the host computer can obtain the running state of the placement device in real time.

Claims (3)

1. The two-axis planar motion control card facing the full-automatic surface mount system is characterized in that it includes: bus interface circuit (1), CPLD module (2), DSP module (3), SRAM cache module (4) and Lower layer interface circuit (5); The address signal input end of the bus interface circuit (1) is connected to the CPLD module (2) address output end; the data signal input and output end of the bus interface circuit (1) is connected to the data signal output and input end of the CPLD module (2); The RAM access control signal output end of the SRAM buffer module (4) is connected to the RAM access control signal input end of the CPLD module (2); the RAM data signal input and output ends of the SRAM buffer module (4) are connected to the RAM data signal of the CPLD module (2). Output and input terminals; the SRAM address signal input terminal of the SRAM cache module (4) is connected to the SRAM address signal output terminal of the CPLD module (2); the SRAM data signal input terminal of the SRAM cache module (4) is connected to the SRAM data of the CPLD module (2) signal output; The peripheral hardware enable signal output end of the CPLD module (2) is connected to the peripheral hardware enable signal input end of the DSP module (3); the processor control signal input end of the CPLD module (2) is connected to the processor control of the DSP module (3) Signal output end; The code disc feedback signal input end of CPLD module (2) connects the code disc feedback signal output end of lower layer interface circuit (5); The switch state signal input end of CPLD module (2) connects lower layer interface circuit (5) The switch state signal output terminal; the PWM signal input terminal of the CPLD module (2) is connected to the PWM signal input terminal of the lower layer interface circuit (5); the pulse signal output terminal of the CPLD module (2) is connected to the pulse signal input terminal of the DSP module (3) ; The pulse signal output end of the DSP module (3) is connected to the pulse signal input end of the lower layer interface circuit (5). 2. the two-axis planar motion control card facing full-automatic surface mount system according to claim 1, is characterized in that, CPLD module (2) comprises RAM access control module (2-1), address decoder (2 -2), data exchange latch (2-3), pulse command generator (2-4), peripheral access control module (2-5), code disc feedback input module (2-6), switch status input Module (2-7), PWM input module (2-8) and pulse output module (2-9); The RAM access control module (2-1) is used to output the RAM access control signal to the SRAM cache module (4); The address decoder (2-2) is used to analyze the address signal of the bus interface circuit (1); the address decoder (2-2) is also used to output the received address signal to the RAM access A control module (2-1) and a peripheral access control module (2-5); The data exchange latch (2-3) is used for storing the data signal of the bus interface circuit (1), and is also used for storing the DSP control signal output by the DSP module (3), the code disc feedback input module (2-6) The output code disk feedback signal, the switch state signal output by the switch state input module (2-7), the PWM signal of the PWM input module (2-8); it is also used to output the pulse command to the pulse command generator (2-4) ; The pulse command generator (2-4) is used to output the pulse command to the pulse output module (2-9); The peripheral access control module (2-5) is used to output the peripheral address signal output by the address decoder (2-2) to the DSP module (3); The code disc feedback input module (2-6) is used to read the code disc feedback signal output by the lower layer interface circuit (5); The switch state input module (2-7) is used to read the switch state signal output by the lower layer interface circuit (5); The PWM input module (2-8) is used to read the PWM signal output by the lower layer interface circuit (5); The pulse output module (2-9) is used to output the pulse command to the DSP module (3), and then the DSP module (3) sends the pulse command to the lower layer interface circuit (5). 3. A two-axis planar motion control method for fully automatic surface mount systems, characterized in that the specific steps of the method are as follows: Step 1, host computer sends control signal to CPLD module (2) by bus interface circuit (1), and the data exchange latch (2-3) of described CPLD module (2) receives this control signal, and this control signal Sent to the SRAM cache module (4), the SRAM cache module (4) sends the control signal to the DSP module (3); the DSP module (3) starts a timer interrupt or an external interrupt, if the timer is interrupted, then perform step 2 ; If it is an external interrupt, execute step 3; Step 2, timer interrupt start, DSP module (3) sends described control signal to the data exchange latch (2-3) of CPLD module (2), and data exchange latch (2-3) sends pulse signal to A pulse command generator (2-4), the pulse command generator (2-4) outputs a pulse signal to a pulse output module (2-9), and the pulse output module (2-9) outputs a pulse signal to a DSP module (3 ), then the pulse signal is sent to the lower layer interface circuit (5) by the DSP module (3), and the lower layer interface circuit (5) outputs the pulse signal to the photoelectric isolation, and then drives the motor to move by the motor driver; Step 3, external interrupt starts, shows that host computer sends control signal to CPLD module (2) again by bus interface circuit (1), and the data exchange latch (2-3) of described CPLD module (2) receives this control signal , and send the control signal to the SRAM cache module (4), the SRAM cache module (4) sends the control signal to the DSP module (3), and the DSP module (3) sends the control signal resent by the host computer to the CPLD The data exchange latch (2-3) of module (2), the data exchange latch (2-3) sends pulse signal to pulse instruction generator (2-4), and described pulse instruction generator (2-4 ) output pulse signal to the pulse output module (2-9), the pulse output module (2-9) outputs the pulse signal to the DSP module (3), then the pulse signal is sent to the lower layer interface circuit (5) by the DSP module (3) ), the lower layer interface circuit (5) outputs the pulse signal to the photoelectric isolation, and then drives the motor to move through the motor driver; Step 4, the lower layer interface circuit (5) sends the motion state of the motor to the CPLD module (2), and the CPLD module (2) feeds back the input module (2-6), the switch state input module (2-7) and the PWM through the code disc The input module (2-8) sends the code disc feedback signal, the switch state signal and the PWM signal to the data exchange latch (2-3) respectively, and the data exchange latch (2-3) transmits the code disc feedback signal , switch state signal and PWM signal are stored in the SRAM cache module; at the same time, the data exchange latch (2-3) sends the code disc feedback signal, switch state signal and PWM signal to the host computer through the bus interface circuit for the host computer to read ; Step 5. The upper computer judges the motion state of the motor according to the read code disc feedback signal, switch state signal and PWM signal, and resends the motor control command, and repeats step 1.