CN103715144B - Discrete grid storage device and forming method thereof - Google Patents

Abstract

The invention provides a discrete gate storage device and a forming method thereof. The forming method of the discrete gate storage device includes: providing a substrate, forming a control gate structure on the substrate, the area between two adjacent control gate structures is an erasing gate area, and the two adjacent control gate structures are connected to the erasing gate structure. The opposite side of the gate area is the word line area; the first side wall is formed around the control gate structure; the second side wall is formed around the first side wall; the sacrificial side wall is formed around the second side wall; the floating gate is formed; Said sacrificial sidewall, exposing the part of the floating gate; forming a tunnel dielectric layer, forming a word line in the word line area, and forming an erasing gate in the erasing gate area. The invention also provides a discrete gate memory device. The first and second side walls of the present invention increase the isolation effect between word lines and control gates, word lines and floating gates, control gates and erasing gates, and improve the programming efficiency, uniformity and erasing efficiency of storage devices , uniformity, especially to reduce the leakage between the word line and the floating gate to solve the problem of write disturbance.

Description

Discrete gate memory device and method of forming same

technical field

The invention relates to the field of semiconductor technology, in particular to a discrete gate storage device and a forming method thereof.

Background technique

In the current semiconductor industry, integrated circuit products can be mainly divided into three types: analog circuits, digital circuits and digital/analog hybrid circuits, among which storage devices are an important type of digital circuits. In recent years, among storage devices, the development of flash memory (flash memory) is particularly rapid. The main feature of flash memory is that it can keep the stored information for a long time without power on; and it has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. field has been widely used.

The flash memory mainly includes a stacked gate flash memory and a discrete gate flash memory, wherein the discrete gate flash memory has the advantages of low programming voltage and high programming efficiency and is widely used.

FIG. 1 shows a discrete gate flash memory, including: a semiconductor substrate 100, an erasing gate (EG: erasinggate) 105 located on the semiconductor substrate 100, a tunnel oxide layer 108, and part of the tunnel oxide layer 108 Located on the semiconductor substrate 100, partly located on the sidewall of the erasing gate 105; located in the semiconductor substrate 100 opposite to the source region (not shown) with the erasing gate 105; floating gates located on both sides of the erasing gate 105 structure and a control gate structure, the floating gate structure includes a floating gate dielectric layer 102a located on the surface of the semiconductor substrate 100 and a floating gate 102 located on the floating gate dielectric layer 102a, the control gate structure includes a control gate located on the surface of the floating gate 102 The gate dielectric layer 103a and the control gate 103 on the control gate dielectric layer 103a, the spacer 107 on the side of the floating gate structure and the control gate structure away from the erasing gate 105; the semiconductor on the side of the sidewall 107 away from the erasing gate 105 The word line 104 on the substrate 100; the word line oxide layer 104a between the word line 104 and the semiconductor substrate 100; show).

The efficiency and uniformity of the programming and erasing of the existing discrete gate flash memory are not good, especially the write disturbance (disturb) is relatively large.

For more information about the discrete gate flash memory, please refer to the Chinese patent with publication number CN101202311A.

Contents of the invention

The problem solved by the invention is that the programming and erasing efficiency and uniformity of the discrete gate flash memory are not good, especially the writing disturbance (disturb) is relatively large.

In order to solve the above problems, the present invention provides a method for forming a discrete gate storage device, including:

providing a substrate, on which a first dielectric layer, a floating gate layer, a second dielectric layer and a control gate layer are sequentially formed;

Etching the control gate layer and the second dielectric layer to form a control gate structure, the area between two adjacent control gate structures is an erasing gate region, and the two adjacent control gate structures are opposite to the erasing gate region One side is the word line area;

forming a first spacer around the control gate structure;

After forming the first sidewall, removing the floating gate layer located on the word line region;

After removing the floating gate layer located on the word line area, forming a second side wall around the first side wall;

forming a sacrificial sidewall around the second sidewall;

After forming the sacrificial sidewall, removing the floating gate layer located in the erasing gate region to form a floating gate;

removing the sacrificial sidewall located in the erase gate region, exposing the part of the floating gate covered by the sacrificial sidewall;

forming a tunneling dielectric layer to cover the exposed part of the floating gate, the substrate of the erasing gate region, and the second sidewall between two adjacent control gate structures; the thickness of the tunneling dielectric layer is smaller than the thickness of the sacrificial sidewall ;

A word line is formed in the word line area, and an erasing gate is formed in the erasing gate area.

Optionally, both the floating gate layer and the control gate layer are made of polysilicon.

Optionally, the first sidewall includes a silicon oxide layer and a silicon nitride layer formed on the silicon oxide layer.

Optionally, the second sidewall includes a silicon oxide layer and a silicon nitride layer formed on the silicon oxide layer.

Optionally, the material of the sacrificial sidewall is silicon oxide or polymer.

Optionally, after removing the sacrificial sidewall, the method further includes a step of: removing the second sidewall of the erase gate region.

Optionally, after forming the first sidewall, before removing the floating gate layer located on the word line region, a step is further included: using the first sidewall as a mask to perform ion implantation on the substrate of the word line region, To adjust the threshold voltage of the word line region.

Optionally, after forming the tunneling dielectric layer, before forming the word line in the word line region, the method further includes a step of removing the first dielectric layer located in the word line region.

Optionally, after removing the first dielectric layer located in the word line region, further comprising forming a word line dielectric layer on the substrate in the word line region.

The present invention also provides a discrete gate storage device, including:

Substrate;

A floating gate structure on the substrate, a control gate structure on the floating gate structure and a first side wall, the first side wall is located around the control gate structure; between two adjacent control gate structures The area between them is the erasing gate area; the side opposite to the erasing gate area of two adjacent control gate structures is the word line area; the floating gate structure includes a floating gate dielectric layer and a floating gate dielectric layer A floating gate, the control gate structure comprising a control gate dielectric layer and a control gate located on the control gate dielectric layer;

There is a second sidewall around the floating gate structure and the first sidewall, and the floating gate structure has a boss protruding from the second sidewall on one side of the erase gate region;

A tunneling dielectric layer covering the boss, the substrate of the erasing gate region, and the second sidewall between two adjacent control gate structures, the thickness of the tunneling dielectric layer is smaller than the width of the boss;

a word line dielectric layer on the word line region and a word line on the word line dielectric layer;

An erasing gate covering the tunnel dielectric layer located on the erasing gate region.

Optionally, the first sidewall includes a silicon oxide layer and a silicon nitride layer formed on the silicon oxide layer.

Optionally, the second sidewall includes a silicon oxide layer and a silicon nitride layer formed on the silicon oxide layer.

Compared with the prior art, the above scheme has the following advantages:

Forming a first sidewall around the control gate structure, using the first sidewall as a mask to etch the floating gate layer under the control gate structure, instead of directly etching the floating gate layer using the control gate structure as a mask , reducing the etching damage to the control gate structure, that is, the formation of the first spacer will not reduce the thickness of the control gate or make the surface of the control gate uneven, which improves the uniformity of the surface of the control gate structure, thereby improving The efficiency of programming and the uniformity of programming are improved.

A first sidewall and a second sidewall are formed between the control gate and the word line to replace the single-layer sidewall in the prior art. Wherein, the total thickness of the first side wall and the second side wall is the same as that of the side wall in the prior art. A second spacer is formed between the floating gate and the word line to replace the single layer spacer in the prior art. When the split-gate storage device of the present invention enters the programming state, without affecting the programming efficiency, the internal structure of the sidewall between the control gate and the word line, between the floating gate and the word line is changed, and the isolation of the sidewall is increased. Effect, thereby reducing the generation of leakage current, further reducing the probability of leakage current entering the floating gate under the action of the control gate, that is, reducing the leakage between the word line and the floating gate, avoiding the change that should not be written Write changes in the cells to solve the write disturb problem during programming.

There is a second sidewall around the floating gate structure and the first sidewall, and the floating gate structure has a boss protruding from the second sidewall on one side of the erase gate region. The tunnel dielectric layer covers the boss, and covers the substrate of the erasing gate region and the second sidewall between two adjacent control gate structures. The thickness of the tunneling dielectric layer is smaller than the thickness of the boss because the erasing gate formed in the erasing gate region and the floating gate have a lateral overlapping portion, and the lateral overlapping portion can make tunneling in the tunneling dielectric layer The increase of punching electrons increases the tunneling current in the tunneling dielectric layer and improves the erasing efficiency.

When the split-gate storage device of the present invention enters the erasing state, a first sidewall, a second sidewall and a tunneling dielectric layer are formed between the control gate and the erasing gate to replace the tunneling oxide layer in the prior art, wherein, The total thickness of the first sidewall, the second sidewall and the tunnel dielectric layer is the same as the thickness of the tunnel oxide layer in the prior art. While not affecting the erasing efficiency, the isolation effect of the side wall is increased, thereby reducing the generation of leakage current, thereby improving the erasing uniformity during erasing.

Description of drawings

The above and other objects, features and advantages of the present invention will be more apparent through a more specific description of preferred embodiments of the present invention shown in the accompanying drawings. Like reference numerals designate like parts throughout the drawings. The drawings are not intended to be drawn in actual scale, and the emphasis is on illustrating the gist of the present invention. In the drawings, some layers and regions are exaggerated for clarity.

FIG. 1 is a schematic structural diagram of a prior art discrete gate memory device;

2 is a schematic flowchart of a method for forming a discrete gate memory device according to an embodiment of the present invention;

3 to 16 are schematic cross-sectional structural views of an embodiment of a method for forming a discrete gate memory device according to an embodiment of the present invention.

detailed description

Referring to FIG. 1, when the existing discrete gate flash memory is programmed, a positive voltage is applied to the control gate 103, an operating voltage is applied to the word line 104 to open the lower channel region, a negative voltage is applied to the drain region, the source region is grounded, and the control gate When the voltage of 103 is greater than the voltage of the drain region, the electrons in the conductive channel will be accelerated to jump from the channel region to the floating gate 102 through the gap (gap) 10 between the word line 104 and the floating gate 102, and then complete programming (writing) action; when the existing discrete gate flash memory is erased, the control gate 103 is grounded, and the erasing gate 105 is applied with a positive voltage, and the electrons are tunneled from the floating gate 102 to the erasing gate 105, and the charge in the floating gate 102 is completed. erase.

The inventors have found that the programming and erasing efficiency and uniformity of the discrete gate flash memory are not good, especially the major reasons for the larger write disturbance (disturb) are as follows:

(1) The uniformity of the surface of the control gate structure is positively related to the efficiency and uniformity of the programming and erasing of the discrete gate flash memory, specifically: the uniformity of the control gate surface will affect the uniformity of the programming and erasing current, and the programming The uniformity of the programming and erasing current is positively related to the efficiency and uniformity of programming and erasing, so the better the uniformity of the surface of the control gate structure, the higher the uniformity of programming and erasing current, and the efficiency and uniformity of programming and erasing The higher the sex.

(2) In the existing process of manufacturing discrete gate flash memory, the material of the formed sidewall 107 is a single-layer structure of silicon oxide, and silicon oxide is easily damaged in the subsequent wet etching process, reducing the size of the sidewall 107. The uniformity of the thickness and surface, that is, reduces the uniformity of the programming current of the discrete gate flash memory, thereby affecting the efficiency and uniformity of programming.

(3) In the existing process of making the discrete gate flash memory, the sidewall 107 formed is a single-layer structure of silicon oxide, and the structure is single, so it is not possible to carry out a process between the word line and the control gate, or between the word line and the floating gate. Very good isolation, so that the leakage current cannot be effectively prevented from entering the floating gate under the action of the control gate, and the leakage between the word line and the floating gate is reduced, so that the cells that should not be written into the change are changed, and then Create write disturb problems.

(4) The important factor affecting the erasing efficiency of the discrete gate flash memory is the tunneling current in the tunneling dielectric layer. If the tunneling current is large, the erasing efficiency of the memory will be high. If the tunneling current is small, the erasing efficiency of the memory will be high. just low. In the prior art, the erasing voltage is usually increased to increase the tunneling current in the tunnel dielectric layer, and the increase in the erasing voltage will affect the stability of the discrete gate flash memory and increase power consumption. Therefore, in the prior art, Improving the erasing efficiency of the discrete gate flash memory is a difficult problem, and the inventors further found that the contact area between the floating gate and the tunneling dielectric layer, and between the tunneling dielectric layer and the erasing gate is related to the size of the tunneling current. Increasing the contact area between the floating gate and the tunneling dielectric layer, and between the tunneling dielectric layer and the erasing gate can increase the number of tunneling electrons, thereby increasing the tunneling current in the tunneling dielectric layer, thereby improving erasing efficiency.

(5) In the prior art, the tunneling oxide layer 108 between the control gate and the erasing gate is a single-layer structure, which cannot provide good isolation between the control gate and the erasing gate, and cannot reduce the leakage current, thus The erasing uniformity of the discrete gate flash memory is not good when erasing.

Therefore, the inventor obtained a method for forming a discrete gate storage device through creative efforts. 2 is a schematic flowchart of a method for forming a discrete gate memory device according to an embodiment of the present invention, and FIGS. 3 to 16 are schematic cross-sectional structural views of an embodiment of a method for forming a discrete gate memory device according to an embodiment of the present invention. The method for forming the discrete gate memory device will be described in detail below with reference to FIG. 3 to FIG. 16 and FIG. 2 .

First, referring to FIG. 3 , step S1 in FIG. 2 is performed to provide a substrate 300 on which a first dielectric layer 301 , a floating gate layer 302 , a second dielectric layer 303 and a control gate layer 304 are sequentially formed.

The substrate 300 may be silicon or silicon germanium with single crystal, polycrystalline or amorphous structure, or silicon on insulator (SOI). Or other materials may also be included, such as gallium arsenide and other III-V compounds.

The first dielectric layer 301 in this embodiment may be silicon oxide, with a thickness ranging from 80 to 100 angstroms. The floating gate layer 302 in this embodiment may be polysilicon, with a thickness ranging from 300 to 500 angstroms.

The second dielectric layer 303 may be silicon oxide or a stacked structure of silicon oxide-silicon nitride-silicon oxide (ONO). In this embodiment, the second dielectric layer 303 is a stacked structure of silicon oxide-silicon nitride-silicon oxide (ONO). The thickness of the second dielectric layer 303 ranges from 140 to 160 angstroms.

The control gate layer 304 in this embodiment may be polysilicon, with a thickness ranging from 500 to 900 angstroms.

The material of the hard mask layer 305 on the control gate layer 304 may be one or more of silicon oxide, silicon nitride, silicon oxynitride or metal hard mask. In this embodiment, it is silicon nitride with a thickness ranging from 800 to 1200 angstroms. The hard mask layer 305 is used as a polishing stop layer when forming erasing gates and word lines.

Referring to FIG. 4, step S2 in FIG. 2 is executed, the control gate layer 304 and the second dielectric layer 303 are etched to form a control gate structure 30, and the area between two adjacent control gate structures 30 is the erasing gate region 40 The side of two adjacent control gate structures 30 opposite to the erasing gate region 40 is the word line region 50 .

Specifically, the etching adopts dry etching, and the dry etching adopts reactive ion etching, and the process gas used is mainly fluorine-containing gas. The above etching step also includes etching the hard mask layer 305 shown in FIG. 3 . The control gate structure 30 formed by etching includes a control gate dielectric layer 306 and a control gate 307 on the control gate dielectric layer 306 .

Referring to FIG. 5 , step S3 in FIG. 2 is executed to form a first spacer 309 around the control gate structure 30 .

The first sidewall 309 is a stacked structure of a silicon oxide layer 309a and a silicon nitride layer 309b, including a silicon oxide layer 309a and a silicon nitride layer 309b, and the exposed silicon nitride layer 309b. The silicon nitride layer 309b needs to be uniform enough to improve the uniformity of the second spacer formed around the silicon nitride layer 309b, thereby improving the stability of the discrete gate flash memory.

Next, referring to FIG. 6 and FIG. 7 , step S4 in FIG. 2 is performed, and after the first sidewall 309 is formed, the floating gate layer 302 on the word line region 50 is removed.

The specific method is as follows: referring to FIG. 6, a mask layer 310 is formed, which is a photoresist layer in this embodiment. The mask layer 310 covers the area between the control gate structures 30 and covers the hard mask layer 305 to mask The layer 310 and the first spacer 309 are masks, and ion implantation is performed on the substrate 300 located in the word line region 50 to adjust the threshold voltage of the word line region 50 .

After the ion implantation, referring to FIG. 7 , the floating gate layer 302 is etched using the mask layer 310 and the first sidewall 309 as masks to remove the floating gate layer 302 located on the word line region 50 . At this time, the first dielectric layer 301 is exposed, and then the mask layer 310 is removed.

It should be noted that the floating gate layer 302 under the control gate structure 30 is etched using the first sidewall 309 as a mask, instead of directly etching the floating gate layer 302 using the control gate structure 30 as a mask in the prior art. Etching reduces the damage to the control gate structure 30 caused by etching, that is, the first spacer 309 will not reduce the thickness of the control gate structure 30 or make the surface of the control gate structure 30 uneven, thereby improving the control gate structure. The uniformity of the surface of the structure 30 further improves programming and erasing efficiency and programming and erasing uniformity.

In addition, the ion implantation for adjusting the threshold voltage of the word line region 50 and the etching of the floating gate layer 302 in the word line region 50 both use the mask layer 310 as a mask, which simplifies the process steps.

Next, referring to FIG. 8 , step S5 in FIG. 2 is performed, and after removing the floating gate layer 302 on the word line region 50 , a second spacer 311 is formed around the first spacer 309 .

The second side wall 311 is a stacked structure of a silicon oxide layer 311a and a silicon nitride layer 311b, and the silicon nitride layer is exposed outside.

The total thickness of the second side wall and the first side wall is equal to the thickness of the single-layer side wall in the prior art. If the total thickness of the first sidewall and the second sidewall is too thick, the distance between the channel region below the word line and the floating gate formed later will become larger. When the programming voltage is high, the transition potential energy of electrons from the channel region to the floating gate will increase, which is not conducive to the injection of electrons in the channel region to the floating gate, reducing the size and uniformity of the programming current and reducing the programming efficiency. Efficiency and uniformity, especially when programming multiple memory cells, this impact is particularly serious; if the total thickness of the first sidewall and the second sidewall is too thin, the lateral distance between the channel region and the subsequently formed floating gate When the distance is reduced, when programming, the lateral electric field applied by the programming voltage to the gap region between the channel region and the floating gate increases, which is not conducive to the injection of electrons in the channel region to the floating gate, which reduces the magnitude of the programming current and reduces the This affects the efficiency and uniformity of programming, especially when programming multiple memory cells.

In this embodiment, the second sidewall 311 is formed by dry etching the silicon oxide layer and the silicon nitride layer. It should be noted that the dry etching is to etch the silicon nitride layer and the silicon oxide layer in the same etching machine, that is, one-time etching, which simplifies the process flow on the one hand; The dimensional deviation caused by etching the silicon nitride layer and the silicon oxide layer by different etching equipment or different etching processes improves the uniformity of the second sidewall 311 .

Referring to FIG. 9 , step S6 in FIG. 2 is executed to form a sacrificial sidewall 312 around the second sidewall 311 .

The thickness of the formed sacrificial sidewall 312 ranges from 200 to 400 angstroms. In this embodiment, the sacrificial sidewall 312 is silicon oxide. As another example, the sacrificial sidewall 312 may also be a polymer, such as photoresist.

Referring to FIG. 10 and FIG. 11 , step S7 in FIG. 2 is performed to form the sacrificial spacer 312 , and then etch the floating gate layer 302 located in the erasing gate region 40 to form the floating gate 313 . Specifically:

Referring to FIG. 10, a mask layer 314 is formed, which is a photoresist layer in this embodiment, and the mask layer 314 covers the surface of the sacrificial spacer 312 located in the word line region 50, the surface of the first dielectric layer 301 in the word line region 50, and hard mask layer 305 .

Referring to FIG. 11 , using the mask layer 314 as a mask, the floating gate layer 302 is etched to form a floating gate 313 . The first dielectric layer under the floating gate 313 is a floating gate dielectric layer, and its thickness range is The floating gate 313 and the underlying floating gate dielectric layer form a floating gate structure. In this embodiment, ion implantation may be performed on the substrate 300 using the mask layer 314 as a mask to form a source region (not shown).

Both the formation of the floating gate 313 and the formation of the source region above use the mask layer 314 as a mask, which simplifies the process steps and saves the process cost.

Referring to FIG. 11 , step S8 in FIG. 2 is performed to remove the sacrificial sidewall 312 located in the erasing gate region 40 , exposing the part of the floating gate covered by the sacrificial sidewall 312 .

The method of removing the sacrificial spacer 312 around the second spacer 311 and located in the erasing gate region 40 is wet etching, and the solution of the wet etching is hydrofluoric acid. In this embodiment, since the material of the first dielectric layer 301 and the material of the sacrificial spacer 312 are both silicon oxide, the removal of the sacrificial spacer 312 located in the erasing gate region 40 will remove the first part of the erasing gate region 40 at the same time. Medium layer 301.

It should be noted that, because the outermost layer of the second sidewall 311 in the present invention is the silicon nitride layer 311b, in the process of removing the sacrificial sidewall 312 of the erasing gate region 40, the second sidewall of the erasing gate region 40 Because the sidewall 311 is protected by the silicon nitride layer 311b, the thickness will not be reduced or the surface will be uneven, which effectively improves the uniformity of the second sidewall 311 and improves the programming uniformity of the discrete gate storage device.

After removing the sacrificial sidewall 312 located in the erase gate region 40 , the floating gate 313 covered by the sacrificial sidewall 312 is exposed, that is, a protrusion protruding from the second sidewall 311 is formed at the floating gate structure of the erase gate region 40 .

After the floating gate structure forms the protrusion, the mask layer 314 is removed.

Next, referring to FIG. 14 , step S9 in FIG. 2 is performed to form a tunneling dielectric layer 316 to cover the exposed floating gate portion, the substrate 300 of the erasing gate region 40 , and the first layer between two adjacent control gate structures 30 . Two sidewalls 311 , the thickness of the tunneling dielectric layer 316 is smaller than the thickness of the sacrificial sidewall 312 .

A specific method for forming the tunneling dielectric layer 316 includes: referring to FIG. 12 , forming a material layer 316 ′ of the tunneling dielectric layer by a deposition method. The material layer 316 ′ of the tunneling dielectric layer has higher requirements on film quality, and in this embodiment, it is a silicon oxide layer. Specifically, the formation method may be plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD). In this embodiment, low-pressure chemical vapor deposition is selected, and the material layer 316' of the tunnel dielectric layer has a thickness of here for

Referring to FIG. 13 and FIG. 14 together, a mask layer 317 is formed, which is a photoresist layer in this embodiment, to cover the erasing gate region 40 . Use the mask layer 317 as a mask to remove the material layer 316 ′ of the tunneling dielectric layer on the substrate of the word line region 50 , and the material layer 316 ′ of the tunneling dielectric layer on the hard mask layer 305 , which is located in the word line region 50 The sacrificial spacer 312 and the first dielectric layer 301 located in the word line region 50 . The removal is wet etching. The wet etching solution is hydrofluoric acid.

Afterwards, the mask layer 317 is removed to form a tunnel dielectric layer 316 . The thickness of the tunneling dielectric layer 316 is smaller than the lateral width of the floating gate protrusion.

It should be noted that, because the outermost layer of the second sidewall 311 in the present invention is a silicon nitride layer, in the process of removing the sacrificial sidewall 312 covering the surface of the word line region 50, the second sidewall 311 is due to nitrogen protection of SiC without being damaged, that is, the thickness of the second sidewall 311 will not be reduced or the surface of the second sidewall 311 is still flat, which effectively improves the uniformity of the second sidewall 311 and improves the discrete gate Programming Uniformity of Memory Devices.

Next, referring to FIG. 15 and FIG. 16 , step S10 in FIG. 2 is executed to form a word line 319 in the word line area 50 and an erasing gate 320 in the erasing gate area 40 .

After the tunneling dielectric layer 316 is formed, referring to FIG. 15 , a word line dielectric layer 318 is formed in the word line region 50 on the surface of the substrate 300. This embodiment is an oxide layer, and the thickness range of the word line dielectric layer 318 is Referring to FIG. 16 , a wordline (wordline: WL) 319 located on the wordline dielectric layer 318 and an erase gate 320 located on the tunnel dielectric layer 316 are formed on the wordline region 50 . The erasing gate 320 and the word line 319 are both polysilicon layers, which are formed by a low-pressure chemical vapor deposition process, and then the deposited polysilicon layer is subjected to photolithography and etching processes, and finally the device structure as shown in FIG. 16 is formed.

Wherein, it should be noted that the erasing gate 320 and the floating gate 313 have a lateral overlapping portion. For the formation process of the lateral overlapping part, please refer to step S6 to step S10: after forming the floating gate 313, remove the sacrificial sidewall 312 located in the erase gate region 40, exposing the part of the floating gate covered by the sacrificial sidewall 312, that is, A protrusion protruding from the second sidewall is formed at the floating gate structure of the erasing gate region 40 , and the thickness of the tunneling dielectric layer 316 formed on the protrusion is smaller than the lateral width of the floating gate protrusion. In this way, the erasing gate 320 and the floating gate structure formed on the tunnel dielectric layer 316 have a lateral overlapping portion, and the width of the overlapping portion ranges from The design of the lateral overlapping portion avoids increasing the number of tunneling electrons by increasing the erasing voltage in the prior art. In the present invention, the lateral overlap of the erasing gate 320 and the floating gate structure increases the contact area between the floating gate 313 and the tunneling dielectric layer 316, and between the tunneling dielectric layer 316 and the erasing gate 320, thereby increasing the number of tunneling electrons , so that the tunneling current in the tunneling dielectric layer increases, thereby increasing the erasing speed.

In other embodiments, after the formation of the floating gate 313 , in addition to removing the sacrificial sidewall 312 located in the erase gate region 40 , the second sidewall 311 may also be continuously removed to increase the area of the floating gate structure. Specifically, the silicon nitride layer located in the second sidewall 311 of the erasing gate region 40 can be removed first, and the silicon oxide layer inside it can be used as an etching stop layer, and then the second sidewall located in the erasing gate region 40 can be removed. The silicon oxide layer at 311 is removed, and the silicon nitride layer at the first spacer 309 serves as an etching stop layer. The wet etching solution for etching the silicon nitride layer located on the second sidewall 311 of the erasing gate region 40 is hot phosphoric acid, and the wet etching solution for the silicon oxide layer therein is hydrofluoric acid. It should be noted that when removing the silicon oxide layer of the second sidewall 311 around the first sidewall 309, the outermost layer of the first sidewall 309 is silicon nitride, which can protect the first sidewall 309 from damage, The uniformity of the surface of the first sidewall 309 is ensured, and the protection of the uniformity of the control gate structure by the first sidewall 309 is further strengthened. The programming uniformity of the discrete gate memory device is improved.

As the area of the raised platform of the floating gate structure increases, the area of the lateral overlapping portion of the erasing gate 320 and the floating gate 313 also increases, thereby increasing the number of tunneling electrons and improving erasing efficiency. It should be noted that even if the second sidewall is removed, the first sidewall also increases the isolation effect. At this time, the total thickness of the tunneling dielectric layer and the first sidewall is equal to the thickness of the existing tunneling oxide layer. That is, erasure efficiency and uniformity of the discrete gate memory device are improved.

It needs to be further explained that the formation of the first sidewall in the present invention not only makes the surface of the control gate structure uniform, but also improves the isolation effect between the control gate and the word line, and between the control gate and the erasing gate, and improves the The uniformity of programming and erasing, thereby improving the efficiency of programming and erasing.

Furthermore, a first spacer and a second sidewall are formed between the control gate and the word line to replace the single-layer spacer in the prior art, wherein the total thickness of the first sidewall and the second sidewall is the same as that of the prior art The side walls in are of the same thickness. A second spacer is formed between the floating gate and the word line to replace the single layer spacer in the prior art. When the split-gate storage device of the present invention enters the programming state, without affecting the programming efficiency, the internal structure of the sidewall between the control gate and the word line, between the floating gate and the word line is changed, and the isolation of the sidewall is increased. effect, thereby reducing the generation of leakage current, and further reducing the probability of leakage current entering the floating gate under the action of the control gate, that is, reducing the leakage between the word line and the floating gate, making it impossible to write changes A write change occurs in the cell to solve the write disturb problem during programming.

In addition, a first spacer, a second sidewall and a tunneling dielectric layer are formed between the control gate and the erasing gate to replace the tunneling oxide layer in the prior art, wherein the first sidewall, the second sidewall and the tunneling The total thickness of the dielectric layer is the same as that of the tunnel oxide layer in the prior art. While not affecting the erasing efficiency, the isolation effect of the side wall is increased, thereby reducing the generation of leakage current, thereby improving the erasing uniformity.

Furthermore, the second spacer fills the gap between the word line and the floating gate. The outermost layer of the second sidewall is silicon nitride, and the second sidewall will not be removed by an etching solution such as hydrofluoric acid during the process of removing the floating gate dielectric layer to form a word line dielectric layer; When removing the sacrificial sidewall, the second sidewall will not be removed by an etching solution such as hydrofluoric acid; when removing the tunnel dielectric layer on the word line region, the second sidewall will not be etched Etching solution such as hydrofluoric acid is removed, that is, the gap between the word line and the floating gate is protected from being corroded. When programming the split-gate memory, electrons in the channel region jump to the floating gate sidewall through the gap to reduce the influence on the programming current, which improves the uniformity of the programming current, thereby improving the efficiency and uniformity of programming.

Referring to FIG. 16, the present invention also provides a discrete gate storage device, including:

substrate 300;

The floating gate structure on the substrate 300, the control gate structure 30 on the floating gate structure and the first sidewall 309, the first sidewall 309 is located around the control gate structure 30; two adjacent The area between two control gate structures 30 is the erasing gate region 40; the side opposite to the erasing gate region 40 of two adjacent control gate structures 30 is the word line region 50; the floating gate structure includes a floating gate A dielectric layer and a floating gate 313 on the floating gate dielectric layer, the control gate structure 30 includes a control gate dielectric layer 306 and a control gate 307 on the control gate dielectric layer 306 .

There is a second sidewall 311 around the floating gate structure and the first sidewall 309, and the floating gate structure has a boss protruding from the second sidewall 311 on the side of the erase gate region 40; the tunneling dielectric layer 316 Covering the boss, and covering the substrate of the erasing gate region 40 and the second sidewall 311 between two adjacent control gate structures 30, the thickness of the tunneling dielectric layer 316 is smaller than the thickness of the boss;

a word line dielectric layer 318 on the word line region 50 and a word line 319 on the word line dielectric layer 318;

The tunneling dielectric layer 316 located on the erasing gate region 40 and the erasing gate 320 covering the tunneling dielectric layer 316 .

Wherein, the first sidewall 309 includes a silicon oxide layer 309a and a silicon nitride layer 309b formed on the silicon oxide layer 309a. The second sidewall 311 includes a silicon oxide layer 311a and a silicon nitride layer 311b formed on the silicon oxide layer 311a.

The thickness range of the word line dielectric layer 318 is The thickness range of the floating gate dielectric layer is The thickness range of the floating gate is The thickness range of the control grid 307 is The erasing gate 320 has a lateral overlapping portion with the floating gate structure, and the width range of the overlapping portion is The lateral overlapping portion effectively increases the number of tunneling electrons and improves the erasing speed.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use the methods disclosed above and technical content to analyze the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made in the technical solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (12)

1. a formation method for discrete grid storage device, is characterized in that, comprising:

Substrate is provided, described substrate is formed with first medium layer, floating gate layer, second dielectric layer and control grid layer successively;

Etch described control grid layer and second dielectric layer formation control grid structure, the region between adjacent two control gate structures is erasing grid region, and the side that adjacent two control gate structures deviate from described erase gate is wordline district;

The first side wall is formed at described control gate structure periphery;

After forming the first side wall, remove the floating gate layer be positioned in wordline district;

After removing the floating gate layer be positioned in wordline district, around the first side wall, form the second side wall;

Formed around described second side wall and sacrifice side wall;

Formed after sacrificing side wall, remove the floating gate layer being positioned at erasing grid region, form floating boom;

Remove the described sacrifice side wall being positioned at erasing grid region, expose the floating gate portion of sacrificing side wall and covering;

Form tunneling medium layer, cover the second side wall between the floating gate portion exposed, the substrate wiping grid region, adjacent two control gate structures, the thickness of described tunneling medium layer is less than the thickness of sacrificing side wall;

Form wordline in wordline district, form erase gate in erasing grid region.

2. the formation method of discrete grid storage device according to claim 1, it is characterized in that, the material of described floating gate layer and described control grid layer is all polysilicon.

3. the formation method of discrete grid storage device according to claim 1, is characterized in that, the first side wall comprises silicon oxide layer and is formed at the silicon nitride layer on described silicon oxide layer.

4. the formation method of discrete grid storage device according to claim 1, is characterized in that, the second side wall comprises silicon oxide layer and is formed at the silicon nitride layer on described silicon oxide layer.

5. the formation method of discrete grid storage device according to claim 1, it is characterized in that, the material of described sacrifice side wall is silica or polymer.

6. the formation method of discrete grid storage device according to claim 1, is characterized in that, after removing described sacrifice side wall, also comprise step: the second side wall removing erasing grid region.

7. the formation method of discrete grid storage device according to claim 1, it is characterized in that, after forming the first side wall, also step is comprised: with described first side wall for mask before removing the floating gate layer be positioned in wordline district, ion implantation is carried out to the substrate in described wordline district, to carry out the adjustment of the threshold voltage in wordline district.

8. the formation method of discrete grid storage device according to claim 1, is characterized in that, after forming described tunneling medium layer, before wordline district forms wordline, also comprises step: remove the first medium floor being positioned at described wordline district.

9. the formation method of discrete grid storage device according to claim 8, is characterized in that, removes after being positioned at the first medium floor in described wordline district, and the substrate being also included in described wordline district forms wordline dielectric layer.

10. a discrete grid storage device, is characterized in that, comprising:

Substrate;

Be positioned at the floating gate structure on described substrate, be positioned at the control gate structure in described floating gate structure and the first side wall, described first side wall is positioned at described control gate structure periphery; Region between adjacent two control gate structures is erasing grid region; The side that adjacent two control gate structures deviate from described erase gate is wordline district; Described floating gate structure comprises floating gate dielectric layer and is positioned at the floating boom on floating gate dielectric layer, and described control gate structure comprises control gate dielectric layer and is positioned at the control gate on control gate dielectric layer;

Have the second side wall around described floating gate structure and described first side wall, described in erasing side, grid region, floating gate structure has the boss of outstanding second side wall;

Tunneling medium layer, cover the second side wall between described boss, the substrate in erasing grid region, adjacent two control gate structures, the thickness of described tunneling medium layer is less than the width of boss;

The wordline being positioned at the wordline dielectric layer in described wordline district and being positioned on described wordline dielectric layer;

Be positioned at the erase gate of the described tunneling medium layer of covering on described erasing grid region.

11. discrete grid storage devices as claimed in claim 10, is characterized in that, described first side wall comprises silicon oxide layer and is formed at the silicon nitride layer on described silicon oxide layer.

12. discrete grid storage devices as claimed in claim 10, is characterized in that, described second side wall comprises silicon oxide layer and is formed at the silicon nitride layer on described silicon oxide layer.