CN103631357B - Power management system and power management method - Google Patents

Abstract

The present invention provides a power management system. The system includes: a display device; a graphics processor; a timing controller including a video frame buffer; and a monitoring control unit for monitoring multiple bus activities of a bus where the graphics processor is located, and filtering multiple graphics processing activities corresponding to the graphics processor from the bus activities, wherein the monitoring control unit also estimates an idle time period of the graphics processor based on the graphics processing activities, wherein the monitoring control unit also controls the graphics processor to burst write multiple images to the video frame buffer, so that the timing controller is sufficient to play the images written by the graphics processor in the display device within the idle time period to perform automatic panel update.

Description

Power management system and power management method

technical field

The present invention relates to power management, in particular to a power management system and method for automatically updating a control panel (Panel selfrefresh).

Background technique

In traditional display technology, it often consumes a lot of power to use the processor to support the screen to display the picture, because the traditional display device panel still reads the display picture from the system memory or the graphics processor (such as GPU) when the display picture is not updated , and send an interrupt signal to the graphics processor. However, with the advancement of technology, Intel has developed the Panel Self Refresh (Panel Self Refresh) technology in the embedded DisplayPort standard (embeddedDisplayPort, eDP) version 1.3, which means that when users browse websites or read e-books, because Screen content is usually static. Therefore, when the display device panel does not update the picture, it will only use the data in the built-in memory of the display device panel and automatically limit the screen refresh rate (refresh rate), and no longer read the display screen of the system memory or the graphics processor, and Reduces interrupts to 30 times per second (depending on screen update rate) to reduce power consumption.

Figure 1 is a simplified functional block diagram showing a conventional power management system that complies with the eDP 1.3 standard and can automatically update the control panel. As shown in FIG. 1 , the power management system 10 includes a graphics processor 20 and a display device panel 30, wherein the display device panel 30 further includes a timing controller (T-CON) 40, a display device 50 and a backlight module 60 . The graphics processor 20 includes a transmitting end 21 for transmitting the display frame generated by the graphics processor 20 to the timing controller 40 . The graphics processing unit 20 can be a graphics processing unit (GPU) on an independent display card, or a graphics processing unit (GPU) on a mainboard (Mainboard) (such as Intel i5, i7CPU). processor. The timing controller 40 at least includes a receiving end 41 , a pixel arrangement unit 42 , a display device interface (LCD interface) 43 , a video frame buffer (Video frame buffer) 44 and a backlight control unit (Backlight control unit) 45 .

In simple terms, the timing controller 40 receives the display picture from the graphics processor 20 through the receiving terminal 41, and then rearranges the pixels of the received picture through the pixel arrangement unit 42 and stores the rearranged pixels in the video frame buffer. 44. The display device interface 43 reads picture data from the video frame buffer 44 through the pixel arrangement unit 42 , and controls the column driver 51 and the row driver 52 in the display device 50 to display the read picture. The backlight control unit 45 is used to control the switch of the backlight module 60 .

It should be noted that, in the conventional timing controller 40 , the size of the video frame buffer 44 is often only the size of one video frame. Taking a full-resolution high-definition picture (Full HD) as an example, its size may be 1920*1080*3=6220800bytes (about 6Mbytes). The timing controller 40 may also optionally include an image encoder and an image decoder (not shown), wherein the image encoder encodes the display images received by the receiving end 41, and then passes the encoded display images through The pixel arrangement unit 42 is stored in the video frame buffer 244 . For details, please refer to "An LCD Driver with on-chip framebuffer and 3times image compression" SPIE-IS&T 2008, Vol.6807, 68070H-1.

When the timing controller 40 performs panel automatic update (for example, when it is in a still picture), it will directly take out the stored picture data from the video frame buffer 44 and directly play it on the display device 50. At this time, the graphics processor 20 can be in A low power state to save power. In addition, when the graphics processor 20 detects that there is new image data (for example, from typing a key on the keyboard or moving the mouse), the graphics processor 20 will wake up the transmitting end 21 and transmit a piece of new image data to the timing control Video frame buffer 44 in device 40.

In the traditional power management system 10, because the graphics processor 20 often receives an interrupt signal from the timing controller 40 or receives an interrupt signal from an external device, the graphics processor 20 must often be woken up to be in a working state (such as ACPI S0 state specified by the standard). In other words, the graphics processor 20 is often in a high power consumption state, which cannot effectively reduce the power consumption of the power management system 10 . Therefore, there is an urgent need for a power management system to reduce power consumption more effectively, so as to achieve a longer service time.

Contents of the invention

The invention provides a power management system. The system includes: a display device; a graphics processor; a timing controller including a video frame buffer; and a monitoring control unit for monitoring a plurality of bus activities of a bus where the graphics processor is located, and by the bus activity filtering a plurality of graphics processing activities corresponding to the graphics processor, wherein the monitoring control unit also estimates an idle time period of the graphics processor according to the graphics processing activities, and controls the graphics processor to be at a low level during the idle time period Power consumption state; wherein the monitoring control unit also controls the graphics processor to burst write multiple images to the video frame buffer, so that the timing controller is sufficient to play the images written by the graphics processor on the display device during the idle time period. Perform panel auto-update.

The invention also provides a power management system. The system includes: a display device; a graphics processor, including a monitoring control unit, which is used to monitor a plurality of bus activities of a bus where the graphics processor is located, and filter the bus activities corresponding to the graphics processor a plurality of graphics processing activities; and a timing controller; wherein the monitoring control unit also estimates an idle time period of the graphics processor according to the graphics processing activities, and controls the graphics processor to be in an idle time period during the idle time period In a low power consumption state, the monitor control unit also controls the graphics processor to burst write multiple images to the video frame buffer, so that the timing controller is sufficient to play the graphics processing on the display device during the idle time the images written by the device.

The present invention also provides a power management method for a power management system, the power management system includes a graphic processor, a monitoring control unit, a timing controller and a display device. The method includes: using the monitoring control unit to monitor multiple bus activities of a bus where the graphics processor is located, and filtering multiple graphics processing activities corresponding to the graphics processor from the bus activities; using the monitoring control unit Estimating an idle time period of the graphics processor according to the graphics processing activities, and controlling the graphics processor to be in a low power consumption state during the idle time period; using the monitoring control unit to control the graphics processor burst write A plurality of images are sent to a video frame buffer of the timing controller, so that the timing controller is sufficient to play the images written by the graphics processor on the display device during the idle time period for automatic panel update.

Description of drawings

Figure 1 is a simplified functional block diagram showing a conventional power management system that complies with the eDP 1.3 standard and can automatically update the control panel.

FIG. 2A is a schematic functional block diagram showing a power management system 200 according to an embodiment of the present invention.

FIG. 2B is a schematic functional block diagram showing a power management system 200 according to another embodiment of the present invention.

FIG. 3A is a schematic diagram showing interrupt signals from various devices to the bus on which the graphics processor resides according to an embodiment of the invention.

FIG. 3B is a schematic diagram showing interrupt signals rearranged and grouped in FIG. 3A .

FIG. 3C is a schematic diagram showing a wake-up signal sent by the monitoring control unit 222 according to an embodiment of the invention.

FIG. 4 is a state diagram showing a state machine of the monitoring control unit 222 according to an embodiment of the invention.

FIG. 5 is a flowchart showing a power management method according to an embodiment of the invention.

[Description of main component labels]

10. 200 ~ power management system; 20. 220 ~ graphics processor;

21, 221～transmitter; 30, 230～display device panel;

40, 240～sequence controller; 41, 241～receiving end;

42, 242～pixel arrangement unit; 43, 243～display device interface;

44, 244～video frame buffer; 45, 245～backlight control unit;

50, 250～display device; 51, 251～column driver;

52, 252～row driver; 60, 260～backlight module;

222～monitoring control unit;

310, 311, 312, 313, 320, 330, 340 ~ interrupt signal;

350, 360～pulse signal; 410－450～status.

detailed description

In order to make the above objects, features and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below together with the accompanying drawings.

FIG. 2A is a schematic functional block diagram showing a power management system 200 according to an embodiment of the present invention. As shown in FIG. 2A, the power management system 200 includes a graphics processor 220 and a display device panel 230, wherein the display device panel 230 further includes a timing controller (T-CON) 240, a display device 250 and a backlight module 260 . The graphics processor 220 includes a transmitting end 221 for transmitting the display frame generated by the graphics processor 220 to the timing controller 240 . In one embodiment, the graphics processor 220 may be a graphics processing unit (GPU) on a separate graphics card. In another embodiment, the graphics processor 220 may be a graphics processor located in a central processing unit (CPU) (such as Intel i5, i7 CPU) on a mainboard. The timing controller 240 includes at least a receiving end 241, a pixel arrangement unit 242, a display device interface (LCD display interface) 243, a video frame buffer (Video frame buffer) 244 and a backlight control unit (Backlight control unit) 245 .

In simple terms, the timing controller 240 receives multiple images from the graphics processor 220 through the receiving end 241, and then rearranges the pixels of the received multiple images through the pixel arrangement unit 242 and rearranges the pixels of the rearranged multiple images. The pixels are stored in video frame buffer 244 . The display device interface 243 sequentially reads the pixel data of the images from the video frame buffer 244 through the pixel arrangement unit 242, and controls the column driver 251 and the row driver 252 in the display device 250, so as to sequentially display the read multiple images. images. The backlight control unit 245 is used to control the switch of the backlight module 260 . It should be noted that the video frame buffer 244 of the present invention is different from the video frame buffer 44 in the conventional power management system 10. The video frame buffer 44 can only store one image, while the video frame buffer 244 of the present invention can Store multiple images (eg 10 or 30 images, the number of which can be adjusted). In other words, the video frame buffer 244 of the present invention can store 10 images at a time for automatic updating of the panel.

FIG. 2B is a schematic functional block diagram showing a power management system 200 according to another embodiment of the present invention. In one embodiment, the power management system 200 further includes a monitoring control unit 222 for monitoring the bus activity of the bus (such as the system bus or PCI-E bus) where the graphics processor 220 is located. In one embodiment, the monitoring control unit 222 may be a microcontroller (Microcontroller unit) outside the graphics processor 220, as shown in FIG. 2A. In another embodiment, the monitoring control unit 222 can also be built in the graphics processor 220, as shown in FIG. 2B. In an embodiment, the monitoring control unit 222 may also be a software plug-in supported by specific hardware, but the present invention is not limited thereto.

The timing controller 240 regularly sends an interrupt signal to the graphics processor 220 when performing automatic panel update (PSR). SATA and SDIO interface devices) interrupt signals are rearranged, and the rearranged interrupt signals are grouped and distributed immediately after the interrupt signals regularly sent by the timing controller 240 . For example, the original bus active state of the graphics processor 220 , that is, various interrupt signals before being rearranged, is shown in FIG. 3A . Taking the picture update rate of 60 pictures per second as an example, the timing controller 240 needs 30 complete pictures per second, and each complete picture can be divided into a top field and a bottom field. Then, the timing controller 240 sequentially performs de-interlacing on the upper field and the lower field of each complete frame so that the display device 250 has a frame update rate of 60 frames per second. In other words, the timing controller 240 needs to obtain a complete frame from the graphics processor 220 every 1/30 second, that is, an interrupt signal is sent to obtain a frame.

FIG. 3A is a schematic diagram showing interrupt signals from various devices to the bus on which the graphics processor resides according to an embodiment of the invention. FIG. 3B is a schematic diagram showing interrupt signals rearranged and grouped in FIG. 3A . FIG. 3C is a schematic diagram showing a wake-up signal sent by the monitoring control unit 222 according to an embodiment of the invention. It can be seen from FIG. 3A that the time interval between the interrupt signals 310 and 320 sent by the timing controller 240 to the graphics processor 220 is 1/30 second (that is, the time unit is about millisecond level), while the interrupt signals from other The interrupt signals 311-313 of the device could have been distributed among the intervals of 1/30 second. The interrupt signal rearranged by the monitoring control unit 222 is as shown in FIG. 3B, wherein the time interval between the interrupt signals 330 and 340 sent by the timing controller 240 to the graphics processor 220 is also 1/30 second. It should be noted that Interrupt signals with the same label in FIG. 3B all come from the same device, and the rearranged interrupt signals are only for illustration purposes, and bus activities that are not related to the graphics processor will be filtered out (such as interrupt signals 311, 312), and only Interrupt signals associated with the graphics processor 220 (eg, interrupt signals 310, 320, 313) are retained. As shown in FIG. 3C , the monitoring control unit 222 sends a wake-up signal to the graphics processor 220, so that the graphics processor 220 is in a working state when the wake-up signal is a high logic level (high logic level), wherein the graphics processor 220 is in the working state. The voltage in the working state is, for example, 1W. When the wake-up signal is low logic level (low logic level), then let the graphics processor 220 be in a low power consumption state (such as a sleep state), wherein the voltage of the graphics processor 220 in the low power consumption state is, for example, 0.001w . In more detail, because the interrupt signals from each device to the graphics processor 220 will be rearranged and grouped by the monitoring control unit 222, and distributed immediately after the interrupt signal sent from the timing controller 240 Processing together, during this period with many interrupt signals (such as the pulse signals 350 and 360 ), the graphics processor 220 can be in the working state, so as to centralize the operation control of each device. When the wake-up signal is in a low logic state, the graphics processor 220 enters a low power consumption state. When the wake-up signal is in a high logic state, in addition to making the graphics processor 220 work, it can also be used as a burst control signal to increase the operating frequency of the graphics processor 220 . Furthermore, if the preset operating frequency of the graphics processor 220 is 1GHz, when the wake-up signal is in a high logic state, the monitoring control unit 222 will increase the operating frequency of the graphics processor 220 to 1.3GHz (not limited, adjustable ), so that the graphics processor 220 can burst a plurality of consecutive images (for example, 10 or 30 images) into the video frame buffer 244 in a short time.

Taking the PCI Express×4 bus as an example, its bandwidth can reach 800MBytes/sec, plus the operating frequency of the graphics processor 220 is 1GHz, then the time it takes for the graphics processor 220 to perform burst writing of images to the video frame buffer 244 It is only tens of microseconds (μs), and the interrupt signal sent by the timing controller 240 to the graphics processor 220 is about every 33 milliseconds (1/30 second). In terms of time ratio, the graphics processor 220 takes a very small percentage of time to execute the burst image writing operation, so the graphics processor 220 can be in a low power consumption state most of the time, so as to save power.

Continuing the foregoing embodiments, the main three functions of the monitoring control unit 222 of the present invention can be summarized: (1) monitor all activities of the bus (PCI-E bus) where the graphics processor 220 is located and filter all the activities related to the graphics processor 220; (2) controlling the graphics processor 220 to burst write multiple images to the video frame buffer 244, so as to automatically update the panel; (3) controlling the graphics processor 220 to enter a low power consumption state.

In one embodiment, the monitoring control unit 222 continuously monitors the activity of the bus, and determines whether the number of images stored in the video frame buffer 244 for automatic panel updating is insufficient. To put it simply, the principle of auto-updating the panel is not to make the user feel the delay of the screen. Take Microsoft's "Always On Always Connected" (Always On Always Connected) standard requirement as an example. time) has an upper limit of 300 milliseconds. In fact, the wake-up time of the graphics processor 220 may be faster, for example, 100 milliseconds.

For example, the monitoring control unit 222 controls the graphics processor 220 to burst write 30 images to the video frame buffer 244, and the display device 250 has a frame update rate of 60 images per second, which means that the real-time sequence controller 240 30 complete pictures are required, and each complete picture can be divided into a top field and a bottom field, and then the timing controller 240 sequentially compares the top field and bottom field of each complete picture The fields are de-interlaced so that the display device 250 has a frame refresh rate of 60 frames per second. Therefore, it takes 1 second for the display device to read the stored 30 frames, and the average interval for reading each frame is 33 milliseconds. If the bus where the graphics processor 220 is located is still inactive after 20 images (or 660 milliseconds), because 660 milliseconds plus the wake-up time of the graphics processor 220 of 300 milliseconds is close to the automatic update of the panel, the display data is insufficient. The monitoring control unit 222 needs to forcibly wake up the graphics processor 220 to write the display image to the video frame buffer 244 in a burst, so as to avoid insufficient display data in the automatic update of the panel.

To put it simply, the monitoring control unit 222 needs to judge in advance whether there will be insufficient display images before the graphics processor 220 is fully awakened next time. frame buffer 244 . If not, the monitoring control unit 222 wakes up the graphics processor 220 to execute instructions from the application program or the operating system. For the user, no matter in which case, it feels that the graphics processor 220 is always on.

FIG. 4 is a state diagram showing a state machine of the monitoring control unit 222 according to an embodiment of the invention. In state 410 , the monitoring control unit 222 monitors the activity of the bus on which the graphics processor 220 resides (eg, the PCI-Express bus) and screens activities related to the graphics processor 220 . If no related activity is displayed, return to state 410 , and the monitoring control unit 222 continuously monitors the activity of the bus where the graphics processor 220 is located. In state 420, the monitoring control unit 222 can perform the following functions: (a) estimate the idle time period (idling time period) T _idle of the graphics processor 220; (b) control the graphics processor 220 to burst write a sufficient amount of display data to the video frame buffer 244, sufficient for automatic panel updates between estimated periods of idle time; (c) controlling the graphics processor 220 to enter a low power state.

In state 430, the monitoring control unit 222 monitors the following conditions: (d) run-out-of-display event and (e) graphics processing activity (GPU activity), such as initiated by an application program or an operating system graphics processing activity. When no event is detected, return to state 430 , and the monitoring control unit 222 continuously monitors the display data insufficient event and the activity event of the graphics processor 220 . When an event is detected, the state 440 is entered, and the monitoring control unit 222 sets the wake-up signal to a high logic state, so that the graphics processor 220 enters the working state from the low power consumption state. If the graphics processor 220 enters the working state due to (d) insufficient display data event, return to state 420 . If the GPU 220 enters the active state due to (e) an activity event of the GPU 220 , enter state 450 . In state 450 , the graphics processor 220 can start processing graphics processing activities initiated by applications or the operating system within a wake-up time (eg, 300 milliseconds).

FIG. 5 is a flowchart showing a power management method according to an embodiment of the invention. In step S500 , the monitoring control unit 222 monitors multiple bus activities of a bus on which the graphics processor 220 resides, and filters multiple graphics processing activities corresponding to the graphics processor 220 from the bus activities. In step S510 , the monitoring control unit 222 estimates an idle time period of the graphics processor 220 according to the graphics processing activities. In step S520, the monitoring control unit 222 controls the graphics processor to burst write multiple images to a video frame buffer of the timing controller, so that the timing controller is sufficient to play on the display device 250 during the idle time period The images written by the graphics processor 220 are used for panel auto-update.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The scope of protection of the present invention should be defined by the appended claims.

Claims (7)

1. A power management system, comprising: a display device; a graphics processor; a timing controller; and A monitoring control unit, used to monitor multiple bus activities of a bus where the graphics processor is located, and filter multiple graphics processing activities corresponding to the graphics processor from the multiple bus activities; Wherein the monitoring control unit further estimates an idle time period of the graphics processor according to the plurality of graphics processing activities, and controls the graphics processor to be in a low power consumption state during the idle time period; Wherein the monitoring control unit also controls the graphics processor to write bursts of multiple images to a video frame buffer in the timing controller, so that the timing controller is sufficient to play the video on the display device during the idle time period The plurality of images written by the graphics processor for panel auto-update, Wherein the monitoring control unit sends a wake-up signal to the graphics processor according to the multiple graphics processing activities, so as to make the graphics processor enter a working state to burst write the multiple images to the video frame buffer, Wherein when the graphics processor enters the working state, the monitoring control unit also controls the graphics processor to operate in the working state with a first operating frequency, wherein the first operating frequency is a predetermined operation higher than the working state frequency. 2. The power management system according to claim 1, wherein the monitoring control unit further determines whether the multiple images stored in the video frame buffer are sufficient for the timing controller to automatically update the panel during the idle time period ; Wherein when the multiple images stored in the video frame buffer are not enough for the timing controller to automatically update the panel during the idle time period, the monitoring control unit also forcibly sends the wake-up signal to the graphics processor, thereby Let the graphics processor enter a working state. 3. The power management system according to claim 1, wherein the monitoring control unit further determines whether the plurality of graphics processing activities are initiated by an application program or an operating system; When the plurality of graphics processing activities are initiated by the application program or the operating system, the monitoring control unit also forcibly sends the wake-up signal to the graphics processor, so that the graphics processor enters a working state. 4. A power management system, comprising: a display device; A graphics processor, including a monitoring control unit, used to monitor multiple bus activities of a bus where the graphics processor is located, and filter multiple graphics processing activities corresponding to the graphics processor from the multiple bus activities; as well as a timing controller; Wherein the monitoring control unit further estimates an idle time period of the graphics processor according to the plurality of graphics processing activities, and controls the graphics processor to be in a low power consumption state during the idle time period; Wherein the monitor control unit also controls the graphics processor to write multiple images in a burst to a video frame buffer, so that the timing controller is sufficient to play the images written by the graphics processor on the display device during the idle time The multiple images, Wherein the monitoring control unit sends a wake-up signal to the graphics processor according to the multiple graphics processing activities, so as to make the graphics processor enter a working state to burst write the multiple images to the video frame buffer; and when The graphics processor enters the working state, and the monitoring control unit also controls the graphics processor to operate in the working state with a first operating frequency, wherein the first operating frequency is higher than a predetermined operating frequency of the working state. 5. The power management system according to claim 4, wherein the monitoring control unit further determines whether the multiple images stored in the video frame buffer are sufficient for the timing controller to automatically update the panel during the idle time period ; Wherein when the multiple images stored in the video frame buffer are not enough for the timing controller to automatically update the panel during the idle time period, the monitoring control unit also forcibly sends the wake-up signal to the graphics processor, thereby Let the graphics processor enter a working state. 6. The power management system according to claim 4, wherein the monitoring control unit further determines whether the plurality of graphics processing activities are initiated by an application program or an operating system; When the plurality of graphics processing activities are initiated by the application program or the operating system, the monitoring control unit also forcibly sends the wake-up signal to the graphics processor, so that the graphics processor enters a working state. 7. A power management method for a power management system, the power management system comprising a graphics processor, a monitoring control unit, a timing controller and a display device, the method comprising: Using the monitoring control unit to monitor a plurality of bus activities of a bus where the graphics processor is located, and filtering a plurality of graphics processing activities corresponding to the graphics processor from the plurality of bus activities; estimating an idle time period of the graphics processor according to the plurality of graphics processing activities by the monitoring control unit; Utilize the monitoring control unit to control the graphics processor to burst write multiple images to a video frame buffer of the timing controller, so that the timing controller is sufficient to play the graphics processing on the display device during the idle time period The multiple images written by the controller for automatic panel update, Using the monitoring control unit to send a wake-up signal to the graphics processor according to the multiple graphics processing activities, so that the graphics processor enters a working state to burst write the multiple images to the video frame buffer; When the graphics processor enters the working state, the monitoring and control unit is used to control the graphics processor to operate in the working state with a first operating frequency, wherein the first operating frequency is a predetermined operating frequency higher than the working state .