CN103631315A - Clock design method facilitating timing sequence repair - Google Patents

Abstract

The invention discloses a clock design method facilitating timing sequence repair. The clock design method comprises the following steps: (1) analyzing clock distribution of the whole design, wherein the clock distribution comprises each physical partition, and the clock domain scale, distribution and data interaction situation between the physical partitions; (2) according to the clock distribution, determining the number and adjusting ranges of clock adjusters inside each physical partition; (3) inserting the clock adjusters into corresponding points; (4) analyzing the whole clock structure from the top layer to obtain the actual delay of each clock branch, setting the adjusting values of the clock adjusters as needed, and therefore balancing the whole clock tree. According to the clock design method, the time for the physical design can be shortened, and the product design cycle is shortened.

Description

Be convenient to the clock design method that sequential is repaired

Technical field

The present invention relates to use the large scale integrated circuit design field of stratification realization flow, particularly relate to a kind of clock design method that sequential is repaired of being convenient to.

Background technology

Integrated circuit (IC) products has obtained general application now in daily life, greatly facilitates people's clothing, food, lodging and transportion--basic necessities of life.Along with continuous development, increasing function is integrated in the middle of chip piece, and the scale of integrated circuit is thereupon increasing, brings very large challenge to the physics realization of circuit, comprises more design times, and more powerful soft hardware equipment is supported etc.Under limited hardware-software resource, stratification physical Design flow process is used in the middle of increasing project.

It is excessive that stratification physical Design flow process not only can solve design, and the problem that software and hardware cannot be supported, can also shorten design time within the specific limits.This flow process is that chip design is divided into a lot of physical division (partition), and the physical Design of all physical division can be carried out simultaneously, finally at top layer, restrains.Because the physical Design of each physical division was independently carried out with the time, so that the timing closure of top layer becomes is very slow, particularly the difference of the time delay of Clock Tree causes the clock delay between physical division poor very large, thereby makes sequential become very poor.Physical Design person has between bottom and top layer, repeatedly repeatedly analyze and intervene, and carrys out the Clock Tree of the whole design of balance.The physical Design time that repeatedly lengthened greatly repeatedly, make the design cycle of product elongated.How to reduce between bottom and top layer is one of subject matter shortening the product design cycle repeatedly.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of clock design method that sequential is repaired of being convenient to, and can reduce the physical Design time, reduces the product design cycle.

For solving the problems of the technologies described above, the clock design method of being convenient to sequential reparation of the present invention, comprises the steps:

Step 1, analyzes the Clock Distribution of whole design, comprising: each physical division, and the clock zone scale between each physical division, distribution and data interaction situation;

Step 2, determines number and the range of adjustment of each physical division internal clocking regulator according to Clock Distribution;

Step 3, inserts clock controller at corresponding point;

Step 4, analyzes whole timing topology from top layer, obtains the actual time delay of each clock branch, and the regulated value of clock controller is set according to demand, thus the whole Clock Tree of balance.

Sequential is the basic guarantee that chip can work with the performance of expectation, and what guarantee sequential is correctly one of important process of back-end realization.Increasing when chip-scale, stratification realization flow is the necessary means that shortens the chip back-end realization cycle.The present invention provides a kind of clock design method that sequential is repaired of being convenient to for stratification realization flow, mainly in clock branch, adding clock controller, and by configuration register, controlled the value of time delay, thereby reach the effect of clock delay between each physical division of balance, be beneficial to top layer timing closure; Can reduce bottom and the top layer number of occurrence, thereby reduce the physical Design time, reach the object that reduces the product design cycle.

Accompanying drawing explanation

Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:

Fig. 1 is the structural drawing of design module D;

Fig. 2 is clock controller schematic diagram;

Fig. 3 is the schematic diagram that adds clock controller.

Embodiment

Shown in Figure 1, in design module D, there is a clock zone osc_clk, three physical division PA, PB, PC.

Suppose that osc_clk is system clock, by clock generator, produced, from top layer, enter PA and PB, and enter PC via PA.Tri-physical division of PA, PB and PC have different scale, and wherein PC is largest, and PB takes second place, and PA is minimum.The time delay of considering Clock Tree has certain relation with the scale of clock zone, supposes that the Clock Tree time delay of PA, PB, PC inside is respectively Dca, Dcb, Dcc, so Dca<Dcb<Dcc.Although the sequential of each physical division inside is not subject to the impact of these clock delays, but, because the difference of Dca, Dcb, Dcc, cause the path across physical division, interface path namely, there is larger delay inequality in the clock of the register of its Origin And Destination, thereby causes a large amount of sequence problems, causes the timing closure difficulty of top layer.

In large scale integrated circuit design, this interface path is a lot, directly on data path, carrying out sequential reparation can cause area to increase sharply, and, when on Clock Tree, the clock delay difference of two leaf nodes surpasses certain value, even if do not consider the problem of area, only on data path, make great efforts also cannot reach the object of timing closure, so, should set about from root, at top layer, from overall angle, remove rebalancing Clock Tree.General way is: first do the Clock Tree of each physical division, make clock convergence; Do again top layer Clock Tree, analyze the sequential of whole design, judge the clock delay gap between each physical division; Then enter bottom and find relevant Clock Tree branch, guaranteeing not destroy under the prerequisite of the inner sequential of physical division, according to the resulting data of top layer, adopt the mode of increase and decrease clock buffer to adjust Clock Tree time delay; Return top layer analysis, so repeatedly, until the timing closure of whole design.But this method has two shortcomings:

1, the Clock Tree branch of physical division is difficult to location, particularly Clock Tree structure is more complicated, and these branches are more, determines that these branches are just more difficult after realizing, and nodename is because different implementation procedures has its different name, therefore must spend more time and manpower.

2, from physical division to top layer, return the number of occurrence of physical division uncontrollable.The time delay adjusted value of physical division level is to estimate from top layer analysis, and bottom layer realization has its uncertainty, so final real added time delay and theoretical value have certain deviation, need repeatedly repeatedly to adjust, particularly when design is complicated, the number of occurrence will be a lot, and the whole timing closure cycle is oversize.

In order to solve above-mentioned two problems, can simplify this process with a kind of clock controller CR, the structured flowchart of clock controller CR is as shown in Figure 2.

Clock controller CR is a circuit that can regulate clock delay, input clkin is being output as clkout after a series of No. two selector switch MX0～MXn, and can be determined by configuration register through the number of Er road selector switch, like this, by the value of regulating allocation register, can reach the object that changes clock delay.Add after a clock controller CR the minimum time delay that can increase Yi Ge No. bis-selector switchs of relevant clock delay.

As shown in Figure 3, on the crucial clock node of each physical division PA, PB and PC inside, insert respectively clock delay regulator CRa, a CRb and CRc; So, when top layer carries out time series analysis, can regulate according to actual conditions the value of the configuration register of each clock delay regulator, sequential situation after being directly adjusted, back-end realization flow process need not be carried out again and desirable clock balance can be obtained, reduce the number of occurrence, shortened the cycle of timing closure while realizing.

According to above analysis, can adopt following technical scheme to realize the described clock design method that sequential is repaired of being convenient to: the Clock Distribution of analyzing whole design, according to Clock Distribution, determine number and the range of adjustment of each physical division internal clocking regulator, insert clock controller, from top layer, analyze timing topology, obtain the actual time delay of each clock branch, the regulated value of clock controller is set according to demand, thus the whole Clock Tree of balance.Its concrete steps are as follows:

Step 1, analyze the Clock Distribution of whole design, comprising: the clock zone scale between physical division and each physical division, distribution and data interaction situation, assess the Clock Tree time delay of each clock zone.

Step 2, according to Clock Distribution, determine the inner needed clock controller number of each physical division, insertion point and range of adjustment, range of adjustment has determined the figure place of corresponding configuration register.

Step 3, at corresponding point, insert clock controller.

Step 4, from top layer, analyze the clock sequential of whole design, obtain the actual time delay of each clock branch, the configuration register of clock controller is set according to demand, adjust its clock delay, thereby the whole Clock Tree of balance makes timing closure.

In addition, if in the design later stage, because cause specific need to be changed timing topology, and when change can have influence on Clock Tree balance, also there is good regulating action, as long as the change of clock delay does not exceed the scope of clock controller, by revising the configuration register value of clock controller, also can obtain the Clock Tree of a new balance, to meet sequential.

By embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (1)

1. be convenient to the clock design method that sequential is repaired, it is characterized in that, comprise the steps:

Step 1, analyzes the Clock Distribution of whole design, comprising: each physical division, and the clock zone scale between each physical division, distribution and data interaction situation;

Step 2, determines number and the range of adjustment of each physical division internal clocking regulator according to Clock Distribution;

Step 3, inserts clock controller at corresponding point;

Step 4, analyzes whole timing topology from top layer, obtains the actual time delay of each clock branch, and the regulated value of clock controller is set according to demand, thus the whole Clock Tree of balance.

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