CN103475801A - Signal clamping device - Google Patents

Abstract

The invention provides a signal clamping device, comprising: a coupling capacitor, one end of the coupling capacitor receives an input signal, and the other end of the coupling capacitor couples the input signal into a signal to be clamped; a signal reset module, a signal reset module and a coupling The other end of the capacitor is connected to reset the signal to be clamped to a low level under the control of the reset signal; the comparison module, the comparison module is connected to the other end of the coupling capacitor, and is used to reset the voltage of the signal to be clamped after reset The voltage of the reference signal is compared to generate a switch control signal; the switch module is respectively connected to the comparison module and the other end of the coupling capacitor, and is used to turn on or off under the control of the switch control signal to selectively use the comparison module The output voltage charges the coupling capacitor. The invention can reduce the circuit area, reduce the power consumption and the cost, have a simpler structure and be more conducive to chip integration.

Description

A signal clamping device

technical field

The invention relates to the technical field of electronic circuits, and particularly designs a signal clamping device.

Background technique

Many systems need to process video signals, such as television, video surveillance, video acquisition, video amplification, etc. When transmitting video signals, there may be a voltage difference between the ground potentials of different devices. In order to protect the interface circuit of the transmission equipment, the video signal is output or input in the way of AC coupling. After coupling, the DC component of the video signal will be lost, and a clamp circuit is usually required to recover the DC component of the coupled video signal.

Figure 1 shows a traditional clamping circuit. As shown in Figure 1, the clamping circuit includes a coupling capacitor C1, two current sources IDC1 and IDC2, an enhanced NMOS transistor MN1 and a comparator COMP. Initial reset: After power-on, RST will have a short high time before going low. When RST is high, MN1 is turned on, and at the same time the COMP output is reset by RST, the output is low, the current IDC1 is disconnected, and the current source IDC1 is disconnected, both IDC2 and MN1 are discharged, and VINC is reset to a low voltage flat. Then RST becomes low and starts the following working process. If MN1 is not added, the VINC node can be pulled to low level only through IDC2, but because IDC1 has a large current and the disconnection time is short, IDC2 current is very small and the capacitance is large, so VINC cannot be pulled down in a short time. discharge to low level. The coupled input video signal VINC is compared with the reference voltage VREF through the comparator. When VINC is less than VREF, the output of the comparator is high level, and the current source IDC1 is turned on to charge the capacitor C1, so that the DC level of VINC rises. When the lowest level of VINC is greater than VREF, the output of the comparator is low level, and the current source IDC1 is disconnected, so that the DC level of VINC is maintained, so that the lowest level of VINC is clamped at the set VREF value.

The traditional signal clamping circuit needs to use an additional first current source IDC1 to charge the coupling capacitor C1, and the area, power consumption and cost of the chip are relatively high.

Contents of the invention

The present invention aims at solving one of the above technical problems at least to a certain extent or at least providing a useful commercial choice. Therefore, the object of the present invention is to provide a signal clamping device with fast clamping speed.

To achieve the above object, an embodiment of the present invention provides a signal clamping device, including: a coupling capacitor, one end of the coupling capacitor receives an input signal, and the other end of the coupling capacitor couples the input signal to be clamping signal; signal reset module, the signal reset module is connected to the other end of the coupling capacitor, and is used to reset the signal to be clamped to a low level under the control of the reset signal; the comparison module, the comparison The module is connected to the other end of the coupling capacitor, and is used to compare the voltage of the signal to be clamped after reset with the voltage of the reference signal to generate a switch control signal; a switch module, the switch module is respectively compared with the The module is connected to the other end of the coupling capacitor, and is used to turn on or off under the control of the switch control signal to selectively use the output voltage of the comparison module to charge the coupling capacitor, wherein, when the When the DC level of the signal to be clamped outputted by the other end of the coupling capacitor is equal to or higher than the voltage of the reference signal, the switch module is turned off to keep the DC level of the signal to be clamped at the voltage of the reference signal voltage.

According to the signal clamping device of the embodiment of the present invention, the purpose of reducing the circuit area, power consumption and cost can be achieved without increasing the complexity of the circuit, and the structure is simpler, which is more conducive to chip integration. In addition, the signal reset module is used to initially reset the signal to be clamped, which improves the clamping speed.

Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and comprehensible from the description of the embodiments in conjunction with the following drawings, wherein:

Fig. 1 is the circuit diagram of traditional signal clamping device;

2 is a circuit diagram of a signal clamping device according to an embodiment of the present invention;

3 is a circuit diagram of a signal clamping device according to an embodiment of the present invention;

4 is a circuit diagram of a signal clamping device according to another embodiment of the present invention;

5 is a circuit diagram of a signal clamping device according to yet another embodiment of the present invention;

FIG. 6 is a circuit diagram of a signal clamping device according to yet another embodiment of the present invention.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

In the present invention, unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection" and "fixation" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection , or integrally connected; it may be mechanically connected or electrically connected; it may be directly connected or indirectly connected through an intermediary, and it may be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

In the present invention, unless otherwise clearly specified and limited, a first feature being "on" or "under" a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them. Moreover, "above", "above" and "above" the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature. "Below", "below" and "under" the first feature to the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is less horizontal than the second feature.

The following describes a signal clamping device according to an embodiment of the present invention with reference to FIGS. 2 to 6 .

As shown in FIG. 2 , the signal clamping device of the embodiment of the present invention includes: a coupling capacitor 100 , a signal reset module 200 , a comparison module 300 and a switch module 400 .

One end of the coupling capacitor 100 receives the input signal VIN, and couples the input signal VIN into a signal VINC to be clamped, and outputs the signal VINC to be clamped at the other end of the coupling capacitor 100 . Wherein, the input signal VIN may be an AC signal, such as a video signal. It can be understood that the signal clamping device provided by the embodiment of the present invention includes but is not limited to clamping video signals, and can also clamp other types of AC input signals, which will not be repeated here.

The signal reset module 200 is connected to the other end of the coupling capacitor 100 (the output end of VINC), and resets the signal VINC to be clamped to a low level under the control of the reset signal RST. For example, the signal VINC to be clamped is reset to zero potential.

In one embodiment of the present invention, the signal reset module 200 includes a current source and a switch unit. Wherein, one end of the current source is connected to the other end of the coupling capacitor 100, and the other end is grounded. The switch unit is connected in parallel with the current source, and is turned on under the control of the reset signal RST. Initially, RST is at a high level, and the switch unit is in a conduction state at this time, and the other end of the coupling capacitor 100 can be discharged, thereby realizing the pull-down of the level of the signal VINC to be clamped. As the current source and the switching unit gradually discharge another degree of the coupling capacitor 100 , the signal VINC to be clamped is reset to a low level. When the reset signal RST turns to low level, the switch unit is turned off.

In the example of the present invention, the switching unit can be an enhanced NMOS (N-Mental-Oxide-Semiconductor, N-type metal-oxide-semiconductor) tube, an enhanced PMOS (P-Mental-Oxide-Semiconductor, P-type metal- Oxide-semiconductor) tube or transmission gate (complementary MOS tube). It should be understood that the foregoing descriptions are for illustrative purposes only, rather than limiting the present invention. The switch unit can also adopt other analog devices with switch control function.

The reset signal RST can be provided by a reset signal generating device. Wherein, the reset signal may be at a high level for a short time and then change to a low level. That is, the initial level of the reset signal RST is a high level, and is reversed to a low level after a lapse of a predetermined time.

The comparison module 300 is connected to the other end of the coupling capacitor 100 (the VINC output end), and compares the DC level of the signal VINC to be clamped after being reset by the signal service reset module 200 with the voltage of the reference signal VREF to generate a switch control signal. It should be noted that the input signal VIC is an AC signal, and the signal VINC to be clamped after being coupled by the coupling capacitor 100 is also an AC signal, and the DC level of the AC signal is the lowest voltage of the AC signal. Therefore, clamping the DC level of the signal VINC to be clamped can also be understood as clamping the lowest voltage of the AC signal, that is, comparing the lowest voltage of the signal VINC to be clamped with the voltage of the reference signal VREF to generate a switch control signal. In an embodiment of the present invention, the comparison module 300 may be a comparator. Specifically, the positive input terminal of the comparator receives the reference signal VREF, the negative input terminal is connected to the other terminal of the coupling capacitor 100 to receive the signal to be clamped, and the reset terminal is connected to the reset signal generating device to receive the reset signal RST. By designing the gain and speed of the comparator to be higher, the clamping can be made more accurate.

It should be noted that the initial level of the reset signal is a high level, and the comparator is reset so that the output of the comparator is at a low level. During this period of time, the switch unit of the signal reset module 200 is turned on, so as to reset the signal VINC to be clamped to a low level. When the reset signal turns to low level, the switch unit is turned off, and the comparator starts to work normally.

The switch module 400 is respectively connected to the comparison module 300 and the other end of the coupling capacitor 100, and is turned on or off under the control of the switch control signal output by the comparison module 300, thereby selectively outputting the voltage output by the comparison module 300 to the coupling capacitor 100 to charge the coupling capacitor 100. Specifically, when the switch module 400 is turned on under the control of the switch control signal, the comparison module outputs a voltage to the coupling capacitor 100 to charge the coupling capacitor 100 . When the switch module 400 is turned off under the control of the switch signal, charging to the coupling capacitor 100 is stopped.

In an embodiment of the present invention, the switch control signal output by the comparison module 300 may be a turn-on signal or a turn-off signal. Wherein, the switch module 400 is in the on state under the control of the on signal; the switch module 400 is in the off state under the control of the off signal.

In an embodiment of the present invention, the switch module 400 may be a diode, an enhanced NMOS transistor or an enhanced PMOS transistor.

Specifically, the comparison module 300 is reset under the control of the reset signal RST, and outputs a cut-off signal, that is, a low-level signal when the reset signal is at a high level.

Furthermore, the comparing module 300 compares the DC level of the signal VINC to be clamped with the voltage of the reference signal VREF. When VINC is smaller than VREF, the output terminal of the comparison module 300 outputs a turn-on signal to control the switch module 400 to turn on, thereby charging the coupling capacitor 100 , and the voltage value of VINC is in a rising stage. When VINC is equal to or greater than VREF, the output terminal of the comparison module 300 outputs a cut-off signal to control the switch module 400 to cut off. It can be seen that when the DC level of VINC is equal to or greater than VREF, the switch module 400 is turned off to keep the DC level of the signal VINC to be clamped at the voltage of the reference signal VREF, that is, VINC=VREF, so as to realize the clamping of VINC.

In one embodiment of the present invention, the current source of the signal reset module 200 is a weak current source, which can slowly pull down the DC level of the VINC signal, so that when the DC level of VINC is higher than VREF and the switch module 400 is turned off again, Slowly discharge the other end of the coupling capacitor 100 to slowly pull down the DC level of the VINC signal, avoiding that the DC level of VINC cannot be set to VREF when the lowest level of VINC is always higher than VREF. It should be noted that during the charging process, when the DC level of VINC is higher than VREF, the DC level of the VINC signal needs to be pulled down. At this time, the switch module 400 should be in the cut-off state, and only the DC level of the VINC signal is controlled by the current source. Make a pull down. This is because the pull-down action of the switch module 400 on the DC level of the VINC signal is a strong pull-down, which will pull down the DC level of the VINC signal too much, so that the DC level of the VINC signal cannot be set at the VREF value.

If the VINC node is not reset at the beginning, if its initial potential is much higher than VREF, then it will take a long time to pull down the potential of VINC, that is, its DC level, to VREF due to the large coupling capacitor C1 and the weak current source IDC . Therefore, the signal reset module 200 of the embodiment of the present invention can improve the clamping speed of VINC.

It should be noted that the switch unit and the switch module 400 can use various types of devices, wherein, in the signal clamping device provided by the embodiment of the present invention, the switch unit and the switch module 400 can use any combination of device types.

Signal clamping devices in various combinations are described below with reference to FIGS. 3 to 6 .

(1) The switch unit is an enhanced NMOS transistor (MN1), and the switch module 400 is a diode

As shown in FIG. 3 , one end of the coupling capacitor C1 is connected to the video signal VIN, and the other end outputs the coupled signal VINC to be clamped. One end of the current source IDC is connected to the signal VINC to be clamped, and the other end is grounded. The gate of the enhanced NMOS transistor MN1 is connected to the reset signal RST, the drain is connected to VINC, and the source and the substrate are grounded. The anode of the diode D1 is connected to the output terminal of the comparator COMP, and the cathode is connected to the signal VINC to be clamped. The positive input terminal of the comparator COMP is connected to the reference signal VREF, the negative input terminal receives the clamping signal VINC, and the reset terminal is connected to RST.

At the beginning, the initial reset signal RST is at high level, and the reset signal resets the comparator COMP, so that the output of the comparator is at low level. At this time, the diode D1 is in a cut-off state. MN1 is turned on when the reset signal is at a high level, and discharges the VINC node of the current source IDC, thereby resetting the VINC node to zero level. Therefore, compared with the scheme of not resetting VINC, the time required for clamping can be greatly reduced. After the RST signal is reset, the NMOS tube MN1 is disconnected, and the comparator starts to work normally.

Comparator COMP compares signals VINC and VREF. When the DC level of VINC is lower than VREF, the output of the comparator COMP is at a high level, so that the diode D1 is turned on, thereby providing current to the coupling capacitor C1 to charge the coupling capacitor C1, so that the DC level of VINC increases. When the DC level of VINC is equal to or greater than VREF, the output of the comparator is low level, and the diode D1 is cut off, so that the DC level of VINC remains at VREF to achieve the purpose of clamping.

(2) The switch unit is an enhanced PMOS transistor (MP1), and the switch module 400 is a diode

As shown in Figure 4, when the switch unit is an enhanced PMOS transistor, the switch unit also includes an inverter INV. Wherein, one end of the inverter INV is connected to the reset signal output device to receive the reset signal RST, and the other end is connected to the reset signal RST. The gates of the enhanced PMOS transistor MP1 are connected, so that the reset level of the enhanced PMOS transistor MP1 and the NMOS transistor can be kept consistent. When RST is valid (high level), RST is low level after passing through the inverter, so that MP1 is turned on, and the VINC node is discharged and reset.

It can be seen from the above that by adding an inverter, it can be realized that whether the switch unit is a PMOS transistor or an NMOS transistor, VINC is reset when RST is at a high level.

The working principles of other devices are the same as above, and will not be repeated here.

(3) The switch unit is an enhanced NMOS transistor (MN1), and the switch module 400 is an NMOS transistor (MN2)

As shown in FIG. 5 , one end of the coupling capacitor C1 is connected to the video signal VIN, and the other end outputs the coupled signal VINC to be clamped. One end of the current source IDC is connected to the signal VINC to be clamped, and the other end is grounded. The gate of the enhanced NMOS transistor MN1 is connected to the reset signal RST, the drain is connected to VINC, and the source and the substrate are grounded. The drain and gate of the enhanced NMOS transistor MN2 are connected to the output terminal of the comparator COMP, the source is connected to VINC, and the substrate is grounded. The positive input terminal of the comparator COMP is connected to the reference signal VREF, the negative input terminal is connected to the clamping signal VINC, the reset terminal is connected to RST, and the output is connected to the drain and gate of the NMOS transistor MN2.

At the beginning, the initial reset signal RST is at high level, and the reset signal resets the comparator COMP, so that the output of the comparator is at low level. At this point, MN2 is in a cut-off state. MN1 is turned on when the reset signal is at a high level, and discharges the VINC node of the current source IDC, thereby resetting the VINC node to zero level. Therefore, compared with the scheme of not resetting VINC, the time required for clamping can be greatly reduced. After the RST signal is reset, the NMOS tube MN1 is disconnected, and the comparator starts to work normally.

Comparator COMP compares signals VINC and VREF. When VINC is smaller than VREF, the output of the comparator COMP is at a high level, which makes MN2 conduct, thereby providing current to the coupling capacitor C1 to charge the coupling capacitor C1, so that the DC level of VINC increases. When the DC level of VINC is equal to or greater than VREF, the output of the comparator is low level, and MN2 is cut off, so that the DC level of VINC remains at VREF to achieve the purpose of clamping.

(4) The switch unit is an enhanced NMOS transistor (MN1), and the switch module 400 is an enhanced PMOS transistor (MP1)

As shown in FIG. 6, the switch module 400 uses an enhanced PMOS transistor MP1, wherein the gate and substrate of the enhanced PMOS transistor MP1 are connected to the other end of the coupling capacitor (VINC output end), and the drain and source are connected to the comparator output terminal. The working principles of other devices are the same as above, and will not be repeated here.

According to the signal clamping device of the embodiment of the present invention, under the premise of not increasing the complexity of the circuit, the output of the comparator is used as both a control signal and a current source, thereby achieving the purpose of reducing the circuit area, reducing power consumption and cost, The structure is simpler and more conducive to chip integration. Moreover, the clamping speed is improved by using the MOS tube reset in the initial state.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be construed as limitations to the present invention. Variations, modifications, substitutions, and modifications to the above-described embodiments are possible within the scope of the present invention.

Claims (10)

1. A signal clamping device, characterized in that, comprising: A coupling capacitor, one end of the coupling capacitor receives an input signal, and the other end of the coupling capacitor couples the input signal into a signal to be clamped; A signal reset module, the signal reset module is connected to the other end of the coupling capacitor, and is used to reset the signal to be clamped to a low level under the control of a reset signal; A comparison module, the comparison module is connected to the other end of the coupling capacitor, and is used to compare the voltage of the signal to be clamped after reset with the voltage of the reference signal to generate a switch control signal; A switch module, the switch module is respectively connected to the comparison module and the other end of the coupling capacitor, and is used to turn on or off under the control of the switch control signal to selectively use the output voltage of the comparison module Charging the coupling capacitor, wherein when the DC level of the signal to be clamped outputted from the other end of the coupling capacitor is equal to or higher than the voltage of the reference signal, the switch module is turned off to switch the to-be-clamped The DC level of the clamp signal is maintained at the voltage of the reference signal. 2. The signal clamping device according to claim 1, wherein the signal reset module comprises: A current source, one end of the current source is connected to the other end of the coupling capacitor, and the other end of the current source is grounded; a switch unit, the switch unit is connected in parallel with the current source, and is used to conduct under the control of the reset signal, and discharge the other end of the coupling capacitor to reset the signal to be clamped to a low level , and the switching unit is turned off after the level of the reset signal is reversed. 3. The signal clamping device according to claim 1 or 2, characterized in that, the initial level of the reset signal is high level, and turns to low level after a predetermined time elapses. 4. The signal clamping device according to claim 2, wherein the switch unit is an enhanced NMOS transistor, an enhanced PMOS transistor or a transmission gate. 5. The signal clamping device according to claim 4, wherein when the switch unit is an enhanced PMOS transistor, the switch unit further comprises an inverter, wherein one end of the inverter is connected to The reset signal output device is connected to receive the reset signal, and the other end of the inverter is connected to the gate of the enhanced PMOS transistor. 6. The signal clamping device according to claim 1, wherein the comparison module is a comparator, wherein the positive input terminal of the comparator receives the reference signal, and the negative input terminal is connected to the coupling capacitance The other terminal is connected to receive the signal to be clamped, and the reset terminal is connected to the reset signal output device to receive the reset signal. 7. The signal clamping device according to claim 6, wherein the switch control signal is an on signal or an off signal. 8 . The signal clamping device according to claim 7 , wherein the comparison module is reset under the control of the reset signal, and outputs a cutoff signal when the reset signal is at a high level. 9. The signal clamping device according to claim 7, wherein when the DC level of the signal to be clamped is less than the voltage of the reference signal, the output terminal of the comparison module outputs a conduction signal to control The switch module is turned on, otherwise the output terminal of the comparison module outputs a cut-off signal to control the switch module to turn off. 10. The signal clamping device according to any one of claims 1-9, wherein the switch module is a diode, an enhanced NMOS transistor or an enhanced PMOS transistor.

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