CN103440010B - Active voltage limiting circuit - Google Patents

Abstract

The invention relates to the technical field of analog integrated circuit circuits. The invention discloses an active voltage limiting circuit aiming at the problem that the output voltage of the existing voltage limiting circuit is not stable enough and the accuracy is poor. The technical solution of the present invention is an active voltage limiting circuit, including four NMOS tubes: M1, M2, M14, M18, fourteen PMOS tubes: M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M15, M16, M17, two PNP type transistors: Q1, Q2, one NPN type transistor: Q3, an inverter and an alternative circuit. When the input voltage is within the set threshold voltage range, the output voltage changes with the input voltage, and the following accuracy is high. When the input voltage is outside the set threshold voltage range, the output voltage is the upper threshold voltage or the lower threshold voltage, and the output voltage has high stability.

Description

An Active Voltage Limiting Circuit

technical field

The invention relates to the technical field of analog integrated circuit circuits, in particular to an active voltage limiting circuit.

Background technique

As a design unit of some circuits, the voltage limit circuit is widely used in analog integrated circuits. Its core is that within the set voltage range, the output voltage can follow the input voltage change. Outside the set voltage range, the circuit output It can be fixed at a certain value and does not change with the input. Its accuracy and stability largely determine the performance of the voltage limiter circuit.

The disadvantage of the traditional voltage limit circuit is that within the set voltage range, the output voltage cannot follow the input voltage well, and an error occurs at the output end; or outside the set voltage range, the circuit output cannot be fixed at a certain value. a specific value. The output voltage of such a circuit is not stable enough, and the accuracy is poor, which will cause unstable factors in the subsequent use of the circuit, and cannot be used in some fields that require relatively stable and accurate.

Contents of the invention

The purpose of the present invention is to provide an active voltage limiting circuit in order to solve the problems of insufficient stability and poor accuracy of the output voltage of the existing voltage limiting circuit.

The technical solution adopted by the present invention is an active voltage limiting circuit, which is characterized in that it includes four NMOS tubes: M1, M2, M14, M18, and fourteen PMOS tubes: M3, M4 , M5, M6, M7, M8, M9, M10, M11, M12, M13, M15, M16, M17, two PNP transistors: Q1, Q2, one NPN transistor: Q3, inverter and one of two select circuit;

The specific connection relationship is as follows: NMOS transistors M1 and M2 form a current mirror, the sources of M1 and M2 are grounded, the current source IB is connected to the gate and drain of M1, the gate of M1 is connected to the gate of M18, and the gate of M2 is connected to the gate and drain of M1. The drain of M2 is connected to the drain and gate of M3, the gate of M3 is connected to the gate of PMOS transistors M4, M6, M7, M9, M11, and M15, and the source of M3, M4, M6, M7, M9, M11, and M15 is connected to a high level VDD, the drain of M4 is connected to the source of M5 and the base of Q1 tube, the drain of M5 is grounded, the gate of M5 is connected to the gate of M10 and connected to the input voltage V _IN , the drain of M6 is connected to the emitter of PNP transistor Q1, Q2 and NPN The base of transistor Q3, the collectors of Q1 and Q2 are grounded, the drain of M7 is connected to the base of Q2 and the source of M8, the drain of M8 is grounded, the gate of M8 is connected to the upper threshold voltage VTH+, and the drain of M9 is connected to the gate of M12 and the source of M10 , the drain of M10 is grounded, the drain of M11 is connected to the source of M12 and M13, the drain of M12 is grounded, the drain of M13 is connected to the drain and gate of M14 and the input terminal of the inverter, the source of M14 is grounded, and the drain of M15 is connected to the gate of M13 And the source of M16, the drain of M16 is grounded, the gate of M16 is connected to the lower threshold voltage VTH-, the collector of NPN transistor Q3 is connected to high level VDD, the emitter of Q3 is connected to the source of M17, the gate of M17 is connected to the drain and outputs voltage VA, the drain of M17 is connected to the drain of M18, the gate of M17 is connected to the B input terminal of the one-of-two selection circuit, the source of M18 is grounded, the A input terminal of the one-two selection circuit is connected to the lower threshold voltage VTH-, and the output terminal of the inverter Connect the enabling terminal EN of the one-two selection circuit, and the output terminal output voltage V _OUT of the one-two selection circuit;

When V _IN <VTH-, the enable terminal EN is high level, and the one-of-two selection circuit outputs VTH-; when VTH-<V _IN <VTH+, the output voltage VA changes with V _IN , and the enable terminal EN is low Level, select one of the two to select the circuit output VA; when V _IN >VTH+, the output voltage VA is fixed at VTH+, the enable terminal EN is low level, and the output voltage of the circuit to select one of the two is VTH+.

The beneficial effect of the present invention is that when the input voltage is within the set threshold voltage range, the output voltage follows the input voltage with high tracking accuracy; when the input voltage is outside the set threshold voltage range, the output voltage is the upper threshold voltage or the lower threshold voltage. threshold voltage, high output voltage stability.

Description of drawings:

Fig. 1 is the circuit schematic diagram of active voltage limiting circuit of the present invention;

Fig. 2 is a simulation schematic diagram of the active voltage limiting circuit of the present invention.

Among them: M1, M2, M14, M18 are NMOS tubes; M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M15, M16, M17 are PMOS tubes; Q1, Q2 are PNP type Transistor; Q3 is an NPN triode; INV is an inverter; MUX2 is a two-to-one selection circuit.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The specific circuit of the active voltage limiting circuit of the present invention is shown in FIG. 1 . Among them, VTH+ and VTH- are the set threshold voltages, VTH+ is the upper threshold voltage, VTH- is the lower threshold voltage, and V _IN is the input voltage.

When V _IN <VTH-, the enable terminal EN is at a high level, and the one-of-two selection circuit MUX2 selects the input voltage VTH- of the input terminal A as the output, that is, V _OUT =VTH-, which is the lowest value of the output voltage.

When VTH-<V _IN <VTH+, the enable terminal EN is at low level, and the one-of-two selection circuit MUX2 selects the input voltage VA of the input terminal B as the output, that is, V _OUT =VA. At this time, VA changes with V _IN , and V _OUT also changes with the input voltage V _IN .

When V _IN >VTH+, VA is fixed at VTH+, the enable terminal EN is at low level, and the two-choice selection circuit MUX2 selects the input voltage VA of the input terminal B as the output, that is, V _OUT = VTH+, which is the highest value of the output voltage .

The circuit of the present invention is shown in Figure 1, including four NMOS tubes: M1, M2, M14, M18, and fourteen PMOS tubes: M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13 , M15, M16, M17, two PNP-type transistors: Q1, Q2, one NPN-type transistor: Q3, an inverter INV and a choice circuit MUX2.

The specific connection relationship is as follows: NMOS transistors M1 and M2 form a current mirror, the sources of M1 and M2 are grounded, the current source IB is connected to the gate and drain of M1, the gate of M1 is connected to the gate of M18, and the gate of M2 is connected to the gate and drain of M1. The drain of M2 is connected to the drain and gate of M3, the gate of M3 is connected to the gate of PMOS transistors M4, M6, M7, M9, M11, and M15, and the source of M3, M4, M6, M7, M9, M11, and M15 is connected to a high level VDD, the drain of M4 is connected to the source of M5 and the base of Q1 tube, the drain of M5 is grounded, the gate of M5 is connected to the gate of M10 and connected to the input voltage V _IN , the drain of M6 is connected to the emitter of PNP transistor Q1, Q2 and NPN The base of transistor Q3, the collectors of Q1 and Q2 are grounded, the drain of M7 is connected to the base of Q2 and the source of M8, the drain of M8 is grounded, the gate of M8 is connected to the upper threshold voltage VTH+, and the drain of M9 is connected to the gate of M12 and the source of M10 , the drain of M10 is grounded, the drain of M11 is connected to the source of M12 and M13, the drain of M12 is grounded, the drain of M13 is connected to the drain and gate of M14 and the input terminal of the inverter, the source of M14 is grounded, and the drain of M15 is connected to the gate of M13 And the source of M16, the drain of M16 is grounded, the gate of M16 is connected to the lower threshold voltage VTH-, the collector of NPN transistor Q3 is connected to high level VDD, the emitter of Q3 is connected to the source of M17, the gate of M17 is connected to the drain and outputs voltage VA, the drain of M17 is connected to the drain of M18, the gate of M17 is connected to the B input terminal of the one-of-two selection circuit, the source of M18 is grounded, the A input terminal of the one-two selection circuit is connected to the lower threshold voltage VTH-, and the output terminal of the inverter The enabling terminal EN of the one-two selection circuit is connected, and the output terminal of the one-two selection circuit outputs a voltage V _OUT .

The working principle of the active voltage limiting circuit of the present invention is described below:

As shown in Figure 1, 1) When the input voltage V _IN is less than the lower threshold voltage VTH-, that is, the gate voltage of the PMOS transistor M16 is greater than the gate voltage of the M10, at this time the gate voltage of the PMOS transistor M13 is greater than the gate voltage of the PMOS transistor M12, and the M13 transistor is turned off , there is no current flowing through the NMOS tube M14, the input of the inverter INV is at low level, the enabling terminal EN of the two-selection circuit MUX2 is at a high level, and the input voltage VTH- of the input terminal A is selected as the output V _OUT , that is The output lower limit voltage of the circuit is VTH-;

2) When the input voltage is greater than the lower threshold voltage VTH-, that is, the gate voltage of the PMOS transistor M16 is greater than the gate voltage of the M10. The drain current of the tube M11 all flows through the NMOS tube M14, which increases the voltage of the input terminal of the inverter INV. The input of the phase device INV is at a high level, and the enabling terminal EN of the two-choice selection circuit MUX2 is at a low level, and the input voltage VA of the input terminal B is selected as the output V _OUT ;

2.1) When the input voltage is greater than the upper threshold voltage VTH+, it can be seen from 2) that the circuit selects VA as the output V _OUT . At this time, the gate voltage of the PMOS transistor M5 is greater than the gate voltage of M8, that is, the base voltage of the PNP transistor Q1 is greater than that of the PNP transistor. The base voltage of the transistor Q2, that is, the Q1 tube is cut off, the Q2 tube is turned on, and all the tail current flows through Q2. At this time, through reasonable design of the circuit parameters, VA=VTH+ is used as the output V _OUT , and the upper limit of the output of the circuit is VTH+ , that is:

VA=V _TH+ +|V _GSM8 |+|V _BEQ2 |-V _BEQ3 -|V _GSM17 | (1)

Among them, V _GSM8 is the gate-source voltage of PMOS transistor M8, V _GSM17 is the gate-source voltage of PMOS transistor M17, V _BEQ2 is the base-emitter voltage of PNP transistor Q2, and V _BEQ3 is the base-emitter voltage of NPN transistor Q3.

Adjust the circuit so that:

|V _GSM8 |＝|V _GSM17 | (2)

|V _BEQ2 |＝V _BEQ3 (3)

Then formula (1) can be simplified as:

VA=VTH ₊ (4)

2.2) When the input voltage is greater than the lower threshold voltage VTH- and less than the upper threshold voltage VTH+, it can be seen from 2) that the circuit selects VA as the output V _OUT . At this time, the gate voltage of the PMOS transistor M5 is lower than the gate voltage of M8, that is, the PNP transistor Q1 The base voltage of the PNP transistor Q2 is lower than the base voltage of the PNP transistor Q2, that is, the Q1 tube is turned on, the Q2 tube is turned off, and all the tail current flows through the Q1. At this time:

VA＝V _IN +|V _GSM8 |+|V _BEQ2 |-V _BEQ3 -|V _GSM17 | (5)

Similarly, by adjusting the circuit and simplifying formula (5), we can get:

VA=V _IN (6)

That is to say: 1) when V _IN <VTH-, the enabling terminal EN is at a high level, and the two-choice selection circuit MUX2 selects VTH-, V _OUT =VTH-, as the lowest value of the output voltage;

2) When V _IN >VTH-, the enable terminal EN is at low level, V _OUT follows VA output, V _OUT =VA.

2.1) When VTH-<V _IN <VTH+, the voltage VA changes with V _IN , that is, V _OUT changes with the input voltage V _IN ;

2.2) When V _IN >VTH+, the voltage VA is fixed at VTH+, that is, V _OUT outputs a fixed voltage VTH+ as the highest value of the output voltage.

In the active voltage limiting circuit of the present invention, the lower threshold VTH- is set to 0.5V, the upper threshold VTH+ is set to 2V, and when the input voltage V _IN ranges from 0 to 3V, the H-spice simulation results are shown in Figure 2 shown.

Those skilled in the art will appreciate that the embodiments described here are to help readers understand the principle of the present invention, and the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (1)

1. an active voltage limit circuit, it is characterized in that, comprise four NMOS tube: M1, M2, M14, M18,14 PMOS: M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M15, M16, M17, two PNP type triode: Q1, Q2, NPN type triode a: Q3, phase inverter and alternative selection circuit;

Concrete annexation is as follows: NMOS tube M1, M2 form current mirror, M1, M2 pipe source ground, current source IB is connected with M1 grid leak, M1 grid connects M18 grid, M2 grid connects M1 grid and drain electrode, M2 drain electrode connects M3 drain and gate, M3 grid connects PMOS M4, M6, M7, M9, M11, M15 grid, M3, M4, M6, M7, M9, M11, M15 source electrode meets high level VDD, M4 drain electrode connects M5 source electrode and Q1 pipe base stage, M5 grounded drain, M5 grid is connected with M10 grid and is connected input voltage V _iN, M6 drain electrode connects PNP type triode Q1, the base stage of Q2 emitter and NPN type triode Q3, Q1, Q2 grounded collector, M7 drain electrode connects Q2 base stage and M8 source electrode, M8 grounded drain, M8 grid connects upper threshold voltage VTH+, M9 drain electrode connects M12 grid and M10 source electrode, M10 grounded drain, M11 drain electrode connects M12 and M13 source electrode, M12 grounded drain, M13 drain electrode connects M14 drain and gate and inverter input, M14 source ground, M15 drain electrode connects M13 grid and M16 source electrode, M16 grounded drain, M16 grid connects threshold voltages VTH-, NPN type triode Q3 collector meets high level VDD, Q3 emitter connects M17 source electrode, M17 grid is connected and output voltage VA with drain electrode, M17 drain electrode connects M18 drain electrode, M17 grid connects the B input end of alternative selection circuit, M18 source ground, the A input end of alternative selection circuit connects threshold voltages VTH-, inverter output connects the Enable Pin EN of alternative selection circuit, the output terminal output voltage V of alternative selection circuit _oUT,

Work as V _iNduring <VTH-, Enable Pin EN is high level, and alternative selection circuit exports VTH-; Work as VTH-<V _iNduring <VTH+, output voltage VA follows V _iNchange, Enable Pin EN is low level, and alternative selection circuit exports VA; Work as V _iNduring >VTH+, output voltage VA is fixed as VTH+, and Enable Pin EN is low level, alternative selection circuit output voltage VTH+.