CN103426815B - Semiconductor reflow processing for component filling - Google Patents

Abstract

A method for at least partially filling a feature on a workpiece generally includes the steps of: obtaining a workpiece comprising the feature; depositing a first conformal conductive layer in the feature; and thermally treating the workpiece so that the first conformal conductive layer is in the feature reflux.

Description

Semiconductor Reflow Processing for Part Filling

technical field

The present disclosure relates to methods for electrochemically depositing conductive materials (such as metals, such as , copper (Cu), cobalt (Co), nickel (Ni), gold (Au), silver (Ag), manganese (Mn), tin (Sn), aluminum (Al) and alloys of the above) method.

Background technique

An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and a dielectric material covering the surface of the semiconductor material. Devices that may be formed within semiconductors include MOS transistors, bipolar transistors, diodes, and diffused resistors. Devices that can be formed within the dielectric include thin film resistors and capacitors. The devices are interconnected by conductor paths formed within the dielectric. Typically, two or more levels of conductor paths with successive levels separated by dielectric layers are used as interconnects. In current practice, copper oxide and silicon oxide are commonly used for conductors and dielectrics, respectively.

Deposits in copper interconnects typically include dielectric layers, barrier layers, seed layers, copper fill, and copper cap. Because copper readily diffuses into the dielectric material, the barrier layer is used to separate the copper deposits from the dielectric material. However, it should be understood that barrier layers may not be required for other metal interconnects other than copper. The barrier layer is usually composed of refractory metals or refractory compounds, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN) and the like. Other suitable barrier layer materials may include manganese (Mn) and manganese nitride (MnN). Barrier layers are typically formed using a deposition technique known as physical vapor deposition (PVD), but may also be formed by using other deposition techniques such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

A seed layer can be deposited on the barrier layer. However, it should also be understood that direct on barrier (DOB) deposition, such as on alloys or co-deposited ) barrier layers of metals and other barrier layers known and/or used by those skilled in the art on which interconnect metals can be deposited without A separate seed layer, the interconnect metal such as titanium ruthenium (TiRu), tantalum ruthenium (TaRu), tungsten ruthenium (WRu).

In one non-limiting example, the seed layer may be a copper seed layer. As another non-limiting example, the seed layer may be a copper alloy seed layer, eg, copper manganese, copper cobalt, or copper nickel. In the case of depositing copper in the component, there are several exemplary options for the seed layer. First, the seed layer may be a PVD copper seed layer. See, eg, Figure 3 for illustrating a process involving PVD copper seed deposition. The seed layer can also be formed using other deposition techniques such as CVD or ALD.

Second, the seed layer can be a stacked film, eg, a liner layer and a PVD seed layer. A liner layer is a material used between the barrier layer and the PVD seed to alleviate the discontinuous seed problem and improve PVD seed adhesion. The liners are usually noble metals such as ruthenium (Ru), platinum (Pt), palladium (Pd) and osmium (Os), but the family can also include cobalt (Co) and nickel (Ni). Currently, CVD Ru and CVD Co are common liners; however, liner layers can also be formed using other deposition techniques (eg, ALD or PVD).

Third, the seed layer may be a secondary seed layer. Secondary seeding layers are similar to liner layers in that secondary seeding layers are typically formed from noble metals such as Ru, Pt, Pd, and Os, but the family can also include Co and Ni and the most common CVD Ru and CVDCo . (Like the seed and liner layers, the secondary seed layer can also be formed using other deposition techniques such as ALD or PVD). The difference is that the secondary seed layer is used as the seed layer, while the liner layer is an intermediate layer between the barrier layer and the PVD seed. See, for example, Figures 5 and 6 for illustrations of a process involving secondary seed deposition followed by ECD seed deposition in Figure 5, as described below, and fast Flash deposition. ("Flash" deposition was mainly on the field and at the bottom of the part, with no significant deposition on the sidewall of the part).

After the seed layer has been deposited according to one of the above examples, the part may include a seed layer enhancement (SLE) layer which is a deposited metal (eg, copper with a thickness of about 2 nm). TLC. The SLE layer is also called an electrochemical deposition seed (or ECD seed). See, eg, FIG. 4 for illustrating a process including PVD seed deposition and ECD seed deposition. See, eg, FIG. 5 for illustrating a process including secondary seed deposition and ECD seed deposition. As seen in Figures 4 and 5, the ECD seed can be a conformally deposited layer.

ECD copper seeds are typically deposited using basic chemistry including a copper ethylenediamine (EDA) complex in very low concentrations. ECD copper seeds can also be deposited using other copper complexes (e.g., copper citrate, copper tartrate, copper urea, etc.), and can be in a pH range of about 2 to about 11, about 3 to about 10, or at ECD copper seeds were deposited in a pH range to about 10.

After a seed layer (which may also include optional ECD seeds) has been deposited according to one of the above examples, conventional ECD fill and capping may be performed in the part, for example using acidic deposition chemistries. Traditional ECD copper acid chemicals may include, for example, copper sulfate, sulfuric acid, methanesulfonic acid, hydrochloric acid, and organic additives (eg, accelerators, suppressors, and levelers). Electrochemical deposition of copper has been found to be the most economical way of depositing copper metallization layers. In addition to being economically viable, ECD deposition techniques provide a substantially bottom-up (eg, non-conformal) metal fill that is mechanically and electrically suitable for interconnect structures.

Traditional ECD filling, especially in small parts, can result in lower quality interconnects. For example, traditional ECD copper filling can create voids, especially in features with dimensions smaller than 30nm. As an example of the type of void formed using conventional ECD deposition, the opening of the feature can be pinch off. Other types of voids can also result from the use of traditional ECD copper fill processes in small components. The voids and other inherent properties of deposits formed using conventional ECD copper fills can increase the resistance of the interconnect, thereby degrading the electrical performance of the device and degrading the reliability of the copper interconnect.

Accordingly, there is a need for an improved, substantially void-free metal filling process for components. The substantially void-free metal fill can be used in small components, eg, components with opening sizes of less than 30 nm.

Contents of the invention

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

According to one embodiment of the present disclosure, a method for at least partially filling a feature on a workpiece is provided. The method generally includes the steps of: obtaining a workpiece comprising a component; depositing a first conformal conductive layer in the component; and heat treating the workpiece to reflow the first conformal conductive layer in the component.

According to another embodiment of the present disclosure, a method for at least partially filling a feature on a workpiece is provided. The method generally includes the steps of: obtaining a workpiece comprising a part; depositing a barrier layer in the part; and depositing a first conductive layer in the part after the barrier layer, wherein the first conductive layer is a seed layer. The method further includes the steps of: depositing a second conductive layer in the component after the first conductive layer, wherein the second conductive layer is a conformal conductive layer; and annealing the workpiece to reflow the second conductive layer in the component.

According to another embodiment of the present disclosure, a workpiece is provided. The workpiece typically includes at least one feature having a dimension of less than 30 nm and a substantially void-free conductive layer in the feature.

Description of drawings

The foregoing aspects of the present disclosure, and many of the attendant advantages, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

Figure 1 is a schematic flowchart depicting the processing steps and exemplary feature development process of an exemplary embodiment of the present disclosure;

FIG. 2 is a comparison diagram of exemplary processing steps that may be used in conjunction with a prior art process and a process according to an embodiment of the present disclosure;

3 is a schematic flow diagram depicting the processing steps and exemplary feature development process using the main prior art damascene processes, including barrier layer deposition, seed crystal deposition, and conventional ECD fill and blanket deposition;

4 is a schematic flow diagram depicting the processing steps and exemplary feature development process using a prior art SLE (also known as ECD seeding) process, including barrier layer deposition, seeding deposition, ECD seeding deposition, and conventional ECD Fill and cover deposition;

5 is a schematic flow diagram depicting processing steps and an exemplary feature development process using a prior art ECD seeding process, including barrier layer deposition, secondary seeding deposition, ECD seeding deposition, and conventional ECD fill and blanket deposition;

6 is a schematic flow diagram depicting process steps and an exemplary feature development process for prior art deposition in a secondary seeding process with a flash layer, including barrier layer deposition, secondary seeding deposition, flash deposition and conventional ECD fill and blanket deposition;

7 is a schematic flow diagram depicting processing steps and an exemplary feature development process of several exemplary embodiments of the present disclosure;

8 is a graphical depiction of exemplary process steps for deposition of various exemplary wafers in a mosaic part having a part diameter of about 30 nm, according to an embodiment of the disclosure;

Figure 9 is a graphical depiction of 120 micron long line resistor resistance results obtained from the exemplary wafer depicted in Figure 8;

Figure 10 is a graphical depiction of 1 meter long wire resistor resistance results obtained from the exemplary wafer depicted in Figure 8;

FIG. 11 is a graphical depiction of RC delay results for 1 meter long resistors obtained from the exemplary wafer depicted in FIG. 8; and

12 includes a transmission electron microscope (TEM) image of a substantially void-free gap-fill for a mosaic feature having a feature diameter of about 30 nm in accordance with an embodiment of the disclosure.

Detailed ways

Embodiments of the present disclosure relate to workpieces, such as semiconductor wafers, devices or processing components for processing the workpieces, and methods of processing the workpieces. The term workpiece, wafer or semiconductor wafer means any flat medium or object, including semiconductor wafers and other substrates or wafers, glass, masks and optical or storage media, MEMS substrates or any other microelectronic, micromechanical or microelectromechanical device artifacts.

The processes described herein will be used for metal deposition or metal alloy deposition in workpiece components, including trenches and vias. In one embodiment of the present disclosure, the process can be used in small features, such as features with feature diameters of less than 30 nm. However, it should be understood that the processes described herein are applicable to any part size. The dimensions discussed in this application are the post-etch feature dimensions at the top opening of the part. The processes described herein can be applied to deposition of copper, cobalt, nickel, gold, silver, manganese, tin, aluminum and alloys of various morphologies in damascene applications, for example. In embodiments of the present disclosure, the damascene feature may be selected from the group consisting of features having the following sizes: less than 30 nm, about 5 nm to less than 30 nm, about 10 nm to less than 30 nm, about 15 nm to about 20 nm, about 20 nm to less than 30 nm , less than 20 nm, less than 10 nm, and about 5 nm to about 10 nm.

It should be understood that the descriptive terms "microfeatured workpiece" and "workpiece" as used herein include all structures and layers that have been previously deposited and formed at a given point during processing, and are not limited to those depicted in FIG. structure and layers.

It should be understood that the processes described herein may also be modified for metal or metal alloy deposition in high aspect ratio features such as vias in through-silicon via (TSV) features.

Although generally described in this application as metal deposition, it should be understood that the term "metal" also contemplates metal alloys. The metals and metal alloys can be used to form a seed layer or to fully or partially fill a part. Exemplary copper alloys may include, but are not limited to, copper manganese and copper aluminum. As a non-limiting example, the alloy composition ratio may range from about 0.5% to about 6% of the secondary alloy metal compared to the primary alloy metal (eg, Cu, Co, Ni, Ag, Au, etc.).

As noted above, conventional fabrication of metal interconnects may include appropriate deposition of barrier layers on the dielectric material to prevent metal from diffusing into the dielectric material. Suitable barrier layers may include, for example, Ta, Ti, TiN, TaN, Mn or MnN. Suitable barrier layer deposition methods may include PVD, ALD, and CVD; however, PVD is the most common process used for barrier layer deposition. Barrier layers are typically used to separate copper or copper alloys from dielectric materials; however, it should be understood that in the case of other metal interconnects, diffusion may not be an issue and barrier layers may not be required.

The barrier layer deposition may be followed by optional seed layer deposition. In the case of depositing metal in a part, there are several options for the seed layer. As noted above, the seed layer may be (1) a seed layer (as a non-limiting example, a PVD copper seed layer). The seed layer can be a metal layer such as copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, ruthenium, and alloys of the above. The seed layer can also be (2) a stacked film of a liner layer and a seed layer (as a non-limiting example, a CVD Ru liner layer and a PVD copper seed layer), or (3) a secondary seed layer (as A non-limiting example, is a CVD or ALD Ru secondary seed layer). However, it should be understood that this disclosure also contemplates other methods of depositing the exemplary seed layer.

As discussed above, the liner layer is a material used between the barrier layer and the seed layer to alleviate the discontinuous seed problem and improve the adhesion of the seed layer. The liners are usually noble metals such as Ru, Pt, Pd and Os, but the series can also include Co and Ni. Currently, CVD Ru and CVD Co are common liners; however, liner layers can also be formed using other deposition techniques (eg, PVD or ALD). For inlay applications, the thickness of the backing layer can vary from approx. arrive In the range.

Also as discussed above, secondary seeding layers are similar to liner layers in that secondary seeding layers are typically formed from noble metals such as Ru, Pt, Pd, and Os, but the series can also include Co and Ni and most Common CVD Ru and CVD Co. The difference is that the secondary seed layer is used as the seed layer, while the liner layer is an intermediate layer between the barrier layer and the seed layer. The secondary seed layer can also be formed using other deposition techniques such as PVD or ALD.

Can be in forming gas environment (forming gas) (for example, 3%-5% hydrogen in nitrogen or 3%-5% hydrogen in helium) at between about 100 ℃ to about 500 ℃ The liner or secondary seed deposit is heat treated or annealed at a temperature to remove any surface oxide, densify the secondary seed layer or liner layer, and improve the surface properties of the deposit. Liners or secondary seed deposits can be additionally passivated by immersion in gaseous nitrogen ( _N2 gas) or other passivating environment to prevent surface oxidation. Passivation of liners or secondary seeds is described in US Patent No. 8,357,599 issued January 22, 2013.

Non-limiting examples of deposited seed layers (e.g., PVD copper seeds, PVD copper seeds including CVD Ru liners or CVD Ru secondary seeds, or another deposited metal or metal alloy, layer combination, or deposition technique After a non-limiting example of ), the component may include a conformal metal layer after the seed layer. However, it should also be understood that the conformal metal layer may be deposited directly on the barrier layer, ie without a seed layer.

In one embodiment of the present disclosure, the conformal layer is deposited using an ECD seeding process, which can then be modified using a process known as ECD seeding "add-on" deposition (or ECD seeding "add-on") that includes a heat treatment step. The conformal layer. In other embodiments of the present disclosure, a conformal layer can be deposited using CVD, ALD, or other deposition techniques, and then the conformal layer can be subjected to a heat treatment step. According to an embodiment of the present disclosure, the conformal layer is "flowable" or capable of moving when subjected to heat treatment or annealing.

In this embodiment, ECD seed "add-on" generally refers to ECD metal seed deposition plus a heat treatment step (eg, annealing step). In one embodiment of the present disclosure, the heat treatment step may result in reflow of some or all of the seed deposition. The increase in temperature in the ECD seed layer facilitates the mobility of atoms in the layer and enhances the ability of the atoms to fill the structure.

ECD seeded "add-on" deposition is similar to ECD seeded deposition (using alkaline chemicals) compared to conventional ECD metal filling (using acidic chemicals), but with the addition of a heat treatment step. Furthermore, instead of just depositing a seed layer, an ECD seed "add-on" can be performed to partially fill or completely fill the part. Substantially void-free filling of small features can be achieved by an ECD seeded "add-on" process, as described in more detail below (see image of substantially void-free filling in small features in Figure 12).

The chemicals used in the ECD chamber for "add-on" deposition of ECD seed crystals may include basic chemicals, for example, Cu(ethylenediamine) at a pH in the range of about 8 to about 11, at In one embodiment of the present disclosure the pH is from about 8 to about 10, and in one embodiment of the present disclosure the pH is about 9.3. However, it should be understood that acidic chemistries using appropriate organic additives can also be used to achieve conformal ECD seed deposition.

Following ECD seed deposition, the workpiece may then be subjected to a spin, rinse and dry (SRD) process or other cleaning process. The ECD seed is then heated at a temperature warm enough to reflow the seed, but not so hot that the workpiece or components on the workpiece are damaged or degraded. For example, the temperature may range from about 100°C to about 500°C for seed reflux in the part. Suitable heat treatment temperatures or annealing temperatures are in the range of about 100°C to about 500°C, and temperatures capable of maintaining the sustained temperature in the range of about 200°C to about 400°C and at least about 250°C to about 350°C can be used. range of equipment to achieve the appropriate heat treatment temperature or annealing temperature.

The heat treatment process or the annealing process may be performed using a forming gas or an inert gas, pure hydrogen gas, or a reducing gas such as ammonia (NH ₃ ). During reflow, the deposit shape changes so that metal deposits can pool at the bottom of the part, as shown in FIG. 7 . In addition to reflow during the heat treatment process, metal deposits can produce larger grains and lower sheet resistivity. Inert gases can be used to cool heated workpieces.

After the ECD seed "add-on" deposition and heat treatment processes have been completed to partially or fully fill the part, traditional acidic chemistries can be used to complete the deposition process for gap fill and blanket deposition. The acidic chemical metal deposition step is often used to fill large structures and to maintain the proper film thickness required for subsequent polishing steps because the acidic chemical metal deposition step is usually a faster process than the ECD seeding process, saving time and Reduce processing costs.

As seen in Figures 1 and 7, the ECD seed deposition and reflow steps may be repeated to ensure complete filling of the part with the ECD seed. As such, the processes described herein may include one or more cycles of ECD seed deposition, cleaning (eg, SDR), and thermal treatment.

Referring to FIG. 1 , a reflow process 100 and exemplary components resulting from the reflow process are depicted. The workpiece 112 may in an exemplary embodiment be a dielectric material on a crystalline silicon workpiece containing at least one feature 122 . In exemplary step 102 , feature 122 is lined with barrier layer 114 and seed layer 115 . In exemplary step 104 , feature 122 of workpiece 112 has received a layer of ECD seed material 116 on seed layer 115 . In an exemplary annealing step 106, the workpiece is annealed at an appropriate temperature to induce an exemplary reflow step 108 to facilitate partial or complete filling. During the annealing step, ECD seed material 116 flows into part 122 to form filler 118 while minimizing adverse effects of workpiece 112 or parts included in workpiece 112 . In an exemplary embodiment, the ECD seed deposition step 104 , the annealing step 106 , and the reflow step 108 may be repeated to obtain the desired characteristics of the fill 118 . The number of times the steps are repeated may depend on the structure. Once the filler 118 has reached the desired dimensions, the exemplary capping step 110 may be used to complete the process of depositing additional material 120 over the part in preparation for additional workpiece 112 processing.

Referring now to FIG. 2 , an example process flow is provided in which embodiments of the present disclosure may be used in conjunction with and incorporated into other workpiece surface deposition processes. A previously developed process will be described first. First, the TSV process includes the deposition of barrier layers, seed layers, and conventional ECD fill. Second, the ECD seeding (also known as SLE) process includes the deposition of the barrier layer, seed layer, ECD seed layer, and conventional ECD fill. Third, the ECD seeding with liner (SLE) process includes the deposition of barrier layers, liner layers, seed layers, ECD seed layers, and conventional ECD fill. Fourth, the ECD Seeding with Secondary Seeding (SLE) process includes the deposition of a barrier layer, a secondary seeding layer, an ECD seeding layer, and a conventional ECD fill. Fifth, the ECD seeding (SLE) process with secondary seeding and flash includes the deposition of barrier layers, secondary seeding layers, flash layers, ECD seeding layers, and conventional ECD fill. Sixth, the ECD seeding (DOB) process includes the deposition of barrier layers, ECD seeding layers, and conventional ECD fill. The ECD seeded (DOB) process is a DOB process because there is no secondary seed, liner or seed layer deposited; instead, the ECD seed layer is deposited directly on the platable barrier layer.

Still referring to FIG. 2 , a process according to an embodiment of the present disclosure will now be described. Seventh, the ECD Seed Over (DOB) process includes the deposition of barrier layers, ECD seed "over" deposits, and conventional ECD fill and/or capping. As with the sixth example above, the ECD Seed On (DOB) process is also a DOB process because no secondary seed, liner or seed layer is deposited; instead, the ECD seed layer is deposited directly on the electroplatable barrier layer. Eighth, the ECD seeding add-on process includes the deposition of barrier layers, secondary seeding layers, ECD seeding "add-on" deposits, and conventional ECD fill and/or capping. Ninth, the ECD seed add-on process without ECD includes the deposition of a barrier layer, a secondary seed layer, and an ECD seed "add-on" deposit. Tenth, the ECD seed add-on process without secondary seeding includes the deposition of barrier layers, seed layers, ECD seed "add-on" deposits, and conventional ECD fill and/or cover. Eleventh, the ECD seed add-on process with liner and seed includes the deposition of barrier layers, precipitation layers, seed layers, ECD seed "add-on" deposits, and conventional ECD fill and/or cover.

Referring to FIG. 7 , another exemplary process according to an embodiment of the disclosure is provided. In the first step, the workpiece with the barrier layer and the secondary seeding layer is heat treated or annealed prior to the ECD seeding step to remove any surface oxide, densify the deposit and improve the surface properties of the deposit. The seed layer shown in FIG. 7 is a secondary seed layer, but it should be understood that the secondary seed layer may also be a seed layer or a stacked film of a liner layer and a seed layer. Suitable heat treatment or annealing conditions may include possibly in forming gas or pure hydrogen at a temperature between about 200°C to about 400°C for about one (1) minute to about ten (10) minutes. As noted above, the workpiece may alternatively be heat treated in an inert gas such as _N2 , argon (Ar), or helium (He). Reducing gases such as ammonia (NH ₃ ) may also be used.

In a second step, the workpiece is transferred to a deposition chamber for conformal deposition of the ECD seed layer. The thickness of the deposited film varies according to the desired properties and feature sizes of the metal deposit.

In the third step, the workpiece is cleaned by rotating, rinsing the workpiece with deionized (DI) water, and drying (SRD) the workpiece.

In a fourth step, the workpiece is heat treated or annealed at a temperature in the range of 200°C to 400°C to reflow the metal into the component.

In a fifth step, the workpiece may undergo sequential reprocessing of steps 2, 3 and 4 until the desired fill profile of the part on the workpiece is obtained.

In the sixth step, the workpiece is subjected to conventional ECD acid chemical deposition to achieve the desired thickness. The workpiece is then prepared for subsequent processing, which may include additional heat treatment, chemical mechanical polishing, and other processes.

Alternative embodiments of the process may include variations of the steps already described herein, and the steps, combinations and permutations may otherwise be incorporated as additional steps below. It is contemplated in the present disclosure that there may be, for example, about 4 to about 10, about 3 to about 10, or about 2 to about 11 Perform conformal "seed" deposition in alkaline or acidic solutions in the pH range. Reflowing can be performed using multiple deposition steps, cleaning (eg SRD) steps and heat treatment or annealing steps, or can be performed in a single step followed by heat treatment or annealing at appropriate temperatures.

ECD seed "add-on" deposition is important for small part development because the heat treatment step or annealing step and reflow step provide substantially void-free seed deposition. As described in more detail below, void formation in components increases electrical resistance (reducing the electrical performance of the device) and degrades the reliability of the interconnect.

Additional advantages are realized by using the processes described herein. In this regard, individual tools (eg, manufactured by Applied Materials, Inc. Electrochemical deposition, cleaning (e.g. SRD) and thermal treatment or annealing tools) can be used for ECD seed deposition steps (or multiple ECD seed deposition steps when repeated), cleaning steps (or multiple cleaning steps when repeated) , a heat treatment step (or multiple heat treatment steps when repeated) and for the final ECD step. Furthermore, the results show substantially void-free gapfill of small components using the processes described herein, resulting in lower resistance and resistance-capacitance (RC) delay values. Furthermore, the processes described herein provide the ability to fill small features on the order of approximately less than about 30 nm, whereas filling may not be achievable using conventional processes. It is also advantageous to deposit "add-on" ECD seeds in features larger than 30nm.

As described above, one or more layers of ECD seeds may be applied and then exposed to elevated temperatures to fill deeper features or high aspect ratio features. Referring to Figure 8, two exemplary ECD seeding additional processes (including annealing steps) are provided (wafer 4 and wafer 5), and two conventional ECD seeding processes for deposition in damascene features with feature diameters of approximately 30 nm (no annealing step) compared to [Wafer 1 and Wafer 7]. Referring to Figures 9 to 11, the results show that incremental deposition of ECD seeds in damascene parts results in resistance and resistance-capacitance (RC) Retardation values decrease where some or all of the deposition steps are followed by an annealing step.

All of Wafer 1, Wafer 4, Wafer 5, and Wafer 7 included the following initial processing conditions: Deposition ALDTaN barrier layer, followed by deposition of A seed layer of Ru (secondary seeding) was CVD, and then the workpiece was subjected to annealing at 300° C. and nitrogen passivation for 10 minutes.

Wafers 1 and 7 were then electroplated by a single step of ECD copper seeding at 2.1 amp-min and 0.5 amp-min, respectively, and then filled and covered using a conventional acidic ECD copper deposition process. The resulting workpiece yielded a thick ECD copper seed (wafer 1) and a thin ECD copper seed (wafer 7).

Wafer 4 and Wafer 5 were subjected to ECD seed "addition" conditions. Wafer 4 included three ECD copper seeding steps, each at 0.7 amp-min, with each of the first two steps followed by a 300°C anneal and no anneal after the third step, followed by conventional An acidic ECD copper deposition process completes the fill and cap. A microscopic image associated with a wafer 4 having a feature size close to 30 nm is provided in FIG. 12 . Although there is no anneal after the third step, it is understood that a final anneal step is also within the scope of this disclosure.

Wafer 5 included four ECD copper seeding steps, each at 0.5 amp-min, with each of the first three steps followed by a 300°C anneal and no anneal after the fourth step, followed by conventional An acidic ECD copper deposition process completes the fill and cap. Like wafer 4, it is understood that a final anneal step is also within the scope of this disclosure.

Referring now to FIGS. 9 through 11 , comparative resistance and RC delay data for Die 1 , Die 4 , Die 5 , and Die 7 are provided. As can be seen in Figures 9 through 11, the workpieces (wafer 4 and wafer 5) formed "additionally" using ECD seeds according to the methods described herein are compared to the workpieces (wafer 1 and wafer 7) formed using previously developed techniques. ) with significantly reduced resistive and resistive/capacitive (RC) delays.

Referring to FIGS. 9 and 10 , workpieces formed in accordance with embodiments of the present disclosure achieve a reduction in electrical resistance in the range of 0 to about 40% compared to workpieces formed using ECD seeding but without an ECD seeding plus annealing cycle. , greater than 0 to about 30%, greater than 0 to about 20%, about 10% to about 20%, and about 10% to about 15%.

Referring to FIG. 11 , workpieces formed in accordance with embodiments of the present disclosure achieved reduced RC retardation values compared to workpieces formed using ECD seeds but without the additional annealing cycle of the ECD seeds. Lower RC delay can result in less or no damage to the low-K intermetal dielectric in the component.

While illustrative embodiments have been illustrated and described, it will be understood that various changes may be made therein without departing from the spirit and scope of the disclosure.

Claims (19)

1. a kind of method at least partly filling the component on workpiece the described method comprises the following steps：

(a) acquisition includes the workpiece of component；

(b) under pH in the range of 8 to 11, the first conformal electrically conductive layers are electrochemically-deposited in using at least one copper complex In the component, at least one copper complex is selected from and is made of cupri ethylene diamine, copper citrate, cupric tartrate and urea copper Group；With

(c) workpiece is heat-treated so that first conformal electrically conductive layers reflux in the component.

2. according to the method described in claim 1, the step of being wherein heat-treated the workpiece reduces the sky in the component filling Gap.

3. according to the method described in claim 1, the method further includes following steps：It conformal is led depositing described first Before electric layer, by barrier deposition in the component.

4. according to the method described in claim 1, the method further includes following steps：It conformal is led depositing described first Before electric layer, current conducting seed crystal layer is deposited in the component.

5. according to the method described in claim 4, the metal for being wherein used for described kind of crystal layer is selected from the group being made of following object Group：Copper, cobalt, nickel, gold, silver, manganese, tin, aluminium, ruthenium and more than each object alloy.

6. according to the method described in claim 1, the metal for being wherein used for first conformal electrically conductive layers is selected from by following object The group of composition：The alloy of copper, cobalt, nickel, gold, silver, manganese, tin, aluminium and above each object.

7. according to the method described in claim 1, wherein heavy come electrochemistry by chemical vapor deposition or by atomic layer deposition Product first conformal electrically conductive layers.

8. according to the method described in claim 1, the method further includes following steps：In first conformal electrically conductive layers The second conformal electrically conductive layers are deposited later, and are heat-treated the workpiece so that the second conformal electrically conductive layers reflux.

9. according to the method described in claim 8, the method further includes following steps：In second conformal electrically conductive layers Third conformal electrically conductive layers are deposited later, and are heat-treated the workpiece so that the third conformal electrically conductive layers reflux.

10. according to the method described in claim 4, wherein described kind of crystal layer is selected from the group being made of following object：Kind crystalline substance, two Secondary kind of crystalline substance and the brilliant stacked film with liner of kind.

11. according to the method described in claim 1, the first conformal electrically conductive layers of wherein institute's reflux are partially or fully filled The component.

12. according to the method described in claim 1, the method further includes following steps：By cap layer deposition it is anti- On first conformal electrically conductive layers of stream.

13. according to the method for claim 12, wherein depositing the coating in acidic chemical.

14. according to the method described in claim 1, wherein heat treatment temperature is in the range of 100 DEG C to 500 DEG C.

15. according to the method described in claim 1, wherein component diameter is less than 30nm.

16. according to the method described in claim 1, wherein with not over the workpiece phase that is formed the step of being heat-treated the workpiece Than there is the workpiece by the heat treatment resistance value being more than in the range of 0 to 40% to reduce.

17. according to the method described in claim 3, wherein described first conformal electrically conductive layers are deposited directly on the barrier layer.

18. a kind of method at least partly filling the component on workpiece the described method comprises the following steps：

(a) acquisition includes the workpiece of component；

(b) by barrier deposition in the component；

(c) the first conductive layer is electrochemically-deposited in the component after the barrier layer, wherein first conductive layer For kind of a crystal layer；

(d) after first conductive layer, under pH in the range of 8 to 11, using at least one copper complex by second Conductive layer is electrochemically-deposited in the component, and at least one copper complex is selected from by cupri ethylene diamine, copper citrate, winestone The group of sour copper and urea copper composition, wherein second conductive layer is conformal electrically conductive layers；With

(e) make the workpiece annealing so that second conductive layer reflux in the component.

19. a kind of microelectronic workpiece, the microelectronic workpiece include：

(a) at least one component, at least one component have the size less than 30nm；With

(b) the void-free conductive layer of essence, the void-free conductive layer of essence is arranged in the component, wherein the essence Void-free conductive layer is formed as follows：Under pH in the range of 8 to 11, using at least one copper complex by One conformal electrically conductive layers are electrochemically-deposited in the component, and at least one copper complex is selected from by cupri ethylene diamine, citric acid The group of copper, cupric tartrate and urea copper composition；With so that the workpiece is annealed so that first conformal electrically conductive layers are in the portion Reflux in part.