CN103425460A - Writing back and discarding method of low-power-consumption register file - Google Patents

Abstract

The invention belongs to the technical field of microprocessors, and in particular relates to a write-back and discarding method of a register file with low power consumption. The present invention is based on the existing microprocessor, and its steps include: for the microprocessor, expand the original MIPS instruction set, add 3 "life length" in the instruction with redundant bits to represent the current register The variable will be used by several subsequent instructions; add "life length" adjustment logic at the execution level, memory access level, and alignment level. If the current register variable is used by subsequent instructions, its "life length" will be reduced by 1. Once found The "life length" of the current register variable is 0, it is discarded by selector-register based masking logic. The static estimation algorithm for the life length of the instruction register is implemented by software tools. Compared with the existing architecture, the present invention can effectively discover register variables that can be discarded without increasing hardware overhead, thereby reducing the power consumption and power consumption density of the register file.

Description

A low-power register file write-back and discard method

technical field

The invention belongs to the technical field of microprocessors, and in particular relates to a write-back and discarding method of a register file with low power consumption.

Background technique

The register file is the first-level storage unit in the processor and the core component of a modern microprocessor. Because the access to the register file is characterized by high speed and high frequency, the power consumption and power consumption density of the register file are quite large. , so that it has become the main component of energy consumption and power consumption hotspot of the microprocessor. High energy consumption poses a challenge to microprocessors, especially those in the embedded application field, and power consumption hotspots will lead to a decrease in circuit stability and life. Therefore, research on reducing the power consumption of the register file has very important practical significance.

Figure 1 shows a traditional 6-stage pipeline microprocessor structure diagram. Including fetching instruction level, decoding level, executing level, accessing memory level, aligning level and writing back level.

In the traditional microprocessor architecture, there is no special circuit to control the write-back of the register file, and useless write-back operations may occur during the actual instruction execution process, but these operations will not be shielded in the traditional microprocessor architecture , resulting in unnecessary energy consumption. To address this shortcoming, it is necessary to control the write-back of the register file. Once a useless write-back operation is found, the corresponding write-back operation is discarded, thereby reducing the access power consumption of the register file.

Contents of the invention

The purpose of the present invention is to provide a register file write-back discarding method capable of reducing access power consumption.

The present invention judges whether the current destination register needs to be written back (if If it is 0, the write-back is abandoned), thereby reducing the useless write-back power consumption of the register file, and also reducing the power consumption density of the register file, and improving the stability and life of the circuit.

The register file write-back discarding method that can reduce the access power consumption provided by the present invention is based on the MIPS microprocessor of the existing basic pipeline structure, and the existing microprocessor includes an instruction fetching stage, a decoding stage, an execution level, memory access level, alignment level, and write-back level (see Figure 1); the specific steps are:

(1) For the microprocessor, expand the original MIPS instruction set, and add 3 bits of "life length" to the instructions with redundant bits to indicate that the current register variable will be used by several subsequent instructions;

In the present invention, the life length of register X is defined as follows: when register X is at E (execution level), M (memory access level), A (alignment level) level, if register X has 1, 2 or 3 feedback Subsequent instructions within the range need to use register X, and the life length of register X is correspondingly designated as 1, 2 or 3; if register X has subsequent instructions beyond the feedback range that need to use register X, the life length of register X is defined as 4. The feedback range is defined as: when an instruction Y at the decoding level (D level) uses register X, and the instruction Z that generates register X is at E, M, or A level, it is said that the Y instruction generates the register in the Z instruction Within the feedback range of X, for example, in Figure 2, when the register $1 is in the E, M, and A levels, it means that it is within the feedback range. Once this range is exceeded, such as register $1 is used in the bottom instruction, it is defined as Subsequent instructions for register $1 are out of feedback range.

(2) On the basis of the above-mentioned expansion of the MIPS instruction set, the "life length" adjustment logic is added at the execution level, memory access level, and alignment level: that is, if the current register variable is used by subsequent instructions, its "life length" will be reduced. Small 1; once the "life length" of the current register variable is found to be 0, it is discarded through the selector-register based masking logic. The specific steps are: 1. If the instruction destination register currently at the execution level, memory access level, or alignment level is used by an instruction at the decoding level, the "lifetime" tag in the current instruction will be decremented by 1; 2. If the value of the "life length" tag in the current instruction is reduced to 0, the data passed to the next level will remain unchanged, and the signal representing the write back of the register file will be invalidated, so that the last write Rollback does not write the register variable back. It is worth noting that the above steps have the same structure at the execution level, memory access level and alignment level.

Further, the present invention also provides an algorithm for static calculation of the life length of instruction registers. The algorithm is implemented by a software tool that can statically traverse the generated assembly code to determine the "life length" of the register variable in the instruction that needs to be added to the "life length". length" and embed it into the redundant bits of the current instruction.

The algorithm for the static calculation of the life length of the instruction register includes a main algorithm and two sub-algorithms. Judgment calculation (outOfGroupWriteDiscardingJudgement), referred to as Algorithm III; see the appendix for the code of the static estimation algorithm for the life length of the instruction register. the

The main algorithm calls two sub-algorithms, and the steps of the main algorithm are as follows:

(1) For each instruction in the assembly code of the current program, first call Algorithm II to calculate the life cycle life and write discard signal wd in the group, if Algorithm II returns a valid wd signal (indicating that Algorithm II is determined to be in the group The register can be discarded), then Algorithm I will determine the life of the instruction register as life, if life is equal to 4, it indicates that the register of the instruction in the group cannot be discarded, and Algorithm I will set life to 4, otherwise Indicates that calling Algorithm II alone cannot determine whether to discard;

(2) Algorithm III is further called, if Algorithm III determines that it can be discarded, then set the register life cycle of the instruction as the return value of Algorithm III, otherwise set it to 4.

Algorithm II is inference within the group, and its steps are as follows:

(1) Select 3 subsequent instructions after the current instruction to form a group (group). When the current instruction is in the delay slot, two groups can be obtained according to whether the branch occurs or not, as shown in Appendix (II-a) Show;

(2) Define three concepts: distance, that is, distance, indicating how many clock cycles the register of the current instruction will be used by subsequent instructions, if the distance is greater than 3, it will be set to 4, dependent, that is, dependency, Indicates whether the current instruction depends on the first instruction. Dependency means that the operand of the current instruction comes from the destination register of the first instruction. rewrite, that is, overwrite, indicates whether the destination register of the current instruction is consistent with the first instruction. is overwritten, otherwise it is not overwritten; as shown in Appendix (II-b);

(3) Algorithm II first obtains the instruction group corresponding to the current instruction, then fills in the form shown in Appendix (II-b), and then starts to check the subsequent instructions one by one. A. If an instruction is found to depend on the first instruction, and the distance If it is 4, set the life cycle of the first instruction to 4 and exit; B. If there is a dependency and the distance is less than 4, add 1 to the life cycle; C. If there is an overwrite, determine whether the life cycle is 4, If it is, it cannot be discarded, otherwise it can be discarded, returning to the life cycle, as shown in Appendix (II-c).

Algorithm III is an out-of-group judgment. Since this algorithm can traverse the entire program, considering the possible branch points in the program, a container is introduced to save the branch points in the program. The specific steps of Algorithm III are:

(1) If it is determined that the current instruction is used by a subsequent instruction, it means that the register of the current instruction cannot be discarded, return 0, and end;

(2) Otherwise, if it is judged that the register of the current instruction is overwritten by a subsequent instruction or the end exit of the program is reached, the next round of judgment is started;

(3) If the next instruction is a conditional branch instruction, it must be judged at the same time whether the branch occurs in two ways. Here, the branch node is stored in the branch container. It should be noted that if the branch node is found in the branch container, It means that the branch point has been reached before, which means that there is a ring, and the ring needs to be removed, otherwise the branch will be stored in the container, and the successful branch will be judged first, and then the failed branch will be judged until the step ( 2) The conditions mentioned in 2) end the algorithm.

After the software code is generated by the compiler, the method of the present invention adopts a strategy of global traversal to determine the "life length" of a certain register variable accessed by subsequent instructions. The algorithm proposed by the present invention has the ability to infer the life length of register variables during static compilation, and through the support of the instruction structure, the life length of the register is embedded in the instruction, and the life length of the variable is dynamically adjusted during operation. The length determines whether to write back, if the life length is zero, the write back to the register can be masked. The invention saves unnecessary write-back operations of registers, thereby reducing the power consumption of register files.

Compared with the existing architecture, the software-guided register file write-back discarding method provided by the present invention can effectively find register variables that can be discarded with almost no increase in hardware overhead, thereby reducing the power consumption of the register file and power density.

Description of drawings

Figure 1 is a traditional 6-stage pipeline microprocessor architecture.

Figure 2 is an example of the definition of the register lifetime.

Figure 3 is the specific judgment logic of register file write discard.

Fig. 4 is a specific implementation strategy of instruction register lifetime tag insertion.

Detailed ways

The present invention describes a software-directed register file write-back discard technique. Various examples of the present invention and design ideas therein are described below.

Figure 2 is an example used to illustrate the definition of register lifetime. If there are 1, 2, or 3 subsequent instructions within the feedback range that use the destination register of the current instruction, its life is defined as 1, 2, or 3. If there are instructions beyond the feedback range that use the register, its life is defined For 4, a specific example, in Figure 2, if the $1 register is only used by its subsequent three instructions (ie subu $3, $1, $7, lw $10, 4($1) and mul $11, $6, $1, these three instructions), Then its life is 3, but if the instruction shown in red (slt $3, $1, $8) also uses $1, then this instruction exceeds the feedback range of $1, and the life length of $1 will be set to 4. Among them, the definition of the feedback range is: when a certain instruction Y at the decoding level (D level) uses register X, and the instruction Z that generates register X is at E, M or A level, then the Y instruction is said to be in Z instruction generates register X within the feedback range.

Figure 3 shows the specific judgment logic of register file write discard. Compared with the traditional structure in Figure 1, this structure adds the judgment logic for the life cycle tag. Figure 3 uses the E-level as an example to describe, and the M-level and A-level structures are exactly the same. First judge whether the register of the current instruction is fed back to the D stage (the feedback hit signal must be valid (that is, the signal bypass-hit signal shown in Figure 3 is valid) and the d stage at this time cannot be blocked (that is, as shown in Figure 3 The d_stall signal is 0)), if it is, the current life cycle tag will be self-decremented, and then judge whether the current tag is 0. If it is zero, it means that the life of the current instruction register is 0, which can be discarded. The discarding adopts register-based -The circuit structure of the selector. The characteristic of this structure is that if the life tag is 0, the register data passed to the next level is kept unchanged, and the representative register file writes back the signal X_wr_sig (X represents E, M and A , the E-level example in Figure 3, so X is E) will be set to 0, thereby shielding the write-back of the register file.

Fig. 4 shows the specific implementation strategy of instruction register lifetime tag insertion. In the actual logic design, we distinguish between R-type instructions and I-type instructions. For R-type instructions, since there are always 5 bits of redundant bits, tags can be inserted into the redundant bits. For I-type instructions, it is necessary to distinguish the range of the immediate value. If the range of the immediate value is between -4096~4095, the tag can be inserted into the upper 3 bits of the immediate value field. Otherwise, a new instruction lli is introduced, and then the The original instruction is split into an lli instruction and an R-type instruction. The life cycle of the lli instruction is 1 and the life cycle tag of the R-type instruction is consistent with the previous I-type instruction, and there can be 5 bits of redundant bits to insert the tag.

The appendix presents an algorithm for statically determining/speculating the lifetime of instruction register variables via compile-time. The algorithm listed in Algorithm I is the overall algorithm, and two sub-algorithms are called, namely: inGroupLifetimeCalculation (in-group life cycle calculation, as shown in Appendix (II)) and outOfGroupWriteDiscardingJudgement (outside-group write discard judgment, as shown in Appendix (III) ) shown). The steps of Algorithm I are: For each instruction in the assembly code of the current program, first call Algorithm II to calculate the life cycle life and write discard signal wd in the group, if Algorithm II returns a valid wd signal (indicating that Algorithm II is determined to be The register in the group can be discarded), then Algorithm I determines the life of the instruction register as life, if life is equal to 4, it indicates that the register of the instruction in the group cannot be discarded, and Algorithm I sets life to 4 , otherwise it means that the single-call Algorithm II cannot determine whether to discard, and Algorithm III is further called. If Algorithm III determines that it can be discarded, the register lifetime of the instruction is set to the return value of Algorithm III, otherwise it is set to 4.

Algorithm II is inference within a group, and its steps are: select 3 subsequent instructions following the current instruction to form a group (group). When the current instruction is in the delay slot, two groups can be obtained according to whether the branch occurs or not, such as shown in Appendix (II-a). As shown in the appendix (II-b), three more concepts are defined: distance (distance, indicating how many clock cycles the register of the current instruction will be used by subsequent instructions, if the distance is greater than 3, it will be set to 4 ), dependent (dependency, indicating whether the current instruction depends on the first instruction, dependent means that the operand of the current instruction comes from the destination register of the first instruction), rewrite (overwriting, indicating whether the destination register of the current instruction is the same as the first instruction) If an instruction is consistent, it is overwritten if it is consistent, otherwise it is not overwritten). As shown in Appendix (II-c), Algorithm II first obtains the instruction group corresponding to the current instruction, then fills in the form shown in Appendix (II-b), and then starts to check the subsequent instructions one by one. 1. If any instruction is found to depend on the first One instruction, and the distance is 4, set the life cycle of the first instruction to 4 and exit; 2. If there is a dependency and the distance is less than 4, add 1 to the life cycle; 3. If there is an overwrite, judge Whether the life cycle is 4, if it is, it cannot be discarded, otherwise it can be discarded, and returns the life cycle.

Algorithm III is an out-of-group judgment. Since this algorithm can traverse the entire program, considering the possible branch points in the program, a container is introduced to save the branch points in the program. The steps of Algorithm III are: 1. If it is determined that the current instruction is used by a subsequent instruction, it means that the register of the current instruction cannot be discarded, return 0, and end; 2. Otherwise, if it is determined that the register of the current instruction is overwritten by a subsequent instruction 3. If the next instruction is a conditional branch instruction, it must be judged whether the branch occurs in two ways at the same time. Here, the branch node is stored in the branch container. It should be noted that if the branch node is found in the branch container, it means that the branch point has been reached before, which means that there is a loop, and the loop needs to be removed, otherwise the branch will be stored in the container, and the successful branch will be determined first , and then judge the failed branch until the condition mentioned in 2 is reached, and the algorithm ends.

appendix

Algorithm: static speculation of life cycle

Input: source program assembly code

Parameters: current command curr_instr , source program src_instr

Life cycle life , write back discard wd , counter i, number of instructions instr_#

Output: life cycle array life_arr

Initialization: convert assembly code into intermediate expression

00: foreach( i∈ [ 0, instr_# ))

01: curr_instr = getInstr ( i ); src_instr = curr_instr

02: wd = inGroupLifetimeCalculation (& curr_instr , & life )

03: if ( wd ) life_arr [ i ] = life ; continue ; endif /* wd is valid , take the next instruction */

04: if ( life == 4) life_arr [ i ] = 4; continue ; endif /* cannot be discarded , next instruction */

05: wd = outOfGroupWriteDiscardingJudgement ( src_instr , curr_instr )

06: if ( wd ) life_arr [ i ] = life ; continue ; endif /* wd is valid, take the next instruction */

07: life_arr [ i ] = 4 /* Conservative speculation, the life cycle is 4, fetch the next instruction */

08: endfor

(I)

                                                

Algorithm: Intra-group life cycle calculation

Input: current instruction curr_instr , life cycle life

Parameters: group of four instructions , accelerator i, column distance , dependent , rewrite

output: write discard wd

Initialization: group = getGroup ( curr_instr ); fillThreeColumns ( group ); i = 0; life = 0; wd = 0

00: while ( i ≤2 && ( dependent [ i ] || ! rewrite [ i ]))

01: if( dependent [ i ] && distance [ i ] == 4) life = 4; wd = 0; break ; endif

02: if( dependent [ i ] && distance [ i ] != 4) life ++; endif ;

03: if ( rewrite [ i ]) break ; endif ; i ++

04: endwhile

05: if ( rewrite [ i ] && life != 4) wd = 1; return wd ; endif /* rewrite in-range detected */

06: updateCurrInstrToLastInstrOfGroup ( group ); return wd

(c)

(II)

Algorithm: write discard judgment outside the group

Input: source program src_instr , current instruction curr_instr

Parameters: next instruction next_instr , the branch point container bp

00 : bp.clear ( ); bp.push_back ( curr_instr )

01: while( ! bp . empty ())

02: next_instr = getNextInstr ( bp . pop_back ())

03: while( 1)

04: if ( isConsumer ( src_instr , next_instr )) return 0; endif /* found to write after reading */

05: if ( isRewrite ( src_instr , next_instr ) || isReachEnd ( next_instr ))

06: break; endif /* no write after reading, the next round of speculation */

07: if ( isConditionalBranch ( next_instr ))

08: if ( bp . find ( next_instr )) break; endif /* ring detected, next round of speculation */

09: bp . push_back ( next_instr ) /* no loop, save branch point to container */

10 : next_instr = getInstrFromBranchSucc ( next_instr ) /* branch succes succ */

11 : endif

12: else next_instr = getNextInstr ( next_instr ) endelse

13: endwhile

14: endwhile

15: return 1

(III)

Claims (2)

1. A low-power register file write-back discarding method is based on the MIPS microprocessor of the existing basic pipeline structure, and the existing microprocessor includes an instruction fetching stage, a decoding stage, an execution stage, Memory access level, alignment level and write-back level; characterized in that the specific steps are: (1) For the microprocessor, expand the original MIPS instruction set, and add 3-bit "life length" to the instructions with redundant bits to represent that the current register variable will be used by several subsequent instructions; Among them, the life length of register X is defined as follows: When register X is at the execution level (E), memory access level (M), and alignment level (A), if 1, 2, or 3 of registers X are within their feedback range Register X is required for the subsequent instructions of register X, and the life length of register X is correspondingly designated as 1, 2, 3; if register X needs to use register X for subsequent instructions beyond the feedback range, the life length of register X is is defined as 4; (2) On the basis of the above-mentioned expansion of the MIPS instruction set, the "life length" adjustment logic is added at the execution level, memory access level, and alignment level: that is, if the current register variable is used by subsequent instructions, its "life length" will be reduced. Small 1; once the "life length" of the current register variable is found to be 0, it is discarded through the selector-register based masking logic. 2. The method according to claim 1, characterized in that, further static calculation of the life length of the instruction register is performed, the calculation is realized by a software tool, and the software tool statically traverses the generated assembly code to determine the "life length" that needs to be added. The "life length" of the register variable in the instruction, and embed it into the redundant bit of the current instruction; the algorithm for the static calculation of the instruction register life length includes: a main algorithm and two sub-algorithms, the main algorithm is referred to as Algorithm I , the two sub-algorithms are: life cycle calculation within the group, referred to as Algorithm II, write discard judgment calculation outside the group, referred to as Algorithm III; the steps of the main algorithm are as follows: (1) For each instruction in the assembly code of the current program, first call Algorithm II to calculate the life cycle life and write discard signal wd in the group. If Algorithm II returns a valid wd signal, it means that Algorithm II is determined to be in the group. If the register can be discarded, Algorithm I will determine the life of the instruction register as life; if life is equal to 4, it indicates that the register of the instruction in the group cannot be discarded, and Algorithm I will set life to 4; Calling Algorithm II cannot determine whether to discard; so (2) Further call Algorithm III, if Algorithm III determines that it can be discarded, set the register lifetime of the instruction as the return value of Algorithm III, otherwise set it to 4; Among them, the steps of Algorithm II are as follows: (1) Select 3 subsequent instructions following the current instruction to form a group (group). When the current instruction is in the delay slot, two groups are obtained according to whether the branch occurs or not; (2) Define three concepts: distance, that is, distance, indicating how many clock cycles the register of the current instruction will be used by subsequent instructions. If the distance is greater than 3, it will be set to 4; dependent, that is, dependency, indicating Whether the current instruction depends on the first instruction, which means that the operand of the current instruction comes from the destination register of the first instruction; rewrite, that is, overwrite, indicates whether the destination register of the current instruction is consistent with the first instruction, and if it is consistent, it is Overwrite, otherwise not overwrite; (3) Algorithm II first obtains the instruction group corresponding to the current instruction, and then fills in the table corresponding to the three concepts in step (2): distance, dependent, and rewrite, and then starts to check the subsequent instructions one by one. A. If there is an instruction dependency Based on the first instruction and the distance is 4, set the life cycle of the first instruction to 4 and exit; B. If there is a dependency and the distance is less than 4, add 1 to the life cycle; C. If there is an overwrite, Then judge whether the life cycle is 4, if it is, it cannot be discarded, otherwise it can be discarded, and return to the life cycle; Algorithm III steps are as follows: (1) If it is determined that the current instruction is used by a subsequent instruction, it means that the register of the current instruction cannot be discarded, return 0, and end; (2) Otherwise, if it is judged that the register of the current instruction is overwritten by a subsequent instruction or the end exit of the program is reached, the next round of judgment is started; (3) If the next instruction is a conditional branch instruction, it must be judged at the same time whether the branch occurs in two ways. Here, the branch node is stored in the branch container. If the branch node is found in the branch container, it means that the branch node has been reached before Passing this branch point means that there is a ring, and the ring needs to be removed, otherwise, the branch will be stored in the container, and the branch that succeeds in branching will be judged first, and then the branch that failed to branch will be judged until reaching the step (2). conditions, the algorithm ends.

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