CN103403691A

CN103403691A - Information processing device, external storage device, host device, relay device, control program, and control method of information processing device

Info

Publication number: CN103403691A
Application number: CN2011800684960A
Authority: CN
Inventors: 桥本大辅
Original assignee: Toshiba Corp
Current assignee: Kioxia Corp
Priority date: 2011-03-10
Filing date: 2011-09-26
Publication date: 2013-11-20
Anticipated expiration: 2031-09-26
Also published as: US8667216B2; US20140223088A1; US11544131B2; US8631191B2; US20120284453A1; US20190266038A1; US8683117B2; US20180004587A1; EP2684136A1; EP2684136B1; US8756367B2; CN103403691B; TW201239622A; KR101475645B1; US20130212325A1; US20210141681A1; US9785494B2; JP5002719B1; WO2012120717A1; US20160041858A1

Abstract

According to one embodiment, when the switching condition for switching to the read-only mode is satisfied, the external storage device switches to an interface controller that only supports the read operation of the non-volatile memory. When it is determined to be identified as a ROM based on information acquired from the external storage device, the host device switches to an interface driver that only supports the read operation of the nonvolatile memory.

Description

Information processing device, external storage device, host device, relay device, control program, and method for controlling information processing device

Cross Reference to Related Applications

This application is based on and claims the benefit of priority from japanese patent application No. 2011-. The entire contents of these applications are incorporated herein by reference.

Technical Field

Embodiments described herein relate generally to an information processing apparatus, an external storage apparatus, a host apparatus, a relay apparatus, a control program, and a control method of an information processing apparatus.

Background

As an external storage device used in a computer system, an SSD (solid state drive) mounted with a nonvolatile semiconductor memory such as a nand-type flash memory attracts attention. The flash memory has advantages such as high speed and light weight compared to a magnetic disk device. The SSD includes: a plurality of flash memory chips; a controller which performs read/write control on a corresponding flash memory chip in response to a request from a host device; a buffer memory for data transfer between a corresponding flash memory chip and a host device; a power supply circuit and a connection interface to a host device.

Drawings

Fig. 1 is a block diagram illustrating a functional configuration example of the computer system of the first embodiment.

Fig. 2 is a block diagram illustrating an internal configuration example of a nand memory chip.

Fig. 3 is a circuit diagram illustrating a configuration example of one plane contained in the nand memory chip.

Fig. 4 is a view illustrating a threshold distribution in the four-value data storage method.

Fig. 5 is a block diagram illustrating a functional configuration example of a computer system when the SSD control tool is saved in the SSD.

Fig. 6 is a block diagram illustrating a functional configuration example of a computer system when the SSD control tool is saved in another external storage device.

Fig. 7 is a block diagram illustrating a functional configuration example of a computer system when installing an SSD control tool from a web page.

Fig. 8 is a block diagram illustrating a functional configuration example of a computer system when the SSD control tool from the optical drive is installed.

Fig. 9 is a block diagram illustrating a functional configuration example of a computer system when the SSD control tool from the USB memory is installed.

Fig. 10 is a view illustrating an appearance configuration of a computer system.

Fig. 11 is a block diagram illustrating a functional configuration example of a host.

Fig. 12 is a block diagram illustrating a hierarchical functional configuration example of a host.

Fig. 13 is a view illustrating management information of the SSD.

Fig. 14 is a flowchart illustrating an example of a write operation of the SSD.

FIG. 15 is a flow chart illustrating an example of operation of garbage collection of NAND memory of an SSD.

Fig. 16 is a flowchart illustrating an example of a read operation of the SSD.

Fig. 17 is a flowchart illustrating an example of an operation when an SSD generates an error.

Fig. 18 is a flowchart illustrating an operation example when a read-only mode switch condition is satisfied in the SSD.

Fig. 19 is a graph illustrating a relationship between raw data of statistical information and a defect rate of an SSD.

Fig. 20 is a graph illustrating a relationship between raw data of statistical information and performance of an SSD.

Fig. 21 is a flowchart illustrating an operation example at the time of SSD startup.

Fig. 22 is a flowchart illustrating an operation example at host startup.

FIG. 23 is a flow chart illustrating an example of operation during host operation.

Fig. 24 is a view illustrating an example of a driver display screen in the host.

Fig. 25 is a flowchart illustrating another operation example at host startup.

Fig. 26 is a view illustrating one example of a management table of statistical information X01 to X19, X23, X24.

Fig. 27 is a flowchart illustrating another operation example at the time of host startup.

Fig. 28 is a block diagram illustrating another configuration example of a host.

Fig. 29 is a flowchart illustrating an operation example at the time of host startup when the host illustrated in fig. 28 is employed.

Fig. 30 is a block diagram illustrating a functional configuration example of the computer system of the second embodiment.

Fig. 31 is a block diagram illustrating a functional configuration example of the computer system of the third embodiment.

Fig. 32 is a view illustrating an appearance configuration example of the computer system of the fourth embodiment.

Fig. 33 is a block diagram illustrating a functional configuration example of the computer system of the fourth embodiment.

Detailed Description

In general, according to one embodiment, an information processing apparatus includes a host apparatus and an external storage apparatus. The external storage device includes: a read-write nonvolatile memory; an interface controller connected to a host device; and a first control unit. The interface controller determines whether a switching condition to switch to a read-only mode that causes the nonvolatile memory to perform only a read operation is satisfied, and when the switching condition is satisfied, the first control unit causes the interface controller to switch from the first interface controller to the second interface controller. The host device includes: an interface driver for operating an external storage device; and a second control unit. The second control unit determines whether to recognize the nonvolatile memory as a read only memory that can perform only a read operation based on information obtained from the external storage device, and causes the interface driver to switch from the first interface driver to the second interface driver when it is determined to be recognized as the read only memory.

When data is stored in a nonvolatile semiconductor storage element such as a nand-type flash memory, after data is erased at a time, writing is performed in units of blocks, reading/writing is performed in units of pages, or the erasing/reading/writing unit is fixed. On the other hand, a unit in which a host apparatus (such as a personal computer) writes data to an auxiliary storage device (such as a hard disk) and reads the data from the auxiliary storage device is called a sector. The sectors are set as erase, write and read units independent of the semiconductor storage device. For example, the unit of erasing, writing, and reading of the nonvolatile semiconductor memory may be larger than the unit of writing/reading of the host device.

When an auxiliary storage device of a personal computer is configured using a flash memory, a block (defective block, damaged block) that cannot be used as a storage area due to various error causes and an area (defective area) that cannot be read may be generated. If the number of defective blocks or the number of defective areas exceeds the upper limit, new defective blocks or defective areas cannot be recorded, and it is not guaranteed that both data stored in the buffer memory (cache memory) and data requested to be written are written to the flash memory. Therefore, when the number of defective blocks or the number of defective areas exceeds a predetermined value, the ability to write data may be suddenly lost despite the available space in the flash memory.

As a solution to the above problem, there is a method of managing the number of lossy clusters and the number of lossy blocks generated in the nand-type flash memory and converting an operation mode when data is written from a host device to the nand-type flash memory according to the number of lossy clusters and the number of lossy blocks. A cluster is a management unit used as a logical address in an SSD. The size of the cluster is twice or more natural number times the size of the sector, and the cluster address is configured by a high-order bit sequence of predetermined bits from the LBA.

In this method, the operation mode of the SSD is divided into the following three modes.

WB mode (write-back mode): data is written to the cache memory at one time and removed to normal operation of the nand type flash memory based on predetermined conditions.

WT Mode (Write Through Mode): an operation mode in which data written to the cache memory is written to the nand type flash memory with one write request at a time. Data written from the host is guaranteed as much as possible by writing to the nand-type flash memory at a time. When the number of remaining entries of the lossy cluster table or the lossy block table is less than or equal to a predetermined number, the SSD transitions to the WT mode.

RO mode (read-only mode): the mode of all processes involving writing to nand type flash memory is disabled. When an SSD is near the end of its life, data that has been written from the host is guaranteed as much as possible by returning an error for all write requests from the host to not perform a write. When the number of remaining entries of the lossy cluster table or the lossy block table is less than or equal to a predetermined number or when the free blocks are insufficient, the SSD transitions to the RO mode.

In WB mode and WT mode, the SSD accepts read requests and write requests from the host and processes the read requests and write requests. In RO mode, the SSD accepts a read request from the host and processes the read request, but does not process a write request from the host and returns an error.

When the SSD is connected to a host installed with an Operating System (OS), such as Windows (registered trademark), the host transmits a write request to the SSD, and when the write request is normally processed, the host recognizes the SSD as an available external storage device.

If the host transmits a write request to the SSD when the SSD transitioned to the RO mode is connected to the host installed with Windows (registered trademark), the SSD returns an error to the host, and thus the host may not recognize the SSD as an available external storage device. Therefore, even if the SSD in the RO mode that can be read is connected to the host, the data recorded in the past may not be read from the SSD.

In the present embodiment, the SSD switched to the RO mode may be generally recognized by the host as a device that can perform only a read operation.

Exemplary embodiments of an information processing apparatus, an external storage apparatus, a host apparatus, a relay apparatus, and a control method of the information processing apparatus will be described in detail below with reference to the accompanying drawings. The present invention is not limited to the following examples.

(first embodiment)

Fig. 1 illustrates a configuration of a first embodiment of a computer system. The computer system 1 is configured by an SSD10 serving as an external storage device, a host 100, and an ATA interface 90 serving as a memory interface connecting the SSD10 and the host 100. The external storage device may be other read-write nonvolatile storage device other than the SSD10, such as a hard disk drive, a hybrid hard disk drive, a USB memory, or an SD card. The host 100 may be a personal computer, may be an imaging device such as a still camera or a video camera, or may be a tablet computer, a smart phone, a game machine, a car navigation system, or the like.

As illustrated in fig. 1, SSD10 includes: a NAND-type flash memory (hereinafter abbreviated as NAND memory) 20 serving as a nonvolatile semiconductor memory; an interface controller 30 for transmitting and receiving signals with a host 100 through an ATA interface 90; a RAM (random access memory) 40 serving as a volatile semiconductor memory including a Cache Memory (CM) 40a serving as an intermediate buffer of the interface controller 30 and the NAND memory 20; a memory controller 50 which is responsible for managing and controlling the NAND memory 20 and the RAM40, and controlling the interface controller 30; an IPL (initial program loader) 55 serving as a boot loader for executing various kinds of boot programs including initialization at startup of the SSD 10; an ECC correction circuit 58 for performing an error correction process on data read out from the NAND memory 20; and a bus 57 for connecting all the constituent elements. The IPL55 may be disposed in storage controller 50. In the present embodiment, the ATA interface is configured as a serial ATA (sata) interface. Other interfaces, such as a parallel ata (pata) interface, may be used in place of SATA interface 90. Other interfaces, such as a USB (universal serial bus) interface, a PCI Express interface, a Thunderbolt (registered trademark) interface, or a serial attached scsi (sas) interface, may be used instead of the ATA interface 90.

For the RAM40, DRAM (dynamic random access memory), SRAM (static random access memory), FeRAM (ferroelectric random access memory), MRAM (magnetoresistive random access memory), PRAM (phase change random access memory), or the like can be employed. The RAM40 may be disposed in the storage controller 50.

The NAND memory 20 stores therein user data specified by the host 100, stores a management table managing the user data, and stores management information managed in the RAM40 for backup. The NAND memory 20 includes a memory cell array in which a plurality of memory cells are arranged in a matrix form, wherein each memory cell can store a plurality of values using an upper page and a lower page. The NAND memory 20 is configured by a plurality of memory chips, and each memory chip is configured by arranging data blocks or cells erased in plural. In the NAND memory 20, reading and writing of data are performed in units of pages. The block includes a plurality of pages.

Fig. 2 illustrates an internal configuration example of a NAND memory chip configuring the NAND memory 20. The NAND memory 20 includes one or more NAND memory chips 20080. The nand memory chip 20080 includes a memory cell array in which a plurality of memory cells are arranged in a matrix form. The memory cell transistors configuring the memory cell array are configured by MOSFETs (metal oxide semiconductor field effect transistors) having a stacked gate structure formed on a semiconductor substrate. The stacked gate structure includes: a charge accumulation layer (floating gate electrode) formed on the semiconductor substrate with the gate insulating film interposed therebetween; and a control gate electrode formed on the floating gate electrode with the gate insulating film interposed therebetween. The memory cell transistor has a threshold voltage that varies according to the number of electrons accumulated in the floating gate electrode, and stores data according to a difference between the threshold voltages. In the present embodiment, a case has been described in which the individual memory cell is a writing method using a 2-bit/cell four-value storage method of the upper page and the lower page. But even in the case where the individual memory cells are a writing method using a two-value storage method of 1 bit/cell of a single page or a writing method using an eight-value storage method of 3 bits/cell of upper, middle and lower pages, the essence of the present invention is not changed. The memory cell transistor is not limited to a structure including a floating gate electrode, and may be a structure in which a threshold voltage is adjusted by trapping electrons at a nitride interface serving as a charge accumulation layer such as MONOS (metal oxide silicon oxynitride). The MONOS type memory cell transistor may be similarly configured to store 1 bit or may be configured to store a plurality of values. Further, as the nonvolatile storage medium, a semiconductor storage medium in which memory cells are three-dimensionally arranged as described in U.S. patent application publication No. 20100172189 and U.S. patent application publication No. 20100254191 may be employed.

As illustrated in fig. 2, the nand memory chip 20080 includes a memory cell array 20082 in which memory cells for storing data are arranged in a matrix form. The memory cell array 20082 includes a plurality of bit lines, a plurality of word lines, and a common source line, wherein memory cells to which data can be electrically rewritten are arranged in a matrix form at intersections of the bit lines and the word lines. A bit control circuit 20083 for controlling bit lines and a word line control circuit 20085 for controlling word line voltages are connected to the memory cell array 20082. In other words, the bit line control circuit 20083 reads out data of the memory cell in the memory cell array 20082 through the bit line, and applies a write control voltage to the memory cell in the memory cell array 20082 through the bit line to perform writing to the memory cell.

The column decoder 20084, the data input/output buffer 20089 and the data input/output terminal 20088 are connected to the bit line control circuit 20083. Data of the memory cell read out from the memory cell array 20082 is output from the data input/output terminal 20088 to the outside through the bit line control circuit 20083 and the data input/output buffer 20089. Write data externally input to the data input/output terminal 20088 is input to the bit line control circuit 20083 through the data input/output buffer 20089 by the column decoder 20084, and is written into a specified memory cell.

The memory cell array 20082, the bit line control circuit 20083, the column decoder 20084, the data input/output buffer 20089, and the word line control circuit 20085 are connected to the control circuit 20086. The control circuit 20086 generates a control signal and a control voltage according to a control signal input to the control signal input terminal 20087 to control the memory cell array 20082, the bit line control circuit 20083, the column decoder 20084, the data input/output buffer 20089, and the word line control circuit 20085. A circuit portion other than the memory cell array 20082 of the nand memory chip 20080 is referred to as a nand controller (NANDC) 20081.

Fig. 3 illustrates a configuration of the memory cell array 20082 illustrated in fig. 2. The memory cell array 20082 is a nand memory cell type memory cell array, and is configured to include a plurality of nand cells. The nand cell is configured of a memory string MS including memory cells connected in series and select gates S1 and S2 connected to both ends of the memory string MS. The select gate S1 is connected to the bit line BL, and the select gate S2 is connectedTo the source line SRC. The control gates of the memory cells MC arranged in the same row are commonly connected to word lines WL 0-WL_m-1. The first select gate S1 is commonly connected to a select line SGD, and the second select gate S2 is commonly connected to a select line SGS.

The memory cell array 20082 includes one or more planes including a plurality of blocks. Each block is configured of a plurality of nand cells, and data is erased in units of blocks.

A plurality of memory cells connected to one word line constitute one physical sector. Data is written and read out for each physical sector (a physical sector is not related to a logical sector of an LBA described below). In the case of the 2-bit/cell write method (four values), two pages of data are stored in one physical sector, in the case of the 1-bit/cell write method (two values), one page of data is stored in one physical sector, and in the case of the 3-bit/cell write method (eight values), three pages of data are stored in one physical sector.

In a read operation, a program verify operation, and a program operation, one word line and one physical sector are selected according to a physical address received from the memory controller 50. Pages in a physical sector are switched by physical addresses. In the present embodiment, the NAND memory 20 is a 2-bit/cell write method, and the memory controller 50 performs processing assuming that two pages (an upper page and a lower page) are allocated as physical pages to a physical sector, where physical addresses are allocated to all the pages.

The 2-bit/cell four-value NAND memory is configured such that threshold voltages in one memory cell have four distribution patterns. Fig. 4 illustrates a relationship between two-bit four-value data (data "11", "01", "10", "00") stored in a memory cell of a four-value nand memory cell flash memory and a threshold voltage distribution of the memory cell. In FIG. 4, V_A1Is the voltage, V, applied to the selected word line when reading two data for a physical sector in which only the lower page has been written but the upper page has not been written_A1VIndicating application for verification when performing a write to A1A verify voltage of whether the writing is completed.

V_A2、V_B2、V_C2Is the voltage, V, applied on the selected word line when reading four data for a physical sector in which only the lower and upper pages have been written_A2V、V_B2V、V_C2VA verify voltage applied when performing writing on each threshold voltage distribution so as to verify whether the writing is completed is indicated. Vread1, Vread2 indicates the read voltages applied to the unselected ones of the nand memory cells when performing a data read out in order to conduct the associated unselected memory cells without regard to the data held. In addition, V_ev1、V_ev2An erase verify voltage, which indicates an erase verify voltage applied to a memory cell when erasing data of the memory cell in order to verify whether or not erasing is completed, has a negative value. The magnitude is determined in view of the disturbing influence of neighboring memory cells. The magnitude of each voltage is as follows:

V_ev1<V_A1<V_A1V<Vread1

V_ev2<V_A2<V_A2V<V_B2<V_B2V<V_C2<V_C2V<Vread2

as described above, the erase verify voltage V_ev1、V_ev2、V_ev3Is negative, but the voltage actually applied to the control gate of the memory cell MC in the erase verify operation is not negative but is zero or positive. That is, in the actual erase verify operation, a positive voltage is applied to the back gate of the memory cell MC, and a voltage having a zero value or a positive value smaller than the back gate voltage is applied to the control gate of the memory cell MC. In other words, the erase verify voltage V_ev1、V_ev2、V_ev3Is equivalently a voltage having a negative value.

The threshold voltage distribution ER of the memory cells after the block erase has a negative upper limit value and is allocated with data "11". Memory cells of data "01", "10", and "00" in a state in which both the lower page and the upper page have been written have positive threshold voltage distributions a2, B2, C2 (the lower limit values of a2, B2, C2 are also positive values), wherein, when the threshold voltage distribution a2 of the data "01" has the lowest voltage value, the threshold voltage distribution C2 of the data "00" has the highest voltage value, and the voltage values of the plural types of threshold voltage distributions have the following relationships: a2< B2< C2. The memory cells of data "10" in the state where the lower page has been written but the upper page has not been written have a positive threshold voltage distribution A1 (the lower limit of A1 is also a positive value). The threshold voltage distribution illustrated in fig. 4 is only one example, and the present invention is not limited thereto. For example, threshold voltage distributions a2, B2, C2 are all illustrated as positive threshold voltage distributions in fig. 4, but it is within the scope of the present invention for threshold voltage distribution a2 to be a negative voltage distribution and for threshold voltage distributions B2 and C2 to be positive voltage distributions. Even if the threshold voltage distributions ER1 and ER2 are positive values, the present invention is not limited thereto. In the present embodiment, the correspondence relationship of the data of ER2, a2, B2, and C2 is described as "11", "01", "10", and "00", but may be other correspondence relationships such as "11", "01", "00", and "10".

The 2-bit data of one memory cell includes lower page data and upper page data, wherein the lower page data and the upper page data are written into the memory cell by different write operations (i.e., two write operations). It should be noted that "^*"represents upper page data, and represents lower page data.

First, writing of lower page data will be described with reference to the first stage to the second stage of fig. 4. It is assumed that all memory cells have the threshold voltage distribution ER in the erased state and store data "11". As illustrated in FIG. 14, when writing of lower page data is performed, the threshold voltage distribution ER of the memory cells is divided into two threshold voltage distributions (ER 1, A1) according to the value ("1" or "0") of the lower page data. If the lower page data has a value of "1", the threshold voltage distribution ER of the erase state is maintained, and therefore ER1= ER, but ER1> ER may be used.

If the value of the lower page data is "0", thenA high electric field is applied to the tunnel oxide film of the memory cell, electrons are injected to the floating gate electrode, and the threshold voltage V of the memory cell_thRises by a predetermined amount. Specifically, the verify potential VAIV is set, and the write operation is repeated until a threshold voltage greater than or equal to the verify voltage VAIV is reached. Therefore, the memory cell becomes a write state (data "10"). If the threshold voltage is not reached even if the writing operation is repeated a predetermined number of times (or if the number of memory cells that do not reach the threshold voltage is greater than or equal to a predetermined value), the writing status with respect to the physical page becomes "write error".

Writing of the upper page data will be described below with reference to the second to third stages of fig. 4. Writing of the upper page data is performed based on write data (upper page data) input from outside the chip, the lower page data having been written in the memory cell.

In other words, as illustrated in the second to third stages of fig. 4. If the upper page data has a value of "1", a high electric field is prevented from being applied to the tunnel oxide film of the memory cell, thereby preventing the threshold voltage V of the memory cell_thIs increased. Therefore, the memory cell of data "11" (threshold voltage distribution ER1 of the erased state) holds data "11" as (ER 2), and the memory cell of data "10" (threshold voltage distribution a 1) holds data "10" as (B2). However, from the viewpoint of ensuring a voltage margin between the distributions, it is desirable to use a voltage larger than the verify voltage V_AIVPositive verification voltage V_B2VThe lower limit value of the threshold voltage distribution is adjusted to form a threshold voltage distribution B2 in which the threshold voltage distribution width is narrowed. If the threshold voltage is not reached (or the number of memory cells that do not reach the threshold voltage is greater than or equal to a predetermined value) even if the lower limit adjustment is repeated a predetermined number of times, the writing state of the relevant physical page becomes "write error".

If the upper page data has a value of "0", a high electric field is applied to the tunnel oxide film of the memory cell, electrons are injected to the floating gate electrode, and the threshold voltage V of the memory cell_thRises by a predetermined amount. In particular toSetting a verification potential V_A2VAnd V_C2VRepeating the write operation until a verify voltage V or higher is reached_AIVThe threshold voltage of (2). Accordingly, the memory cells of data "11" (threshold voltage distribution ER1 of the erased state) become data "01" of threshold voltage distribution a2, and the memory cells of data "10" (a 1) become data "00" of threshold voltage distribution C2. In this case, the verify voltage V is used_A2VAnd V_C2VTo adjust the lower values of the threshold voltage distributions a2 and C2. If the threshold voltage is not reached (or the number of memory cells that do not reach the threshold voltage is greater than or equal to a predetermined value) even if the write operation is repeated a predetermined number of times, the writing with respect to the physical page becomes "write error".

In the erase operation, an erase verify potential V is set_evThe erase operation is repeated until the threshold voltage is less than or equal to the verify voltage Vev. Accordingly, the memory cell becomes an erased state (data "11"). If the threshold voltage is not reached (or the number of memory cells that do not reach the threshold voltage is greater than or equal to a predetermined value) even if the erase operation is repeated a predetermined number of times, the erase state of the relevant physical page becomes "erase error".

One example of the data writing method in the typical four-value storage method is described above. The basic operation in the multi-bit storage method of three bits or more is similar, and only the operation of dividing the threshold voltage distribution in eight or more ways according to the upper page data is added for the above operation.

The RAM40 includes a Cache Memory (CM) 40a that serves as a data transfer cache between the host 100 and the NAND memory 20. The RAM40 is used as a management information storage memory and a work area memory. The management table managed by the RAM40 is realized by extracting various types of management tables stored in the NAND memory 20 at the time of startup, and is evacuated and held in the NAND memory 20 periodically or at the time of power-off.

The memory controller 50 has its functions realized by a processor that executes a system program (firmware) stored in the NAND memory 20, various types of hardware circuits, and the like, and performs data transfer control between the host 100 and the NAND memory 20 with respect to various types of commands such as a write request from the host 100, a cache flash request, a read request, and updating and managing various types of management tables stored in the RAM40 and the NAND memory 20.

When issuing a read request or a write request, the host 100 outputs an LBA (logical block addressing) serving as a logical address to the SSD10 through the ATA interface 90. The LBA is a logical address with a sequence number from zero attached to a logical sector (e.g., 512B in size). When a read request or a write request is used, the host 100 outputs a sector size corresponding to the target of the read request or the write request to the SSD10 along with the LBA.

The interface controller 30 includes: a read/write mode interface controller (hereinafter abbreviated as RWIF controller) 31 such as an ATA controller used in a normal operation mode in which read/write is enabled; a read-only mode interface controller (hereinafter abbreviated ROIF controller) 32 such as an ATAPI (ATA packet interface) controller or a controller of a read-only medium standard used in a read-only mode that allows only data reading and data writing; and selection switches 33 and 34 capable of selecting one of the RWIF controller 31 or the ROIF controller 32.

The selection switch 33 selects only one of the RWIF controller 31 or the ROIF controller 32 and connects the selected controller to the ATA interface 90, and the selection switch 34 selects only one of the RWIF controller 31 or the ROIF controller 32 and connects the selected controller to the bus 57. In the selected state of the RWIF controller 31, the selection switch 33 electrically connects the ATA interface 90 and the RWIF controller 31, and the switch 34 electrically connects the bus 57 and the RWIF controller 31. In the selected state of the ROIF controller 32, the selection switch 33 electrically connects the ATA interface 90 and the ROIF controller 32, and the switch 34 electrically connects the bus 57 and the ROIF controller 32.

It is desirable that the RWIF controller 31 be configured to explicitly indicate to the host 100 that the SSD10 is an ATA device. For example, in the device signature described in ATA/ATAPI command set 2 (ACS-2), LBA (7:0) output is 01h, LBA (15:8) is 00h, and LBA (23:16) is output to the host 100 as 00h, so that the host 100 can be notified that SSD10 is an ATA device. It is desirable that ROIF controller 32 be configured to explicitly indicate to host 100 that SSD10 is an ATAPI device. For example, in the device signature described in ACS-2, LBA (7:0) is output of 01h, LBA (15:8) is 14h, and LBA (23:16) is output as EBh to the host 100, so that the host 100 can be notified that SSD10 is an ATAPI device.

ROIF controller 32 is configured to notify host 100 that SSD10 does not support write commands, only reads. For example, when receiving a command GET CONFIGURATION (46h) employed in INCITS multimedia command 6 (MMC-6) from the host 100 through the ATA interface 90, the ROIF controller 32 returns to the host 100 that all Write functions are not supported in features such as Random Write (feature value =0020h), Incremental Streaming Write (feature value =0021h), Write one (feature value =0025h), and the like. Therefore, even if the host 100 side uses Windows (registered trademark) or the like for the OS, the SSD10 can be recognized as a readable device. On the other hand, the ROIF controller 32 may be configured to explicitly indicate to the host 100 that the SSD10 is an ATA device (similar to the RWIF controller 31), and may be configured to return to the host 100 that all write functions are not supported when device identification information is received from the host 100 over the ATA interface 90, such as the command ECh IDENTIFY DEVICE (read device identification) described in ACS-2. The method of informing SSD10 whether it is a read-only device may take various other forms.

The functions of the interface controller 30 and various controllers included therein may be installed as hardware (such as LSI) or may be installed partially or entirely as software such as firmware. When the power supply of the SSD is turned off, the firmware is stored in the NAND memory 20, but is read out to the RAM40 or the memory controller 50 by the IPL55 at the time of power supply startup of the SSD mounted as the firmware.

The RWIF controller 31 has the following functions: receives read requests, write requests, and other requests, as well as data, from the host 100, transmits the received requests and data to the memory controller 50, and transmits the data to the RAM40 under the control of the memory controller 50. The RWIF controller 31 also transmits identification information that the device is a read-write capable device to the host 100 when receiving a transmission request of device identification information from the host 100.

The ROIF controller 32 has the following functions: receives a read request, other requests (except for a write request) and data from the host 100, transfers the received request and data to the memory controller 50, and transfers the data to the RAM40 by control of the memory controller 50. When receiving a transmission request of device identification information from the host 100, the ROIF controller 32 also transmits device identification information, which the device does not support writing, to the host 100. Thus, host 100 recognizes that SSD10 does not support writes, and thus write requests will not be transmitted from host 100 to SSD10. When a write request is transmitted from host 100 to SSD10 after device identification information that the device does not support writing is transmitted to host 100, ROIF controller 32 may return an error to host 100. With respect to commands that do not involve a write operation of the NAND memory 20, the ROIF controller 32 performs a process similar to the RWIF controller 31.

When the power of the SSD10 is turned on, the IPL55 is started and executes the initialization process programs of the NAND memory 20, the RAM40, the memory controller 50, and the interface controller 30. In this case, the IPL55 reads the management information of the NAND memory 20 from the NAND memory 20 or the RAM 40. The IPL55 determines whether a read-only mode switching condition, i.e., whether the SSD10 is in a state to be used in the normal operation mode or in a state to be used in the read-only mode, is satisfied based on the read management information. If the normal mode is determined, the IPL55 sets the selector switches 33, 34 to select the RWIF controller 31 and to place the ROIF controller 32 in the unselected state as a result of the determination. If it is determined based on the read management information that the SSD10 is in a state of use in the read-only mode, the IPL55 sets the selection switches 33, 34 to select the ROIF controller 32 and to put the RWIF controller 31 in an unselected state. The read-only mode switching condition will be described in detail below.

Even when SSD10 is operating in the normal read/write state, it is desirable for storage controller 50 to determine whether a read-only mode switching condition for switching to the read-only mode state is satisfied, and to perform a read-only mode switching condition process, which will be described below, when read-only mode switching condition is satisfied when SSD10 is operating in the normal state. The interface controller 30 thus switches to the ROIF controller 32 according to a read-only mode switching procedure.

The configuration of the host 100 will now be described. Host 100 includes Operating System (OS) 150, SSD control utility 110, and interface driver 120 of SSD10. The interface driver 120 includes: a read/write mode interface driver (hereinafter abbreviated RWIF driver) 121 such as an ATA driver used when the SSD10 is in a normal operation mode to start reading/writing; a read-only mode interface driver (hereinafter abbreviated ROIF driver) 122, such as a read-only driver of an ATAPI driver used when SSD10 is in read-only mode; and selection switches 123, 124 for selecting a driver to be applied to the SSD10 through the RWIF driver 121 and the ROIF driver 122. SSD control tool 110 may select a drive to be applied to SSD10 from one of RWIF drive 121 or ROIF drive 122 or may leave both drives in an unselected state by selecting

switches

123, 124. The software 140 is software other than the SSD control tool 110, and is software using the SSD10.

As illustrated in fig. 5, when the power of the host 100 is turned off, the SSD control tool 100 is stored as the SSD control tool 110A in the NAND memory 20 area of the SSD10, but is loaded from the NAND memory 20 to the main memory 201 at the startup of the host 100 or the startup of a program. As illustrated in fig. 6, if a plurality of external storage devices are connected to the host 100, the SSD control tool 100 may be stored in an area of the external storage device 300 different from the SSD10 as the SSD control tool 100B and loaded from the external storage device 300 to the main memory 202 at the time of the host 100 startup or program startup. In particular, if the external storage device 300 serves as a system driver for storing the OS150 and the SSD10 serves as a data driver for storing user data (such as files), still image data, and moving image data, it is desirable to store the SSD control tool 110 in the external storage device 300 serving as a system driver from the standpoint of clearly separating the roles of the drive 10 and the drive 300 (such as using the external storage device 300 serving as a system driver as a driver for mainly storing the OS and an application and using the SSD10 serving as a data driver as a driver for storing the user data).

As illustrated in fig. 5 and 6, from the standpoint of saving labor for the user in performing the setting of the SSD control tool 110, it is desirable that the computer system 1 is shipped with the SSD control tool 110 stored in the SSD10 or the external storage device 300, and placed on shelves (shelves) and provided to the user. From the standpoint of allowing the user to select whether to install the SSD control tool and from the standpoint of providing the latest SSD control tool to the user, it is desirable that the SSD control tool is stored in the SSD10 or the external storage device 300 by downloading from a WEB page (WEB) or installing from an external storage device (such as a DVD-ROM, a USB memory, or the like).

Fig. 7 illustrates an example of a case where the SSD control tool is downloaded from a web page. In fig. 7, the SSD control tool 110C is stored in the storage medium 400 in the web server, and the SSD control tool 110C is downloaded to the SSD10 or the external storage device 300 via a network (such as the internet, a local area network, and a wireless LAN) through the LAN controller 208 or the like.

Fig. 8 illustrates an example of a case where the SSD control tool is installed from an optical medium such as a DVD-ROM or a CD-ROM. The SSD control tool 110D is stored in an optical medium 500 (such as a DVD-ROM or a CD-ROM), and the optical medium 500 is set in the optical drive 206 so that the SSD control tool 110D is mounted in the SSD10 or the external storage device 300 through the optical drive 206.

Fig. 9 illustrates an example of a case where the SSD control tool is installed from the USB memory. The SSD control tool 110E is stored in the USB memory 600, wherein the SSD control tool 110E is installed in the SSD10 or the external storage device 300 through the USB controller 209 by connecting the USB memory 600 to the USB controller 209. Of course, other external memory (such as an SD card) may be used instead of the USB memory 600. From the standpoint of facilitating user availability, it is desirable that optical medium 500 and USB memory 600 package SSD10 as an accessory when SSD10 is shipped. The optical medium 500 or the USB memory 600 may be sold separately as a software product or may be attached as a supplement to magazines and books.

The selection switch 124 selects only one of the RWIF driver 121 or the ROIF driver 122 and connects the selected driver to the ATA interface 90, and the selection switch 123 selects only one of the RWIF driver 121 or the ROIF driver 122 and connects the selected driver to the software 140. In the selected state of the RWIF driver program 121, the selection switch 124 places the ATA interface 90 and the RWIF driver 121 in a connected state, and the switch 123 places the software 140 and the RWIF driver 121 in a connected state. In the selected state of the ROIF driver 122, the selection switch 124 places the ATA interface 90 and the ROIF driver 122 in a connected state, and the switch 124 places the software 140 and the ROIF driver 122 in a connected state.

Fig. 10 illustrates an appearance configuration of the computer system 1. Fig. 10 illustrates a configuration of a general desktop personal computer. The SSD10 is physically connected to the host board 130 actually through a SATA cable serving as the ATA interface 90, and is electrically connected to a CPU (not illustrated) attached on the host board 130 through a south bridge mounted on the host board 130. SSD10 is connected to power supply circuit 132 by power cable 131. A display 133, a keyboard 134, a mouse 135, and the like are connected to the main board 130. The computer system is not limited to the desktop computer type and is applicable to laptop computers of the notebook personal computer type.

Fig. 11 illustrates a system configuration example of the host 100 mounted with the SSD10. The host 100 includes a CPU200, a north bridge 201, a main memory 202 (such as a DRAM), a display controller 203, a display 133, a south bridge 205, an optical drive 205, a BIOS-ROM207, a LAN controller 208, a USB controller 209, a keyboard 134, a mouse 135, and the like.

The CPU200 is a processor configured to control the operation of the computer system, and executes an Operating System (OS) loaded from the SSD10 to the main memory 200. Further, when the optical drive 206 starts execution of at least one of a read process and a write process with respect to a loaded optical disc, the CPU200 executes such a process.

The CPU200 also executes a system BIOS (basic input output system) stored in the BIOS-ROM 207. The system BIOS is a program for hardware control in a computer system.

The north bridge 201 is a bridge device connected to a local bus of the CPU 200. The north bridge 201 incorporates a memory controller to access and control the main memory 202. The north bridge 201 also has a function of performing communication with the display controller 203 and the like.

The main memory 202 temporarily stores programs and data and serves as a work area of the CPU 200. The main memory 202 is configured by DRAM or the like.

The video controller 203 is a video reproduction controller for controlling the display 133 of the computer system.

The south bridge 205 is a bridge device connected to the local bus of the CPU 200. The south bridge 205 controls the SSD10 or a storage device for storing various types of software and data through the ATA interface 90.

In the computer system, the SSD10 is accessed in units of logical sectors. A write command (write request), a read command (read request), a flash command, and the like are input to the SSD10 through the ATA interface 90.

The south bridge 205 also has a function of access controlling a BIOS-ROM207, an optical drive 206, a LAN controller 208, and a USB controller 209. The keyboard 134 and the mouse 135 are connected to the USB controller 209.

In fig. 11, when the power of the computer system is turned off, the OS150, the SSD control tool 110, the interface driver 120 including the RWIF driver 121 and the ROIF driver 122, and the like, and the software 140 are saved in the SSD10, and are loaded from the SSD10 to the main memory 202 when the power of the host is turned on or such functions are called (call out). The interface driver 120 loaded on the main memory 202 reads to the CPU200 through the north bridge 201, and the CPU200 performs control of the SSD10 through the south bridge 205 based on the information of the read interface driver.

FIG. 12 illustrates a hierarchical structure of various types of computer system elements. SSD control tool 110 and software 140 typically do not communicate directly with SSD10, but rather communicate with SSD10 through OS150 and interface driver 120. If SSD control tool 110 and software 140 are required to transmit commands (such as read requests and write requests) to SSD10, SSD control tool 110 and software 140 transmit access requests in units of files to OS 150. The OS150 refers to a file management table or metadata included in the OS150, specifies a logical address (LBA) of the SSD10 corresponding to the file making the access request, and transmits a command including the corresponding LBA to the interface driver 120. The interface driver 120 converts a command from the OS150 into a unique command to the relevant interface and transfers the command to the SSD.

If a response is returned from the SSD10, the interface driver 120 converts the response unique to the relevant interface into a command of the OS150 and transmits the command to the OS 150. The OS150 specifies which response on which software the response after conversion corresponds to, and returns the response to the specified software.

SSD control utility 110 may directly access interface driver 120 without an intervening OS 150. SSD control tool 110 may select exclusively which of RWIF driver 121 or ROIF driver 122 of the interface driver is active by directly accessing interface driver 120. If the RWIF driver 121 is active, the RWIF driver 121 relays the OS150 and the SSD10, and the ROIF driver 122 does not perform anything. If ROIF driver 122 is active, ROIF driver 122 relays OS150 and SSD10, and RWIF driver 121 does not perform anything. The SSD control tool 110 may alternately select the RWIF driver 121 and the ROIF driver 122 through the OS 150.

At host startup or SSD connection, SSD control utility 110 obtains device identification information of the SSD from SSD10. It is determined whether the SSD10 is a readable-writable device or a device that does not support writing based on the device identification information, and the switch setting of the interface driver 120 is performed based on the determination result. The RWIF driver 121 is enabled if it is determined that the SSD10 is a read-write device, and the ROIF driver 122 is enabled if it is determined that the SSD10 is a device that does not support writing. If the response from SSD10 regarding the write request is erroneous, SSD control facility 110 determines that SSD10 transitions to read-only mode and restarts SSD10 and causes interface driver 120 to transition from RWIF driver 121 to ROIF driver 122.

From the standpoint of preventing user data loss due to data corruption or corruption of SSD10, it is desirable that ROIF drive 122 be configured not to transmit write commands at all with respect to SSD10. However, if a portion of data (such as system information of an operating system) needs to be written into SSD10, ROIF driver 122 may exceptionally allow related data to be written into SSD10, but the amount of related data is expected to be sufficiently small compared to the capacity of NAND memory 20. More desirably, to prevent a user from erroneously transferring WRITE commands and writing data to SSD10, ROIF driver 122 does not transfer normal WRITE commands for SSD10 at all (such as 35h of WRITE DMA EXT and 61h of WRITE FPDMA QUEUE described in ACS-2), and if data is exceptionally required to be written to SSD10, it is desirable that only commands using special commands (such as SCT Command Transport and other commands unique to the vendor described in INCITS ACS-2) allow WRITEs for SSD10. If a write using a special command can be executed exceptionally even when the ROIF driver 122 is applied (at the time of RO mode), the storage controller 50 and the ROIF controller 32 need to be configured to receive the special command from the host 100 and normally execute a data write process even if the SSD10 is in the RO mode.

Fig. 13 illustrates a configuration of management information used in the SSD10. The management information is stored in the nand memory 20 in a nonvolatile manner as described above. The management information stored in the NAND memory 20 is extracted in the RAM40 for use at the startup of the SSD10. The management information on the RAM40 is evacuated periodically or upon power-off and saved in the NAND memory 20. If the RAM40 is a nonvolatile RAM (such as MRAM or FeRAM), the management information may be stored only in the RAM40, in which case the management information is not stored in the NAND memory 20.

As illustrated in fig. 13, the management information includes a free block table 21, a lossy block table 22, an active block table 23, an active page table 24, a read-only (RO) mode flag 25, and statistical information 26.

The free block table (FB table) 21 manages the ID of the physical block (free block: FB) of the NAND memory 20, and the ID for writing can be reallocated when writing to the NAND memory 20 is performed. The FB table also manages the number of times of erasure for each physical block ID.

The damaged block table (BB table) 22 manages IDs of damaged blocks (BB) serving as physical blocks, which cannot be used as storage areas due to excessive errors or the like.

The active block table (AB table) 23 manages Active Blocks (AB) or physical blocks to which applications are assigned. In the AB table 23, the correspondence relationship between the LBA and the ID of the Active Block (AB) is managed. The number of times of erasure is also managed for each physical block ID.

The active page table (AP table) 24 manages the correspondence between LBAs and physical block IDs and physical page IDs to which applications are assigned.

At shipping and at normal times, the RO mode flag 25 is written with 0, and when the SSD operates as the RO mode, the RO mode flag 25 is written with 1.

The statistical information 26 stores various parameters (X01 to X24) regarding the reliability of the SSD10.

The statistical information includes the total number of lossy blocks (statistical information X01), the total number of erasures (statistical information X02), the average value of the number of erasures (statistical information X03), the cumulative value of the number of write errors of the NAND memory (statistical information X04), the cumulative value of the number of erasure errors of the NAND memory (statistical information X05), the total number of read logical sectors (statistical information X06), the total number of write logical sectors (statistical information X07), the total number of uncorrectable ECC error counts (statistical information X08), the total number of n-bit to m-bit ECC correction units (statistical information X09), the number of R errors of SATA communication (statistical information X10), the number of errors of SATA communication (statistical information X11), the number of errors of the RAM40 (statistical information X12), the total number of usages of the SSD10 (statistical information X13), the total time of temperatures higher than the highest value of the recommended operating temperature (statistical information X14), A total time for which the temperature is lower than the minimum value of the recommended operating temperature (statistical information X15), a maximum value of the command response time (statistical information X16), an average value of the command response time (statistical information X17), a maximum value of the response time of the NAND memory (statistical information X18), an average value of the response time of the NAND memory (statistical information X19), a current temperature (statistical information X20), a maximum temperature (statistical information X21), a minimum temperature (statistical information X22), a rate of increase of the statistical information (statistical information X23), a NAND memory garbage collection (NAND GC) failure flag (statistical information X24), and the like.

The total number of lossy blocks (statistical information X01) will be described below. Each time one physical block of the NAND memory 20 in the SSD10 is added as a defective block, the statistical information X01 is increased by 1. It is desirable to reset the statistical information X01 to zero at the time of manufacturing SSD10 (before the test process), with it more desirable that blocks with small inter-distribution voltage margins where errors occur or threshold distributions are distributed during the test process be pre-added to the damaged blocks. The statistical information X01 can be directly calculated from the BB table 22 without being stored in the statistical information 26. The more the statistical information X01 increases, the more the reliability deteriorates.

The total number of times of erasure (statistical information X02) will be described below. The statistical information X02 indicates the cumulative value of the number of times of erasing of all blocks of the NAND memory 20 in the SSD10. The statistical information X02 is increased by 1 each time one physical block of the NAND memory 20 of the SSD10 is erased. It is desirable to reset the statistical information X02 to zero at the time of manufacture of SSD10 (prior to the testing process). The statistical information X02 can be directly calculated from the FB table 21, the BB table 22, and the AB table 23 without being stored in the SSD statistical information 26. The more the statistical information X02 increases, the more the reliability deteriorates.

The average value of the number of times of erasure (statistical information X03) will be described below. The statistical information X03 indicates the per-block average of the number of times of erasing of all blocks of the NAND memory 20 in the SSD10. A part of the blocks (such as the blocks storing the management information) may be excluded from the object of counting the statistical information X03. It is desirable to reset the statistical information X03 to zero at the time of manufacture of SSD10 (prior to the testing process). The statistical information X03 can be directly calculated from the FB table 21, the BB table 22, and the AB table 23 without being stored in the statistical information 26. The more the statistical information X03 increases, the more the reliability deteriorates.

The cumulative value of the number of times of occurrence of write errors of the NAND memory (statistical information X04) will be described below. Each time a write error occurs in one write memory cell in the NAND memory 20 of the SSD10, the statistical information X04 is added by 1 (may be added in block units). It is desirable to reset the statistical information X04 to zero at the time of manufacture of SSD10 (prior to the testing process). The more the statistical information X04 increases, the more the reliability deteriorates.

The cumulative value of the number of times of occurrence of erasure errors of the NAND memory (statistical information X05) will be described below. It is desirable to reset the statistical information X05 to zero at the time of manufacture of SSD10 (prior to the testing process). The statistical information X05 is incremented by 1 whenever an erasure occurs in one block in the NAND memory 20 of the SSD10. Assuming that the entire plurality of blocks is used as an erase unit, the statistical information X05 is incremented by 1 each time an erase error occurs in such an erase unit. The more the statistical information X05 increases, the more the reliability deteriorates.

The total number of read logical sectors (statistical information X06) will now be described. The statistical information X06 is the total number of logical sectors of data transmitted as read data by the interface controller 30 to the host device 100. It is desirable to reset the statistical information X06 to zero at the time of manufacture of SSD10 (prior to the testing process). The more the statistical information X06 increases, the more the reliability deteriorates.

The total number of written logical sectors (statistical information X07) will now be described. The statistical information X07 is the total number of logical sectors of data received by the RWIF controller 31 from the host device 100 as write data. It is desirable to reset the statistical information X07 to zero at the time of manufacture of SSD10 (prior to the testing process). The more the statistical information X07 increases, the more the reliability deteriorates.

The total number of uncorrectable ECC error counts (statistical information X08) will now be described. When the error bit cannot be recovered by the ECC correction performed by the ECC correction circuit 58, the statistical information X08 is increased by 1 for each read cell. When the memory controller 50 reads out data from the NAND memory 20, the memory controller 50 transfers the read data to the ECC correction circuit 58, and performs ECC correction and transfers the corrected data to the host through the interface controller 30 if there is a data error. If the data error is not corrected by the ECC correction circuit 58, the memory controller accumulates the statistical information X08 or adds an uncorrectable amount of data errors to the statistical information X08. The evaluation values of the number of error bits that cannot be error-corrected may be added, or the number of blocks that cannot be error-corrected may be added. It is desirable to reset the statistical information X08 to zero at the time of manufacture of SSD10 (prior to the testing process). The more the statistical information X08 increases, the more the reliability deteriorates.

The total number of n-bit to m-bit ECC correction units (statistical information X09) will be described below. Here, n, m are natural numbers, where 0. ltoreq. n.ltoreq.m.ltoreq.the maximum correctable digit. When the ECC correction circuit 58 performs ECC correction on ECC correction units (e.g., physical pages), "the total number of n-bit to m-bit ECC correction units" is added by 1 for one ECC correction unit if all error bits are normally recovered and the recovered number of error bits is greater than or equal to n and less than or equal to m. In the case where a maximum of 64 bits can be corrected for one correction unit by ECC correction, eight parameters such as "the total number of 1-bit to 8-bit ECC correction units", "the total number of 9-bit to 16-bit ECC correction units", "the total number of 17-bit to 24-bit ECC correction units", "the total number of 25-bit to 32-bit ECC correction units", "the total number of 33-bit to 40-bit ECC correction units", "the total number of 41-bit to 48-bit ECC correction units", "the total number of 49-bit to 56-bit ECC correction units", and "the total number of 57-bit to 64-bit ECC correction units" may be prepared, wherein when ECC correction is normally performed, one of the eight parameters is increased by 1 (or the correction amount of data errors may be increased) for ECC correction of one ECC correction unit. It is desirable to reset the statistical information X09 to zero at the time of manufacture of SSD10 (prior to the testing process). The more the statistical information X09 increases, the more the reliability deteriorates.

The number of R errors occurring in SATA communication (statistical information X10) will be described below. The statistical information X10 is increased by 1 each time an R error (reception error R-ERR) occurs in the SATA standard. If there is some kind of error, such as a CRC error, in a data frame transmitted and received between the host and the SSD, it is counted as one time R error. For the statistical information X10, one of physical Event counters (Phy Event counters) of the SATA standard may be employed. It is desirable to reset the statistical information X10 to zero at the time of manufacture of SSD10 (prior to the testing process). The more the statistical information X10 increases, the more the reliability deteriorates.

The number of error occurrences of SATA communication (statistical information X11) will be described below. The statistical information X11 is increased by 1 each time another exception (not R error) occurs in SATA communication. For example, if the communication standard actually negotiated between SSD10 and host device 100 is a communication standard with a speed lower than the third generation (such as the second generation) (although ATA interface 90, interface controller 30, and storage controller 50 are designed as SATA third generation), it is assumed that there is an error in SATA communication and statistical information X11 is increased by 1. It is desirable to reset the statistical information X11 to zero at the time of manufacture of SSD10 (prior to the testing process). The more the statistical information X11 increases, the more the reliability deteriorates.

The number of error occurrences of the RAM40 (statistical information X12) will be described below. For example, if an ECC circuit or an error detection circuit is mounted on the RAM40, when the memory controller 50 receives a signal notifying that ECC correction cannot be performed or a signal notifying error detection from the RAM40, the statistical information X12 is increased by 1. It is desirable to reset the statistical information X12 to zero at the time of manufacture of SSD10 (prior to the testing process). The more the statistical information X12 increases, the more the reliability deteriorates.

The total number of uses of the SSD10 (statistical information X13) will be described below. When the power of the SSD10 is turned on, the memory controller 50 counts clocks or receives time information from an internal clock circuit to increase the elapsed time. Alternatively, the storage controller 50 may periodically receive time information of the host device 100 from the host device 100, and may increase the difference between the time information. It is desirable to reset the statistical information X13 to zero at the time of manufacture of SSD10 (prior to the testing process). The more the statistical information X13 increases, the more the reliability deteriorates.

The total time (statistical information X14) for which the temperature is above the highest value of the recommended operating temperature will be described below. If the thermometer is installed in the SSD10 (such as on the substrate of the SSD10, in the memory controller 50 and the NAND memory 20), the memory controller 50 periodically receives temperature information from the thermometer. If the received temperature is higher than the recommended operating temperature (e.g., 100 ℃), the storage controller 50 increases the total time of operation at higher than or equal to the recommended operating temperature based on the time information acquired from the clock, the internal clock, or the host device 100. It is desirable to reset the statistical information X14 to zero at the time of manufacture of SSD10 (prior to the testing process). The more the statistical information X14 increases, the more the reliability deteriorates.

The total time (statistical information X15) during which the temperature is below the minimum value of the recommended operating temperature will be described below. If a thermometer is installed in SSD10, memory controller 50 periodically receives temperature information from the thermometer. If the received temperature is below the recommended operating temperature (e.g., -40 ℃), the storage controller 50 increases the total time of operation above or equal to the recommended operating temperature based on the time information acquired from the clock, the internal clock, or the host device 100. It is desirable to reset the statistical information X15 to zero at the time of manufacture of SSD10 (prior to the testing process). The more the statistical information X15 increases, the more the reliability deteriorates.

The maximum value of the command response time (statistical information X16) will be described below. The statistical information X16 is the maximum value of the time (or the number of clocks) required until the response to the host device 100 (or until the completion of the command execution) is received from the host device 100. If the occurrence response time is greater than X16, then X16 is overwritten by such a response time. For each command, statistical information X16 may be saved — it is desirable to reset the statistical information X16 to zero when SSD10 is manufactured (before the testing process) or when SSD10 is shipped. The more the statistical information X16 increases, the more the reliability deteriorates.

For example, the command response time may be:

read response time of SSD 10: the time from when SSD10 receives a read request from host 100 until the transfer of the read data to host 100 is completed.

Write response time of SSD 10: the time from when SSD10 receives a write request from host 100 until write completion notification is returned to host 100. Alternatively, the time from when SSD10 receives a write request from host 100 until the write data reception by host 100 is completed.

The response time may be clocked by counting an internal clock of the memory controller 50.

The average value of the command response time (statistical information X17) will be described below. The statistical information X17 is an average value of the time (or the number of clocks) required until the response to the host device 100 (or until the completion of the command execution) from when the host device 100 receives the command. A constant number of response time lists may be registered in the RAM40, and the statistical information X17 may be obtained by calculating an average of the response time lists. Statistical information X17 may be maintained regarding each command. It is desirable to reset the statistical information X17 to zero when SSD10 is manufactured (before the testing process) or when SSD10 is shipped. The more the statistical information X17 increases, the more the reliability deteriorates.

The maximum value of the response time of the NAND memory (statistical information X18) will be described below. The statistical information X18 is the maximum value of the time (or the number of clocks) required until the memory controller 50 obtains a response (or receives a command execution completion notification) after issuing a command to the NAND memory 20. If the occurrence response time is greater than X18, then X18 is overwritten by such a response time. Statistical information X18 may be maintained regarding each command. It is desirable to reset the statistical information X18 to zero when SSD10 is manufactured (before the testing process) or when SSD10 is shipped. The more the statistical information X18 increases, the more the reliability deteriorates. For example, the response time of a NAND memory can be:

read response time of the NAND memory 20: the time from when the memory controller 50 issues a read request to the NAND memory 20 until the readout of data by the NAND memory 20 is completed.

Write response time of the NAND memory 20: the time from when the memory controller 50 issues a write request to the NAND memory 20 until the writing of data to the NAND memory 20 is completed.

Erase response time of NAND memory 20: the time from when the memory controller 50 issues an erase command to the NAND memory 20 until the erase of the NAND memory 20 is completed.

The average value of the response time of the NAND memory (statistical information X19) will be described. The statistical information X19 is an average value of the time (number of clocks) required until the memory controller 50 obtains a response (or receives a command execution completion notification) after issuing a command to the NAND memory 20. A constant number of response time lists may be held in the RAM40, and the statistical information X19 may be obtained by calculating an average of the response time lists. Statistical information X19 may be maintained regarding each command. It is desirable to reset the statistical information X19 to zero when SSD10 is manufactured (before the testing process) or when SSD10 is shipped. The more the statistical information X19 increases, the more the reliability deteriorates.

The current temperature (statistical information X20) will be described below. If a thermometer is installed in SSD10, memory controller 50 periodically receives temperature information from the thermometer. The storage controller 50 saves the temperature last received from the thermometer in the statistical information X20 as the current temperature. If such a value is very high (e.g., greater than or equal to 85 ℃), then it is determined that the reliability of SSD10 is negatively impacted, and if the temperature is very low (e.g., less than or equal to-10 ℃), then it is determined that the reliability of SSD10 is negatively impacted.

The maximum temperature (statistical information X21) will be described below. The storage controller 50 saves the maximum value of the current temperature X20 in the statistical information X21 as the maximum temperature. If such a value is very high (e.g., greater than or equal to 85 ℃), it is determined that the reliability of SSD10 is negatively impacted. When receiving a current temperature from the thermometer that is higher than X21, the memory controller 50 rewrites the X21 to the current temperature. Compared to the operating temperature of SSD10, it is desirable to set X21 to a sufficiently small temperature (e.g., -40 ℃) when SSD10 is manufactured (prior to the testing process) or when SSD10 is shipped. The more the statistical information X21 increases, the more the reliability deteriorates.

The lowest temperature (statistical information X22) will be described below. The memory controller 50 saves the minimum value of the current temperature X20 in the statistical information X22 as the lowest temperature. If such a value is very small (e.g., greater than or equal to-40 ℃), it is determined that the reliability of SSD10 is negatively impacted. When receiving a current temperature lower than X22 from the thermometer, the memory controller 50 rewrites the X22 to the current temperature. Compared to the operating temperature of SSD10, it is desirable to set X22 to a sufficiently high temperature (e.g., 120 ℃) when SSD10 is manufactured (prior to the testing process) or when SSD10 is shipped. The more the statistical information X22 drops, the more the reliability deteriorates.

The rate of increase of the statistical information (statistical information X23) will be described below. The non-latest information of the statistical information X01 to X19 (for example, a value at the time when the power supply of the SSD10 is turned on or a constant time before, a value at a time before the power supply of the SSD10 is turned off, or the like) is held, respectively. The statistical information X23 is defined as one of the following.

Rate of increase of statistics = (latest statistics) - (old information)

Rate of increase of statistical information = ((latest statistical information) - (old information)/(elapsed time from acquisition of old information))

Rate of increase of statistical information = ((latest statistical information) - (old information)/(number of nand accesses from the time of acquiring old information))

It is desirable to set X23 to zero at the time SSD10 is manufactured (prior to the testing process). The more the statistical information X23 increases, the more the reliability deteriorates.

The NAND memory garbage collection (NAND GC) failure flag (statistical information X24) will be described below. If the statistical information X24 is 1, a sufficient number of free blocks cannot be ensured for operation by NAND garbage collection (NANDGC). It is desirable to set X24 to zero at the time SSD10 is manufactured (prior to the testing process). The more the statistical information X24 increases, the more the reliability deteriorates.

For the statistical information 26, all of the parameters described above may be stored, or some or only one of these parameters may be stored. The expected statistics 26 keep recent information on the RAM40 and are periodically backed up in the NAND memory 20. The statistical information 26 may be stored in only one of the RAM40 or the NAND memory 20, or the relevant statistical information may be transmitted to the host device 100 and stored in the host device 100 or a storage device connected to the host device 100.

The write operation in the SSD10 will now be described using fig. 14. When the SSD10 receives a write request from the host 100 (step S100), the storage controller 50 searches the free block table 21 of the RAM40 (step S101), and acquires the current free block number. If the number of free blocks is less than a predetermined threshold value (step S102), the memory controller 50 performs "NAND memory garbage collection" ("NAND GC"), which will be described later (step S120), and if the number of free blocks is greater than the predetermined threshold value (step S102), newly obtains a free block from the free block table 21 and acquires the physical ID of the obtained free block.

Next, the storage controller 50 performs a write operation to the acquired free block (step S103), adds the LBA, the physical block ID, and the number of times of erasure of the relevant physical block received from the host 100 in the active block table 23, and also adds the LBA, the physical block ID, and the physical page ID to the active page table 24 (step S104), and removes the written physical block from the free block table 21 (step S105). The memory controller 50 reflects the contents of the above writing process in the statistical information 26.

An example of the operation of the NAND GC in the SSD10 (step S120 of fig. 14) will now be described using fig. 15. The page (valid page) recorded in the active page table 24 that contains all pages in the physical block corresponds to the LBA. Not all pages contained in the physical block are valid pages, and a page that does not correspond to a valid page (invalid page) does not correspond to an LBA. A valid page is a page that stores the most recent data, and an invalid page is a page where data of the same LBA is written at another place and thus is no longer referred to. The physical block has availability in terms of data through a certain number of invalid pages, and thus a free block is secured by performing NAND GC that collects data of valid pages and rewriting to a different block.

First, assume that the number of rows i =0 and the cumulative number of free spaces S =0 (step S121). The memory controller 50 reads out the head row (i = 0) of the active block table 23, and acquires the physical block ID of the head row (current physical block ID) (step S122). The active page table 24 is then read out, and all IDs of valid pages corresponding to the current physical block ID in the active page table 24 are acquired (step S123). The memory controller 50 subtracts the size of the acquired valid page IDs from the physical block size to obtain the size v of the invalid page of the current physical block (step S124), wherein if v > 0 (step S125), the current physical block is added to the NAND GC target block list (step S127). Further, the memory controller 50 adds the size v of the invalid page of the current physical block to the accumulated number S of free spaces and updates the accumulated number S of free spaces (step S128).

If v =0 in step S125, or if the accumulated number of free spaces S in step S125 does not reach the physical block size, the memory controller 50 increases the number of columns i to 1 (step S126), reads out the next row (i = 1) of the active block table 23, and acquires the physical block ID (current physical block ID) of the next row (step S122). Then, the processes of step S123 to step S128 are similarly performed. The procedures of steps S122 to S129 are similarly repeated until the accumulated number of free spaces S in step S129 reaches the physical block size.

If the total size S of the invalid pages acquired so far in step S129 is larger than the physical block size, the memory controller 50 reads out the data of all the valid pages on the NAND GC target block list from the NAND memory 20 and writes the data in the RAM40 (step S130), and also performs an erase process on all the physical blocks on the NAND GC target block list (step S131), removes all the physical blocks subjected to the erase process from the active block table 23 and adds the same to the free block table 21 (in this case, increases the number of times of erase), and removes all the read-out pages from the active page table 24 (step S132). Next, the memory controller 50 acquires a new free block from the free block table 21, writes the data written into the RAM40 into the acquired free block (step S133), adds the physical block ID of the free block to which the data is written, the corresponding LBA, and the number of times of erasure of the relevant block to the active block table 23, adds the page ID of the write data and the corresponding LBA to the active page table 24 (step S134), and removes the block ID of the block to which the data is written from the free block table 21 (step S135). The memory controller 50 reflects the processing content of the NAND GC in the statistical information 26. The erasing process of step S131 need not always be performed in the NAND GC of step S120, and the erasing process of step S131 may be performed immediately before the writing operation of step S103 and the number of times of erasing may be increased.

A sufficient number of free blocks with respect to writing can be generally ensured by such a NAND GC. If a sufficient number of free blocks regarding writing cannot be secured even by the NAND GC (step S136), an "RO mode switching process" to be described later is performed (step S137).

The NAND GC is not limited to be executed when a write request is received from the host 100, and may be executed when a command is last received from the host or after a predetermined time elapses from when a command is received from the host 100 to switch to a standby or idle state.

The readout process in the SSD10 will now be described using fig. 16. When the SSD10 receives a read request from the host 100 (step S140), the storage controller 50 searches the active block table 23 (step S141), and investigates whether or not a physical block ID corresponding to an LBA received from the host 100 exists in the active block table 23 (step S142). If the physical block ID exists in the active block table 23, the memory controller 50 acquires the physical page ID contained in the physical block ID of the active page table 24 (step S144), reads out data from the physical page corresponding to the acquired physical page ID (step S145), and transfers the read data to the host 100 through the RAM40 (step S146). The memory controller 50 reflects the contents of the above readout process on the statistical information 26.

If the physical block ID corresponding to the LBA received from the host 100 is not present in the active block table 23 in step S142, the memory controller 50 may transmit data of which all bits are '0' to the host 100 by the data length corresponding to the request from the host 100 without performing the read-out operation from the NAND memory 20 (step S143).

The error process in SSD10 will now be described using fig. 17. The processes regarding the read request and the write request from the host 100 are generally performed in the above manner, but a write error may occur in a write operation (program operation) to the NAND memory 20, an erase error may occur in an erase operation with respect to the NAND memory 20, an uncorrectable ECC (error correction code) error (failure in the error correction process) may occur in a read operation with respect to the NAND memory 20, and the like, in which case an exception process thus becomes necessary.

When one of the above-described errors occurs (step S150), the memory controller 50 adds the physical block in which the error occurred to the lossy block table 22 (step S151), and removes the physical block in which the error occurred from the active block table 23 and the free block table 21 (step S152), so that the physical block in which the error occurred is not accessed thereafter. In this case, the data of the physical block in which the error occurred may be copied to a different physical block. The memory controller 50 reflects the contents of the error process on the statistical information 26. Examples of such error processes have been introduced in the description of the read process, the write process, and the NAND GC process, but the error processes are not limited to these examples, and it should be recognized that the error processes can be applied with respect to all of the read process, the write process, the erase process, and other kinds of operations on the NAND memory 20.

By using the SSD10, the reliability of each block of the NAND memory 20 deteriorates, the number of lossy blocks increases, and the sum of the number of free blocks and the number of active blocks decreases. Further, if the SSD10 is used, the number of free blocks sufficient to perform the write process (which is the lifetime of the SSD 10) cannot be ensured even if the NAND GC is performed. In this case, it is determined that the RO mode switch condition is satisfied and the RO mode switch procedure is performed.

The RO mode switching process in SSD10 will now be described using fig. 18. While SSD10 is operating, storage controller 50 determines whether the RO mode switch condition is satisfied by monitoring statistics 26. RMAX used as the RO mode switching criterion may be RMAX = an upper limit value of a value of the statistical information of the guaranteed reliability.

RMAX may take different values for various statistics X01-X19, X23, X24. As illustrated in fig. 19, RMAX derives the relationship of the original value of the statistical information (original data) to the defect rate of SSD10 at the development stage, and it is desirable to adopt the original data of the statistical information for RMAX when the defect rate exceeds an acceptable value (e.g., 100 ppm), and for the defect rate, other defect rates such as the defect rate of data written to SSD10, the defect rate of NAND memory 20, or the defect rate of memory cells of NAND memory 20 may be adopted instead of the defect rate of SSD10. For example, at the development stage of SSD10, a wear test to verify whether write data is stored correctly for a constant time or longer in succession is performed while repeating write operations with respect to a large number (e.g., 100) of test SSD10 groups at high temperature, and while continuing to monitor statistics and while the original data of the statistics can be adopted for RMAX when the defect rate reaches a constant percentage. For example, if data (e.g., random data) is written in a high temperature state (e.g., 75 ℃) which is an initial condition related to wearing out the entire area of the LBA of the SSD10, but remains unchanged for a certain period of time or longer in the high temperature state (e.g., 85 ℃) and thereafter the temperature of the SSD10 is lowered (e.g., 25 ℃) and a read-out operation is performed on the entire area of the LBA of the SSD10 and the read data is not ECC-correctable (or if there is a constant amount of more data which is not ECC-correctable, or if the read data and the written data do not match or cannot be read out in the initial condition), this is defined as a defect of the SSD10, and a value obtained by dividing the number of defective SSD10 by the number of SSDs 10 of test executions is employed for the defect rate. Raw data for RMAX may be used with statistical information that this defect rate is statistically lower and significantly lower than the acceptable defect rate. A certain degree of margin may be given to RMAX, and RMAX' obtained by the following formula may be employed for RMAX:

RMAX' = RMAX-margin.

RMAX can be obtained at development time through design simulation. For example, a value of the statistical information that a defect rate (such as that of SSD 10) is greater than or equal to a constant value may be obtained by design simulation and may be used for RMAX.

As illustrated in fig. 20, for RMAX, a value of statistical information that the performance (read performance, write performance, etc.) of SSD10 is less than or equal to a predetermined value may be specified by measuring or simulating SSD10, and this value may be adopted for RMAX. For example, since the probability of data errors read from the memory cells of the NAND memory increases as the reliability of the NAND memory deteriorates, the time required for ECC correction at the time of data readout increases, and there may be a great correlation between the reliability of SSD10 and the readout performance of SSD10. For example, for the measurement of sequential readout performance, the following performance measurement is performed.

1. F4h SECURITY ERASE UNIT (Normal Erase) is performed with ACS-2 of SSD10.

2. Data (e.g., random data) is written sequentially onto the entire area of the LBA of SSD10.

3. Readout is performed sequentially on all LBAs, and an average value (unit MiB/s) of the amount of data read is obtained in unit time (readout speed). For the measurement of Performance information (e.g., Performance speed), the measurement may be performed according to a standard described in a non-patent document (SNIA, Solid State Storage Performance test Specification version0.9http:// www.snia.org /).

As illustrated in fig. 20, the statistical information dependency of the performance information is obtained, for example, when the sequential readout speed expectation value is 400MiB/s at the time of shipment of the SSD10 and the lowest performance allowed by the standard of the publishable specification is 300MiB, the statistical information value of which readout speed expectation value is 300MiB is obtained and adopted for RMAX.

Thus, RMAX can be arbitrarily defined by a developer, and RMAX can also be defined by methods other than the above and references.

The memory controller 50 compares RMAX with the value of the statistical information (one of X01 to X19, X23, and X24), and determines that the SSD10 reaches the end of life and the mode is switched to the RO mode when the value of the statistical information > RMAX or the value of the statistical information ≧ RMAX (step S160: yes). For example, in the case of the NAND GC failure flag (statistical information X24), when the value of the statistical information is 1, it is determined that the SSD10 has reached the end of life and the mode is switched to the RO mode. In the case of the total number of damaged blocks (statistical information X01), when the value of the statistical information is greater than a predetermined value, it is determined that SSD10 has reached the end of life and the mode is switched to the RO mode.

The memory controller 50 compares each value of the pieces of statistical information (one of X01 to X19, X23, and X24) with RMAX, and determines to switch to the RO mode when one of the values of the statistical information is greater than or equal to RMAX.

The storage controller 50 determines whether the SSD10 reaches the end of life (whether the SSD10 is in the abnormal state) in the above manner, and performs an RO mode switching process to be described later when it is determined that the SSD10 reaches the end of life (when it is determined that the SSD10 is in the abnormal state) (step S160: yes).

When the current temperature X20 and the maximum temperature X21 are employed for the statistical information (e.g., RMAX =85 ℃ for RMAX), it is determined that SSD10 is in an abnormal state and switches to the RO mode at a temperature outside the guaranteed operating range (e.g., the value of the statistical information > MAX or the value of the statistical information > MAX) (step S160: YES), and thereafter, since SSD10 returns to the normal state when returning to the normal temperature at which the value of the statistical information ≦ RMAX-MAX margin or the value of the statistical information < RMAX-margin MAX, it is desirable to determine to switch from the RO mode to the normal mode (step S160: NO). The MAX margin is a value greater than or equal to zero, but a value greater than zero is desirable to prevent frequent transitions of the RO mode from the normal mode from occurring (e.g., MAX margin =5 ℃).

The statistical information may take various modes other than the statistical information X01 to X19, X23, X24 introduced in the present embodiment, but the present invention is also applicable to these statistical information. There is a positive correlation among the relationships of X01 to X19, X23, X24 and defect rate, but the present invention is also applicable to statistical information of defect rate in which there is a negative correlation (e.g., the lowest temperature experienced by SSD10 after shipment, etc.). In this case, RMAX is replaced with a lower limit value RMIN that can guarantee reliability, where when the statistical information is smaller than RMIN, SSD10 is determined to have reached the end of life and switched to the RO mode.

In particular, when the current temperature X20 and the minimum temperature X22 are employed for the statistical information (such as RMIN = -10 ℃ for RMIN), it is determined that the SSD10 is in the abnormal state and switched to the RO mode at a temperature outside the range of the guaranteed operation (such as the value of the statistical information < RMIN or the value of the statistical information ≦ RMIN) (step S160: yes), and thereafter, since the SSD10 returns to the normal state when returning to the normal temperature at which the value of the statistical information ≧ RMIN + MIN or the value of the statistical information > RMIN + MAX margin, it is desirable to determine switching from the RO mode to the normal mode (step S160: no). The MIN margin is a value greater than or equal to zero, but is desirably a value greater than zero to prevent frequent switching of the RO mode from the normal mode from occurring (e.g., MIN margin =5 ℃).

When the statistical information is greater than a predefined RMAX or shows an outlier that is not possible in normal operation, it is desirable to perform the RO mode switching procedure even if SSD10 has not reached the end of life.

When the RO mode switch condition is satisfied (step S160: YES), the following RO mode switch process is started. First, the memory controller 50 desires to cancel all write processes currently performed on the NAND memory 20 (step S161), return an error with respect to all write requests received from the host 100, and delete all queues of write requests received from the host 100 (step S162). Next, the memory controller 50 writes 1 to the RO mode flag 25 in the management information of the NAND memory 20 (step S163). In this case, all tables except the RO mode flag 25 of the management information of the RAM40 can be reflected on the management information of the NAND memory. Then, the SSD10 returns errors regarding all write requests received from the host 100 until the power is turned off or restarted (steps S164, S165).

The boot process of the SSD10 will now be described using fig. 21, and when the SSD10 boots up, the IPL55 reads out the RO mode flag 25 in the management information of the NAND memory 20 (step S170), and distinguishes the RO mode flag 25 (step S171). If the RO mode flag 25 is 0 (step S171), the IPL55 validates the RWIF controller 31 of the interface controller 30 (step S172) as being in the normal mode, and then reads out the management information of the NAND memory 20 to the RAM40 (step S173).

If the RO mode flag 25 is 1, the IPL55 validates the ROIF controller 32 to be in the RO mode (step S174), and then reads out the management information of the NAND memory 20 on the RAM40 (step S175). In the RO mode, SSD10 acts as a read-only device that does not support writes. After switching to the RO mode, the SSD10 only needs to perform a read operation among read and write operations, and thus the information of the management table can be reconfigured so that the speed of the read-out operation becomes fast.

The operation on the host 100 side will now be described. First, an operation at the time of startup of the host 100 will be described using fig. 22. When the host 100 is started, the host 100 starts the SSD control tool 100 (step S201). If the OS150 is Windows (registered trademark), it is desirable that the SSD control tool 110 record a boot or recording service program so that the SSD control tool 110 is set as a resident program at the time of boot, and the SSD control tool 110 can be automatically booted. The system disk used in the boot host 100 may be the SSD10, an SSD of a pre-installed system prepared separately from the SSD10, or a Hard Disk Drive (HDD), or a DVD-ROM, CD-ROM, or USB memory installed with a boot program.

When the SSD control tool 110 starts up, the SSD control tool 110 transmits a transmission request of the device information to the SSD10 to acquire the device information of the SSD10. As described above, if the RWIF controller 31 is valid in the SSD10, the SSD control tool 110 recognizes that the SSD10 is an ATA device by LBA (7:0) and LBA (15:8) in the device signature described in ACS-2, and when a transfer request of device identification information (such as ECh IDENTIFY DEVICE described in ACS-2 or the like) is received from the host 100, the RWIF controller 31 transfers the identification information that the SSD10 is a readable-writable device to the host 100. If ROIF controller 32 is valid in SSD10, SSD control tool 110 recognizes that SSD10 is an ATAPI device by LBA (7:0) and LBA (15:8) in the device signature described in ACS-2, and when a transmission request of device identification information (such as 46h get configuration described in MMC-6 or the like) is received from host 100, ROIF controller 32 transmits the device identification information that SSD10 does not support writing. Accordingly, the SSD control tool 110 acquires the device identification information from the SSD10 in this manner (step S202). The method of notifying SSD10 whether it is a read-only device may take various forms other than the above.

If the information returned from the SSD10 is that the writing device is not supported (step S203), the SSD control tool 110 switches and sets the selection switches 123, 124 to invalidate the RWIF driver 121 (step S206) and to validate the ROIF driver 122 (step S207) to operate the SSD10 in the RO mode. If the information acquired by the SSD10 is not a device that does not support writing (step S203), the SSD control tool 110 switches and sets the selection switches 123, 124 to invalidate the ROIF driver 122 (step S204) and to validate the RWIF driver 121 (step S205) to operate the SSD10 in the normal mode.

The operation of the SSD control tool 110 when the host 100 operates will now be illustrated using fig. 23. In order to quickly detect the switching of the SSD10 to the RO mode, if the SSD10 is in the normal mode, it is desirable that the SSD control tool 110 continuously monitor the response from the SSD10 in relation to the write request from the host 100 (step S210). If SSD10 is in RO mode, the write request is not transmitted to SSD10, so SSD control tool 110 may not detect the response of SSD10.

If an error (which may be one or more errors) is returned with respect to the write request transmitted to the SSD10 in the normal mode, the SSD control tool 110 determines to start the RO mode switching process for the SSD10 as illustrated in fig. 18 and returns a state of errors with respect to all write requests, and invalidates the RWIF driver 121 (step S211). From the standpoint of quickly recognizing SSD10 as a write-only device, SSD control tool 110 is expected to restart SSD10 by sending a reset Command to SSD10 or the like using the comp reset of the SATA standard, a Command unique to the SCT Command Transport vendor described in ACS-2, and other commands unique to the vendor (step S212). This restart process of restarting the computer system 1 by the user is performed by the off/on of the power supply of the SSD10, and the SSD10 switches to the RO mode by performing the process illustrated in fig. 21. The SSD control tool 110 activates the ROIF driver 122 (step S213).

Accordingly, the host 100 can reliably perform the readout process with respect to the SSD10 without erroneously identifying the SSD10 as an invalid external storage device, while starting the SSD10 immediately after starting the RO mode switch process and during the RO mode.

Fig. 24 illustrates an example of a display of a drive when Windows (registered trademark) is used for the OS in the host 100, and assumes that an SSD is connected for the drive D. If the SSD is in the normal readable-writable state, the type of drive D is shown as "local disk", as illustrated in FIG. 24 (a). However, after the SSD control tool 110 recognizes that the drive D is a write-unsupported device through the processes of fig. 22 and 23, the type of the drive D is shown as "CD-ROM", "DVD-ROM", or "ROM drive", as illustrated in fig. 24 (b).

In the above description, as for the statistical information used in the RO mode switching condition in the SSD10 of fig. 18, the statistical information X01 to X19, X23, X24 are employed, but other statistical information may be used to determine whether the RO mode switching condition is satisfied.

For example, if a management unit (referred to as a cluster) described in U.S. patent application publication No. 20090222617 is introduced in the SSD10, several lossy clusters may be employed for the RO mode switching condition. The cluster size is a natural multiple of twice or more the sector size, and the cluster address is configured by a higher bit sequence of predetermined bits from the LBA. In the SSD10, a lossy cluster table for managing a cluster address (cluster ID) of a lossy cluster is stored as management information. When an ECC correction error occurs in the ECC process by the ECC correction circuit 58 while performing readout from the NAND memory 20, the memory controller 50 may record a cluster in which the ECC correction error occurs in the lossy cluster table. The number of lossy clusters can be obtained based on the recorded contents of the lossy cluster table. Therefore, if the SSD10 operates in the normal mode, the storage controller 50 acquires the current lossy cluster number based on the number of entries of the lossy cluster table stored in the management information in the RAM40, compares the acquired lossy cluster number with a threshold, and determines that the RO mode switch condition is satisfied when the lossy cluster number is greater than or equal to the threshold.

In the flowcharts of fig. 18 and 21, it is determined whether or not the read-only mode switch condition is satisfied by interpolating the RO mode flag 25 in the SSD10 at the time of SSD startup, but it may be determined whether or not to switch to the read-only mode by directly determining whether or not at least one of various types of management information used in the RO mode switch condition satisfies the RO mode switch condition at the time of startup, instead of using the RO mode flag 25.

Process variants of SSD control tool 110 installed on host 100 will now be described. For example, the operational steps illustrated in FIG. 25 may be employed in place of the operational steps generally illustrated in FIG. 23. In fig. 25, when the SSD10 operates in the normal mode, the SSD10 control tool 110 issues a command to periodically acquire the statistical information of the SSD10 to the SSD10 (step S220). This command may be SMART READ DATA (smart read data) (B0h (D0h)) or S.M.A.R.T (self-monitoring analysis and reporting technique) commands (which are self-diagnostic functions of the memory),

An SCT Command Transport or vendor unique Command described in ACS-2. In the SSD10 that receives the information of the s.m.a.r.t., the storage controller 50 acquires one, a part, or all of the statistical information X01 to X19, X23, and X24, and returns the acquired statistical information to the host 100. The SSD control tool 110 acquires the statistical information by receiving the statistical information returned from the SSD10 (step S221).

Fig. 26 illustrates a management table regarding statistical information X01 to X19, X23, X24. For example,

as illustrated in fig. 26, when B0h/D0h SMART READ DATA is used, the attribute ID of each of the constituent elements (X01 to X19, X23, X24, and the like) about the statistical information is assigned, but of course the attribute ID may be assigned only to some of the constituent elements. As for the constituent elements of the statistical information 26, SMAB is adopted as the optimum value after the normalization, and SMAL such as defined as SMAL = SMAB × AMALR (0 ≦ AMALR < 1) (SMAL is an integer and is converted into an integer by rounding off the decimal after the decimal point) is adopted after the normalization in order to secure the reliability of the lower limit value. The attribute values are defined as:

attribute value = SMAL + SMAB x (1-AMALR) x (RMAX-original data)/RMAX

Attribute threshold =30 (fixed value)

Raw data of (raw data) = statistical information

Causing the storage controller 50 to calculate an attribute value ("value" in fig. 26) of the s.m.a.r.t information and transmit this attribute value to the SSD control tool 110. The attribute threshold is the "threshold" in fig. 26, and the raw data is the "raw data" in fig. 26.

The optimum value SMAB after normalization need only be an arbitrary natural number and SMAB =100 may be employed. AMALR need only be any number satisfying 0 ≦ AMALR <1, and AMALR =0.3 may be employed. Further, AMALR and SMAB may take different values for each of X01-X19, X23, X24. If SMAB =100 and AMALR =0.3, the optimum value of the attribute value regarding the statistical information to be employed is 100 (for example, the value immediately after shipment is 100), and gradually decreases as the reliability deteriorates, wherein the attribute value 30 reaches a value less than or equal to 30 when the SSD can no longer guarantee the reliability (when the original data of the statistical information is greater than or equal to RMAX). B0h/DAh SMART RETURN STATUS (which is a command described in ACS-is used as a means for detecting whether the attribute value exceeds the threshold value, and whether the attribute value exceeds the threshold value can be determined from the output of the relevant command.

The "worst" of fig. 26 may be employed as a specification for SSD control tool 110 to diagnose the life of SSD10. The "worst" is calculated by the memory controller 50 as the worst value of the attribute values. In the case of X01 to X19, X23, X24, the worst is the minimum value of the attribute values after the SSD10 is shipped (or after manufacturing). Alternatively, as for the worst value, a minimum value of the attribute values within a constant time range in the past may be employed as the worst value, or a minimum value from the past until now may be employed as the worst value back to the past, in which communication or a process is performed for a certain number of times (a certain amount of data).

The "raw data" (raw values) in fig. 26 may be employed as a specification for SSD control tool 110 to diagnose the life of SSD10. Raw data of the statistical information (e.g., X01-X19, X23, X24) is transferred from the SSD10 to the SSD control tool 110 as raw data. In this case, the SSD control means 110 may obtain RMAX from stored RMAX or the SSD control means 110 by reading from the SSD10 or from another storage device, respectively, compare RMAX with original data, and determine that the SSD10 reaches end of life when the original data > RMAX or the original data > RMAX. For example, in the case of the NAND GC failure flag, it is determined that SSD10 reaches the end of life when the original data is 1. In the case of the total number of damaged blocks, it is determined that SSD10 reaches the end of life when the raw data is greater than a predetermined value. With respect to the original data, the original data of the statistical information does not necessarily need to be output, and the memory controller 50 may transmit a value obtained by performing four arithmetic operations on the original data of the statistical information to the SSD control tool 110 as the original data, and compare RMAX with the value obtained by the four arithmetic operations in order to make a determination. The memory controller 50 may transmit data obtained by encrypting the original data of the statistical information to the SSD control tool 100 as the original data, and the memory controller 50 may decode the data and compare the decoded data with the RMAX in order to make a determination.

The SSD control tool 110 compares the acquired statistical information with predetermined thresholds (e.g., RMAX and RMIN) (step S222), and similar to fig. 23, invalidates the RWIF driver 121 when it is determined that SSD10 reaches the end of life (or just before the end of life or in an abnormal state) (step S222: yes) (e.g., when the statistical information of SSD10 is greater than RMAX (or X24=1, or when the statistical information is less than RMIN)) (step S223). The SSD control tool 110 may restart the SSD10 (step S224). After restarting the SSD110, the SSB control tool 110 activates the ROIF driver 122 (step S225).

When SSD10 is in the normal mode, the operation in host 100 may be the operation steps in fig. 27. In this operation step, the SSD control tool 110 periodically issues SMART READ DATA or s.m.a.r.t. command or vendor unique command to the SSD10 (step S240). In the SSD10 that receives the information of the s.m.a.r.t, the storage controller 50 acquires the current number of lossy clusters based on the number of entries of the lossy cluster table in the management information stored in the RAM40, and returns the acquired number of lossy clusters to the host 100. The SSD control tool 110 acquires the lossy cluster number by receiving the lossy cluster number returned from the SSD10 (step S241).

The SSD control tool 110 compares the acquired lossy cluster number with a predetermined threshold value (step S242), and when the lossy cluster number of the SSD10 is greater than or equal to the threshold value, the RWIF driver 121 is invalidated (step S243), the SSD10 is restarted (step S244), and the ROIF driver 122 is validated (step S245), similarly to fig. 13.

The backup function may be loaded in SSD control tool 110. In a state where the SSD10 is switched to the read-only mode, it is assumed that the data holding property of the SSD10 is deteriorated, and therefore the user data of the SSD needs to be evacuated to another auxiliary storage device as fast as possible. Fig. 28 is a view illustrating a configuration of the host 100 when the SSD control tool 110 is loaded with the backup function. An auxiliary storage device (other SSD, hard disk drive, portable disk storage medium, etc.) 400 is connected to the host 100, and the OS of the host 100 and the auxiliary storage device 400 communicate through an auxiliary storage device driver 401.

Fig. 29 illustrates an operation example of the SSD control tool 110 when backup is employed. In fig. 29, step S208 is added to the operation step of the SSD control tool 110 illustrated in fig. 22. In the backup in step S208, the SSD control tool 110 displays a message (such as "SSD is being switched to read only mode. The backup is started when the "ok" button is clicked with the mouse 135, and the information displayed disappears and the backup is not performed when the "cancel" button is clicked with the mouse 135. A command to read out data of all LBAs of SSD10 is sent to ROIF driver 122. The SSD control tool 110 sends a command to the secondary storage device driver 401 to write the data read out from the SSD10 to the same LBA (LBA of the secondary storage device 400) as that of the data read out from the SSD10 (LBA of the SSD). For example, the data of LBA =0h of the SSD10 is copied to LBA =0h of the secondary storage device 400. The data of LBA =234c5h of SSD10 is copied to LBA =234c5h of secondary storage device 400.

In the backup process, SSD control tool 110 may send a command to the OS of host 100 to copy all files of SSD10 to secondary storage device 400. In this case, the OS refers to the file management table or metadata contained in the OS, acquires all the LBAs of all the files of the SSD10, reads out all the data of the acquired LBAs, writes the read data in the secondary storage device 400, and updates the file management table or metadata so that the written LBAs and the file indexes correspond. Partition information including the SSD10 and Master Boot Record (MBR) information of the file system management area may be accessed to acquire information of the used area and the file, a ROM image on data of the SSD10 is generated based on the acquired information, and the generated ROM image may be saved in another storage device.

In the present embodiment, the physical address of the NAND memory 20 is directly associated with the LBA in the management information for the sake of simplicity, but the LBA may be managed using a management unit twice or more natural number times the sector size as in U.S. patent application publication 20090222617, and the correspondence of the management unit to the physical address of the NAND memory may be described in the management information (instead of the LBA). The management information describing the correspondence relationship of the physical address and the LBA of the NAND memory 20 may take various forms, and the form taken by the table (logical-physical conversion table) describing the correspondence relationship of the physical address and the LBA does not affect the essence of the present invention. And with respect to the nonvolatile memory other than the nand type flash memory, the management information describing the correspondence relationship of the physical address and the nonvolatile memory with the LBA may take various forms, but the form taken by the table (logical-physical conversion table) describing the correspondence relationship of the physical address with the LBA does not affect the essence of the present invention.

Information unrelated to the reliability information used in the management information section does not affect the essence of the present invention. The requirements for reliability information may also be applied in embodiments following the second embodiment.

Therefore, according to the first embodiment, it is determined in the SSD10 whether a read-only mode switch condition is satisfied, wherein if the read-only mode switch condition is satisfied, the interface controller shifts to a mode dedicated for reading, it is determined in the host 100 whether the SSD10 is recognized as a read-only memory for read-only operation of read-write operation based on information acquired from the SSD10, and if it is determined to be recognized as a read-only memory, the interface driver for SSD control shifts to a mode dedicated for reading, and thus the host can generally recognize the SSD switched to the read-only mode as a device enabling read-only operation.

(second embodiment)

In the first embodiment, both the function mounted to the SSD10 and the function mounted to the host 100 are used. In the second embodiment, a case where only the function mounted to SSD10 is applied is explained, which is most effective if the function is mounted on both SSD10 and host 100, but sufficient effect can be exhibited even by mounting the function only on SSD10.

Fig. 30 illustrates a configuration of the second embodiment of the computer system. In the second embodiment, the SSD10 is mounted with the interface controller 30 described in the first embodiment, and the SSD control tool 110 for causing the SSD10 to convert the interface driver 120 is not mounted on the host 100 side. In fig. 30, the same reference numerals are assigned to constituent elements having the same functions as those illustrated in fig. 1, and redundant description will be omitted. In a second embodiment, for example, the functions of the IPL55 are installed on the controller 50. And in the SSD10 of the second embodiment, all the functions of the SSD10 described above in the first embodiment may be installed.

In the second embodiment, the storage controller 50 uses the above-described management information to determine whether the above-described read-only mode switch condition that causes the SSD10 to switch from the normal readable/writable state to the read-only mode state is satisfied at the SSD startup or during the SSD operation, wherein if the read-only mode switch condition is satisfied, the interface controller 30 switches from the RWIF controller 31 to the ROIF controller 32. When a request is made from the host 100, the RWIF controller 31 transmits device identification information indicating that the relevant drive is a readable/writable drive to the host. When a request is made from the host 100, the ROIF controller 32 transmits device identification information indicating that the relevant drive is a read-only drive to the host.

It is desirable that the RWIF controller 31 be configured to explicitly indicate to the host 100 that the SSD10 is an ATA device. For example, in the device signature described in ATA/ATAPI command set 2 (ACS-2), LBA (7:0) output is 01h, LBA (15:8) output is 00h, and LBA (23:16) is output to the host 100 as 00h, so that the host 100 can be notified that SSD10 is an ATA device. It is desirable that ROIF controller 32 be configured to explicitly indicate to host 100 that SSD10 is an ATAPI device. For example, in the device signature described in ACS-2, LBA (7:0) output is 01h, LBA (15:8) output is 14h, and LBA (23:16) is output as EBh to the host 100, so that the host 100 can be notified that SSD10 is an ATAPI device.

ROIF controller 32 is configured to notify host 100 that SSD10 does not support write commands and only reads. For example, when receiving the command GET CONFIGURATION (46h) employed in the INCITS multimedia command 6 (MMC-6) from the host 100 through the ATA interface 90, the ROIF controller 32 returns to the host 100 that all Write functions are not supported in the features such as Random Write (feature value =0020h), Incremental Streaming Write (feature value =0021h), Write one (Write Once) (feature value =0025h), and the like. On the other hand, the ROIF controller 32 may be configured similarly to the RWIF controller 31 to explicitly indicate to the host 100 that the SSD10 is an ATA device, and may be configured to return to the host 100 that all write-not-support functions are not supported when device identification information (such as the ECh IDENTIFY DEVICE command described in ACS-2) is received from the host 100 over the ATA interface 90. The method of informing SSD10 whether it is a read-only device may take various other forms.

For example, referring to fig. 18 used in the first embodiment, the storage controller 50 determines whether the RO mode switch condition is satisfied when the SSD10 operates (fig. 18: step S160). Specific examples when the RO mode switch condition is satisfied include when, for example, the following conditions are satisfied: such as when it is determined that the SSD has reached the end of life (or just before reaching the end of life, or is in an abnormal state), such as when at least one of statistics X01-X19, X23, X24 is greater than RMAX, when X24=1, or when the statistics are less than RMIN.

When the RO mode switch condition is satisfied, the storage controller 50 desirably cancels all write processes currently performed on the NAND memory 20 (step S161), returns an error with respect to all write requests received from the host 100, and deletes all queues of write requests received from the host 100 (step S162). Next, the memory controller 50 writes 1 to the RO mode flag 25 in the management information of the NAND memory 20 (step S163). Thereafter, the SSD10 returns errors with respect to all write requests received from the host 100 until the power is turned off or reset (step S164, step S165).

At the time of startup of the SSD10, operations similar to those used in the first embodiment are performed. In other words, when the SSD10 is started, the IPL55 in the memory controller 50 reads out the RO mode flag 25 in the management information of the NAND memory 20 (step S170), and reads the RO mode flag 25 (step S171). If the RO mode flag 25 is 0 (step S171), the IPL55 validates the RWIF controller 31 of the interface controller 30 (step S172) as being in the normal mode, and then reads out the management information of the NAND memory 20 to the RAM40 (step S173).

If the RO mode flag 25 is 1, the IPL55 validates the ROIF controller 32 to be in the RO mode (step S174), and then reads out the management information of the NAND memory 20 on the RAM40 (step S175). In the RO mode, SSD10 acts as a read-only device that does not support writes.

When the host 100 or the connected device is started, the host 100 requests identification information for the connected device. In the normal mode, SSD10 causes RWIF controller 31 to return device identification information to the host indicating that SSD10 is readable and writable by host 100, and thus host 100 recognizes SSD10 as a readable and writable device. In the RO mode, SSD10 causes ROIF controller 32 to transmit device identification information back to host 100 indicating that SSD10 is a read-only drive that does not support writing, and thus host 100 recognizes SSD10 as a write-not-supported device. Thus, while in RO mode, write requests are not sent from host 100 to SSD10. Therefore, in the RO mode, the SSD10 acts as a read-only device that does not support writing, so that an access other than writing can be made from the host 100. Even if Windows (registered trademark) is installed on the host 100 for the OS, the SSD10 is recognized as a readable device.

When SSD10 notifies host 100 that SSD10 is identification information of an external storage device that does not support writing when the reliability of SSD10 deteriorates, it appears to host 100 as if SSD10 switched from a readable-writable external storage device to an external storage device that does not support writing. Accordingly, the SSD10 with degraded reliability serves as a read-only device of the host 100, so that the host 100 can process the SSD10 into a general read-only external storage device, such as a CD-ROM or a DVD-ROM.

(third embodiment)

In the third embodiment, a case is shown where the application is installed only to the function of the host 100, which is most effective if the function is installed on both the SSD10 and the host 100, but can exhibit sufficient effects even by installing the function only on the host 100.

Fig. 31 illustrates a configuration of the third embodiment of the computer system. In the third embodiment, the interface driver 120 and the SSD control tool 110 described in the first embodiment are mounted on the host 100, and the interface controller 30 (in which the transferable RWIF controller 31 and the ROIF controller 32) is not mounted on the SSD10 side. In fig. 31, the same reference numerals are assigned to constituent elements having the same functions as those illustrated in fig. 1, and redundant description will be omitted. The interface controller 38, to which only the RWIF controller 31 is installed, is installed in place of the interface controller 30. And in the host 100 of the third embodiment, all the functions of the host 100 described in the above first embodiment may be installed. In the third embodiment, SSD10 itself does not necessarily need to be able to switch to RO mode.

In the third embodiment, the SSD control tool 110 performs operations similar to those described in fig. 25 and 27 of the first embodiment. When the host 100 is started up, the host 100 starts up the SSD control tool 110. It is desirable that the SSD control tool is automatically started up along with the startup of the host 100 by recording a startup menu, a service, or a registry in Windows (registered trademark). The SSD control tool may be arbitrarily activated by the user with the keyboard 134, mouse 135, or the like. When the SSD control tool 110 is started, the SSD control tool 110 transmits a transmission request of the statistical information to the SSD10 to acquire at least one of the statistical information X01 to X19, X23, X24 of the SSD10 in the case of fig. 25 (fig. 25: step S220). The transfer request may be SMART READ DATA or an s.m.a.r.t Command (which is a self-diagnostic function of memory), an SCT Command Transport described in ACS-2, or a Command unique to the vendor, as described above.

The SSD control tool 110 acquires the statistical information in this manner (step S221). The SSD control tool 110 compares the statistical information returned from the SSD with a threshold value (e.g., RMAX or RMIN described in the first embodiment) (step S222). When the B0h/D0 hsnart READ DATA described in ACS-2 is used to acquire the statistical information, the SSD control tool 110 acquires at least one of the constituent elements (X01 to X19, X23, X24) of the statistical information 26 in the form of the attribute values, the threshold values, the worst values, and the original DATA (original values) illustrated in fig. 26. The method of calculating the attribute values, the threshold values, the worst values, and the raw data (raw values) by the storage controller 50 is the same as the first embodiment, and the information calculated in this way is transmitted from the SSD10 to the control tool 110 as information on the reading of B0h/D0h SMART READ DATA.

For example, when the attribute value and the threshold value of SMART are used as comparison data for diagnosing the lifetime (or abnormal state) of SSD10, SSD control tool 110 performs the comparison of the attribute value with the threshold value, and when the attribute value < the threshold value (or the attribute value ≦ the threshold value), SSD control tool determines that SSD10 reaches the end of lifetime (or abnormal event). If SMAB =100 and AMALR =0.3 in the first embodiment, the optimum value of the attribute value regarding the statistical information to be employed is 100 (for example, the value immediately after shipment is 100) and gradually decreases as the reliability deteriorates, wherein when the SSD can no longer guarantee the reliability (when the original data of the statistical information is greater than or equal to RMAX), the attribute value 30 reaches a value less than or equal to 30, and the SSD control tool 110 determines that the SSD10 is identified as the read-only memory (step S222: yes). B0h/DAh SMART RETURN STATUS (which is a command described in ACS-2) as a means for detecting whether the attribute value exceeds the threshold value, and whether the attribute value exceeds the threshold value can be determined by the output of the relevant command.

For example, when the worst value and the threshold of SMART are used as comparison data for diagnosing the life (or abnormal state) of SSD10, SSD control tool 110 performs a comparison of the worst value with the threshold, and SSD control tool determines that SSD10 reaches the end of life (or abnormal event) when the worst value < the threshold (or the worst value ≦ the threshold). As in the first embodiment, if SMAB =100 and AMALR =0.3, the optimum value of the worst value regarding the statistical information to be employed is 100 (for example, the value immediately after shipment is 100), and gradually decreases as the reliability deteriorates, wherein the worst value 30 reaches a value less than or equal to 30 when the SSD can no longer guarantee the reliability (when the original data of the statistical information is greater than or equal to RMAX), and the SSD control tool 110 determines that the SSD10 is identified as the read-only memory (step S222: yes).

For example, when raw data (original value) of SMART, which increases with deterioration of the reliability of the SSD10, is taken as comparison data for diagnosing the lifetime (abnormal state) of the SSD10, the SSD control tool 110 performs comparison of the original value with RMAX, and the SSD control tool determines that the SSD10 reaches the end of lifetime (abnormal state) when the original value ≧ RMAX (or original value > RMAX). RMAX is a parameter stored on the main memory 202 (such as the SSD control tool 110). It is desirable that RMAX be stored in SSD10 as nonvolatile information when the power of computer system 1 is turned off, and that RMAX be loaded to main memory 202 when the SSD control tool is loaded to main memory 202 as illustrated in fig. 5 and 6 when the power is turned on. As in the first embodiment, it is desirable that RMAX be determined at the time of development of SSD10, and stored in an area that becomes a mounting source of the SSD control tool (such as an area of storage medium 400 of the web server, a storage area of optical storage medium 500, or an area of USB memory 600).

The original value gradually increases as the reliability of the SSD10 deteriorates, wherein the original value reaches a value greater than or equal to RMAX when the SSD can no longer guarantee the reliability, and the SSD control tool 110 determines that the SSD10 is identified as the read only memory (step S222: yes). RMAX may take different values with respect to each constituent element (such as statistical information X01 to X19, X23, X24, and the like).

For example, when the original data (original value) of SMART, which increases as the reliability of the SSD10 deteriorates, is used as comparison data for diagnosing the lifetime (abnormal state) of the SSD10, the SSD control tool 110 performs comparison of the original value with RMIN, and determines that the SSD10 reaches the end of lifetime (abnormal state) when the original value is ≦ RMIN (or the original value < RMIN). RMIN is a parameter held on main memory 202 (such as SSD control tool 110). When the power of the computer system 1 is turned off, RMIN is desirably stored in the SSD10 as nonvolatile information, and when the SSD control tool is loaded to the main memory 202 as illustrated in fig. 5 and 6 when the power is turned on, RMIN is loaded to the main memory 202. As in the first embodiment, it is desirable that RMIN is determined at the time of development of the SSD10, and that RMIN is stored in an area that becomes a mounting source of the SSD control tool (such as an area of the storage medium 400 of the web server, a storage area of the optical storage medium 500, or an area of the USB memory 600).

The original value gradually decreases as the reliability of the SSD10 deteriorates, wherein the original value reaches a value less than or equal to RMIN when the SSD can no longer guarantee the reliability, and the SSD control tool 110 determines that the SSD10 is recognized as the read-only memory (step S222: yes). The RMIN may take different values with respect to each constituent element (such as statistical information X01-X19, X23, X24, etc.).

For example, when the statistical information X24 is received as raw data (raw value) of SMART and the statistical information X24 is used as comparison data for diagnosing the life (or abnormal state) of the SSD10, the SSD control tool 110 performs determination of whether the raw value is 1 or not, and determines that the SSD10 reaches the end of its life (or abnormal state) when the raw value = 1. If the reliability of the SSD10 deteriorates and the storage controller 50 cannot secure a sufficient number of free blocks even by the NAND GC, the original value is set to 1 by the storage controller 50, and the SSD control tool 110 determines to recognize the SSD10 as the read-only memory (step S222: yes).

If it is determined as a result of the comparison at step S222 that the RO mode switch condition is satisfied in the SSD10, that is, if it is determined that the SSD10 is recognized as the read only memory (step S222: yes), the ROIF driver 122 is activated (step S225). SSD control tool 110 may cause operating system 150 to recognize SSD10 as a read-only memory by operating system 150's system parameters in fig. 12. It is desirable for the SSD control tool 110 to transmit a reset command or the like and restart the SSD10 before step S225 (step S224).

It is desirable for the SSD control tool 110 to periodically execute the procedures of steps S220, S221 and S222 (in the case of fig. 25) as illustrated in fig. 25, fig. 27, and the like, that is, to transmit a request of statistical information to the SSD10 and to determine to recognize the SSD10 as the read-only memory even when the host 100 operates. For example, SMART READ DATA may be issued at each constant time and it may be determined whether to identify SSD10 as read-only memory. The request and determination may be performed at the time of the host 100 startup, or may be performed after the host 100 startup to reduce the number of interrupt processes of the SSD control tool 110. If it is determined that SSD10 is identified as read-only memory, ROIF driver 122 of interface driver 120 is enabled. After identifying SSD10 as a read-only memory to reduce the number of interrupt processes of SSD control tool 110, it is desirable not to perform the transmission request of the statistical information and the RO mode switch determination.

When it is recognized that SSD10 is activated or connected, SSD control tool 110 may perform the request and determination. For example, if the interface 90 is the SATA interface, it is determined that the SSD10 is activated or connected when the status register of the SSD10 regarding the host 100 changes from 7Fh to 50h, and then the request and determination may be performed.

The determination identified as read-only memory may be performed by the storage controller 50, and the SSD control tool 110 may only receive the determination result through SMART READ DATA, SCT Command Transport or a Command unique to the vendor. For example, if it is determined by the storage controller 50 to be identified as read-only memory with a criterion similar to the first embodiment, the SSD control tool 110 receives the value 0 as the attribute value from the SSD10 through SMARTREAD DATA and receives the value 100 at other times (normal times), wherein the value 70 is received as the threshold value for both cases of being identified as read-only memory and not being identified as read-only memory, and determines not to be identified as read-only memory if the attribute value < the threshold value (step S222: no). It should be appreciated that the worst value and the original value may be used to receive the determination.

When the current temperature X20, the maximum temperature X21, and the minimum temperature X22 are employed for the statistical information, the temperature anomaly may be temporary, and therefore when the attribute value ≧ the threshold (or the attribute value > the threshold), the SSD control tool 110 invalidates the ROIF driver and validates the RWIF driver after determining to return to the normal state in step S255.

From the standpoint of preventing loss of user data caused by data corruption or corruption of SSD10, it is desirable that ROIF drive 122 be configured not to transmit write commands at all with respect to SSD10. However, if a portion of data needs to be written (such as system information of an operating system in SSD 10), ROIF driver 122 may exceptionally allow related data to be written to SSD10, but it is desirable that the data amount of the related data be sufficiently small relative to the capacity of NAND memory 20. More desirably, to prevent a user from erroneously transferring write commands and writing data to SSD10, ROIF driver 122 does not transfer normal write commands with respect to SSD10 at all (such as 35hWRITE DMA EXT and 61h WRITE FPDMA QUEUE described in ACS-2), and if data needs to be written into SSD10 with exception, it is desirable to allow writes with respect to SSD10 only by commands using special commands (such as SCT Command Transport described in INCITS ACS-2 and other commands unique to the vendor).

Also in the third embodiment, as illustrated in fig. 5, when the power of the host device 100 is turned off, the SSD control tool 110 is stored in the area 110A of the NAND memory 20 of the SSD10, but is loaded from the area 110A to the area 110 at the time of startup of the host device 100 or program startup. As illustrated in fig. 6, if a plurality of external storage devices are connected to the host device, the SSD control tool may be stored in the area 110B of the non-volatile storage device 300 which is the SSD10 but is different from the SSD10, and may be loaded from the area 110B to the area 110 at the time of startup or program startup of the host device 100. In particular, if the nonvolatile storage device 300 is used as a system driver for storing an OS, and the SSD10 is used as a data driver for storing user data (such as files, still image data, and moving image data), it is desirable to store a control tool in the nonvolatile storage device 300 used as a system driver from the standpoint of clearly separating the roles of the driver 10 and the driver 30 (such as using the system driver 30 as a driver for mainly storing an OS and an application program, and using the data driver 10 as a driver for storing user data).

And in the third embodiment, as illustrated in fig. 5 and 6, it is desirable that the computer system 1 be shipped with the SSD control tool stored in the SSD10 or the nonvolatile storage device 300, placed on a rack, and provided to the user from the standpoint of saving labor for the user in performing the setting of the control tool. From the standpoint of enabling the user to select whether to install the SSD control tool and from the standpoint of providing the latest control tool to the user, it is desirable that the control tool be stored in the SSD10 or the nonvolatile storage device 300 by downloading from the web page illustrated in fig. 7, installing from the DVD-RO M illustrated in fig. 8, and installing from the external storage device storage medium (USD memory) illustrated in fig. 9. And in the third embodiment, from the standpoint of promoting user availability, it is desirable that the optical medium 500 and the USB memory 600 package and sell together the SSD10 as an accessory when the SSD10 is shipped. The optical medium 500 or the USB memory 600 may be sold separately as a software product or may be attached as a supplement to magazines and books.

Accordingly, SSD control tool 110 mounted on host 100 determines the reliability status (statistical information) of SSD10, and selects an interface driver for the SSD based on the determination result, and thus when the reliability of SSD10 deteriorates (when the end of life is reached, in an abnormal state), it appears to the OS and other software as if SSD10 is switched from the readable-writable external storage device to the external storage device that does not support writing. Accordingly, the SSD10 with degraded reliability serves as a read-only device for the OS and software, so that the host 100 can handle the SSD10 as a general-purpose read-only external storage device, such as a CD-ROM or a DVD-ROM.

(fourth embodiment)

In the first and second embodiments, the SSD10 transmits information that the SSD10 is a read-only device to the host 100. Using the interface relay device 700 prepared separately from the SSD10, the interface relay device 700 can transmit information that the SSD10 is a read-only device to the host 100. Interface relay 700 is referred to as a read-only bridge. In the fourth embodiment, SSD10 itself does not necessarily need to be able to switch to RO mode.

Fig. 32 illustrates a state in which the read-only bridge 700 is connected to the computer system illustrated in fig. 10. FIG. 33 is a block diagram illustrating a computer system connecting a fourth embodiment of a read-only bridge. Read-only bridge 700 is configured to transmit information that is a read-only device to host 100. The information that is a read-only device may be the command GETCONFIGURATION (46h) employed in MMC-6 described above, or may be other commands. Further, read-only bridge 700 is configured to act as a relay of host-side and SSD-side interfaces (e.g., to transmit various commands and responses received from host 100 to SSD10 and to transmit various commands and responses received from SSD10 to host 100). If the interface standards of the host-side interface and the SSD-side interface are different, the read-only bridge 700 converts the received command and response so as to comply with the transmission-side interface, and then transmits the accepted command and response. If the host-side interface is a SATA interface, read-only bridge 700 may be configured to explicitly indicate to host 100 that SSD10 is an ATAPI device. For example, in the device signature described in ACS-2, LBA (7:0) output is 01h, LBA (15:8) output is 14h, and LBA (23:16) is output as EBh to the host 100, so that the host 100 can be notified that SSD10 is an ATAPI device.

During normal use of host 100, SSD10 is connected to motherboard 130 of host 100 by a SATA cable or USB cable that serves as TTA interface 90, as illustrated in fig. 10. When the SSD control tool 110 mounted on the host 100 acquires the statistical information by the s.m.a.r.t information described in ACS-2 above and determines that the reliability of the SSD10 is deteriorated when the condition of the statistical information > RMAX, statistical information < RMIN, or X24=1 is satisfied by comparing the management information and the threshold value, the SSD control tool 110 displays a warning window (or warning dialog) including a message (such as "SSD lifetime is at the end of life. connect the device-side terminal of the read-only bridge to the SSD, connect the host-side terminal of the read-only bridge to the personal computer, and back up the SSD data") on the display 133. The threshold (RMAX, RMIN, etc.) to be compared with the management information may be held in the host 100 so that the SSD control tool 110 may perform the determination of the reliability degradation, or the threshold may be held in the SSD10 so that the storage controller 50 of the SSD10 may perform the determination of the reliability degradation, and the storage controller 50 may transmit only information that the management information exceeds the threshold to the host 100.

As illustrated in fig. 32, according to the warning message displayed on the display 133, the user connects the SSD10 with the read only bridge 700 with a SATA cable, a USB cable, or the like, and connects the read only bridge 700 with the motherboard 130 with a SATA cable, a USB cable, or the like.

When host 100 is then started, read-only bridge 700 passes information that SSD10 is a read-only device to host 100. Next, host 100 applies the read-only drive of the read-only ATAPI drive as interface drive 170 of read-only bridge 700, and SSD10 is identified as a read-only device, such as a CD-ROM and DVD-ROM on the host. On the other hand, the read-only bridge 700 may be configured to explicitly indicate to the host 100 that the SSD10 is an ATA DEVICE, and may be configured to return to the host that all write functions are not supported when DEVICE identification information (such as the command EChINDENTIFY DEVICE described in ACS-2) is received from the host 100 over the ATA interface. The method of informing SSD10 whether it is a read-only device may take a variety of other ways.

In the present embodiment, when the write operation with respect to the SSD is disabled or not guaranteed, the host can perform the read operation on the SSD10 by simply connecting the read-only bridge 700 between the host 100 and the SSD even under the condition that the write operation with respect to the SSD may cause the SSD data defect or the SSD failure.

The system disk to boot the host with the read only bridge 700 connected may be the SSD10, or may be an SSD or a Hard Disk Drive (HDD) prepared separately from the SSD10 in which the system is previously installed, or may be a DVD-ROM, a CD-ROM, or a USB memory in which a boot program is installed.

Even when the read only bridge 700 is connected, the host 100 can save the SSD control tool 110 having a function of backing up data of the SSD or other software. When it is detected that read-only bridge 700 is connected, software having a backup function displays a message such as "read-only bridge connected, backup SSD data? "and a" ok "button and a" cancel "button for selecting backup necessity in a window of the software. The backup is started when the "ok" button is clicked with the mouse 135, and the message displayed disappears without the backup when the "cancel" button is clicked with the mouse 135. The backup may be performed later even if the "cancel" button is pressed with the mouse 135.

In the first to fourth embodiments, the case where the NAND memory is employed for the nonvolatile memory has been described, but the first to fourth embodiments can also be applied to nonvolatile memories other than the NAND memory, such as a Hard Disk Drive (HDD) for the nonvolatile memory. The non-volatile memory may be a semiconductor storage medium as shown in U.S. patent application publication No. 20100172189 and U.S. patent application publication No. 20100254191, in which the memory cells are arranged in three dimensions.

Although specific embodiments have been described, these embodiments are presented by way of example only. And are not intended to limit the scope of the present invention. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying drawings and equivalents thereof are intended to include such forms or modifications as would fall within the scope and spirit of the inventions.

Claims

1. An information processing device comprising a host device and an external storage device, wherein,

The external storage device includes:

Readable and writable non-volatile memory,

an interface controller connected to the host device, the interface controller enabling a first interface controller for supporting read and write operations of the nonvolatile memory and a first interface controller for supporting only the nonvolatile memory The read operation of the read operation to the second interface controller is alternately selected, and

a first control unit for determining whether a switching condition that causes the nonvolatile memory to switch to a read-only mode for performing only the read operation of the read/write operation is satisfied, and when the switching condition is satisfied , switching the interface controller from the first interface controller to the second interface controller; and

The host device includes:

an interface driver for operating the external storage device, the interface driver enabling a first interface driver for supporting read and write operations of the nonvolatile memory and a first interface driver for supporting only the nonvolatile memory read and write operations are alternately selected for the second interface driver for read operations, and

A second control unit for determining, based on information acquired from the external storage device, whether the non-volatile memory is recognized as a read-only memory where only read-write operations are possible, and when it is determined that the recognition is When it is a read-only memory, switch the interface driver from the first interface driver to the second interface driver.

2. The information processing device according to claim 1, wherein the first control unit determines whether the switching condition is satisfied during operation of the external storage device and at startup of the external storage device.

3. The information processing device according to claim 1, wherein, during operation of the host device and at startup of the host device, the second control unit determines whether to recognize the nonvolatile memory as only read memory.

4. The information processing apparatus according to claim 1, wherein,

notifying the host device that the host device is a readable and writable device in response to an access from the host device by the first interface controller;

The second interface controller notifies the host device that a read operation, which is only a read and write operation, is possible in response to an access from the host device.

5. The information processing apparatus according to claim 1, wherein,

when a write request is received from the host device, the second interface controller returns an error to the host device;

The second control unit switches the interface driver from the first interface driver to the second interface driver when an error is received from the external storage device.

6. The information processing apparatus according to claim 1, wherein, after switching the interface driver from the first interface driver to the second interface driver, the second control unit explicitly notifies the user whether to switch the interface driver to the second interface driver. backup the stored data of the non-volatile memory to another storage medium, and if approved, back up the stored data of the non-volatile memory to another storage medium.

7. A control method for an information processing device comprising a host device and an external storage device, the external storage device comprising a readable and writable non-volatile memory, the method comprising:

It is determined in the external storage device whether a switching condition causing the nonvolatile memory to switch to a read-only mode of a read operation performing only a read-write operation is satisfied, and when the switching condition is satisfied, causing the non-volatile memory to switch to a read-only mode The interface controller of the host device is switched from the first interface controller that supports the read and write operations of the nonvolatile memory to the second interface controller that only supports the read and write operations of the nonvolatile memory. device; and

Determining in the host device whether the nonvolatile memory is identified as a read-only read-only memory is a possible read-only memory based on information obtained from the external storage device, and when it is determined that the read-only memory is identified as a read-only When reading the memory, the interface driver used to operate the external storage device is switched from the first interface driver that supports the read and write operations of the non-volatile memory to the first interface driver that only supports the read and write operations of the non-volatile memory. Second interface driver for read operations.

8. The control method of an information processing device according to claim 7, further comprising:

returning an error from the external storage device to the host device when a write request is received from the host device;

The interface driver is switched from the first interface driver to the second interface driver in the host device when an error is received from the external device.

9. The control method of an information processing device according to claim 7, further comprising:

After switching the interface driver from the first interface driver to the second interface driver, the host device explicitly notifies the user whether to back up the stored data of the external storage device to another storage medium, if obtained If approved, back up the storage data of the external storage device to another storage medium.

10. A host device connected to an external storage device, the external storage device comprising a readable and writable non-volatile memory, the host device comprising:

an interface driver for operating the external storage device, the interface driver enabling a first interface controller for supporting read and write operations of the nonvolatile memory and a first interface controller for supporting only the nonvolatile memory The second interface controller for the read operation of the read operation is alternately selected; and

a control unit for determining, based on information obtained from the external storage device, whether the nonvolatile memory is identified as a read operation that is identified as a read-only operation as a possible read-only memory, when it is determined that the read-only memory is identified as read-only When storing, switching the interface driver from the first interface driver to the second interface driver.

11. The host device according to claim 10, wherein the control unit determines whether to recognize the nonvolatile memory as a ROM during operation of the host device and at startup of the host device.

12. The host device of claim 10, wherein:

when receiving a write request from the host device after switching to a read-only mode in which the nonvolatile memory performs only the read operation, the external storage device returns an error to the host device;

The control unit switches the interface driver from the first interface driver to the second interface driver when an error is received from the external device.

13. The host device according to claim 10, wherein, after switching the interface driver from the first interface driver to the second interface driver, the control unit explicitly notifies the user whether the external storage The storage data of the device is backed up to another storage medium, and if approved, the storage data of the external storage device is backed up to another storage medium.

14. A control program loaded in a host device connected to an external storage device, the external storage device includes a readable and writable non-volatile memory, and the host device includes an interface driver for operating the external storage device , the interface driver makes the first interface driver for supporting the read and write operations of the non-volatile memory and the second interface driver for only supporting the read and write operations of the non-volatile memory are alternately selected; where,

The control program determines, based on information obtained from the external storage device, whether the non-volatile memory is identified as a read-only memory where only a read-write operation is possible, and is arranged to, when determined to be identified as a read-only memory When reading the memory, switch the interface driver from the first interface driver to the second interface driver.

15. The control program according to claim 14, wherein, during operation of the external storage device and at startup of the external storage device, the control program determines whether to recognize the nonvolatile memory as read-only memory.

16. The control program according to claim 14, wherein the control program determines whether to recognize the nonvolatile memory as a read-only memory during operation of the host device and at startup of the host device.

17. The control program according to claim 14, wherein the control program requests the transmission of statistical information to the external storage device, compares the statistical information received from the external storage device with a threshold, and if the If the statistical information exceeds the threshold, it is determined that the external storage device is identified as a read-only memory.

18. The control program according to claim 14, wherein,

when receiving a write request from the host device after switching to a read-only mode causing the non-volatile memory to perform only read operations, the external storage device returns an error to the host device,

The control program switches the interface driver from the first interface driver to the second interface driver when an error is received from the external storage device.

19. The control program according to claim 14, wherein after switching the interface driver from the first interface driver to the second interface driver, the control program explicitly notifies the user whether to switch the external storage The storage data of the device is backed up to another storage medium, and if approved, the storage data of the external storage device is backed up to another storage medium.

20. An external storage device connected to a host device, the external storage device comprising:

Readable and writable non-volatile memory;

an interface controller connected to the host device, the interface controller enabling a first interface controller for supporting read and write operations of the nonvolatile memory and a first interface controller for supporting only the nonvolatile memory The second interface controller for the read operation of the read operation is alternately selected; and

a control unit for determining whether a switching condition for causing the nonvolatile memory to switch to a read-only mode of a read operation that performs only read and write operations is satisfied, and when the switching condition is satisfied, causing the interface controller transitioning from the first interface controller to the second interface controller.

21. The external storage device according to claim 20, wherein the control unit determines whether the switching condition is satisfied during operation of the external storage device and at startup of the external storage device.

22. The external storage device of claim 20, wherein:

the first interface controller notifies the host device as a readable and writable device in response to an access from the host device;

23. An information processing device comprising a host device, an external storage device and a relay device, the external storage device includes a readable and writable non-volatile memory, and the relay device can be connected between the host device and the between external storage devices to relay information between said host device and said external storage device, wherein,

The host device includes a control unit for determining, based on information obtained from the external storage device, whether to identify a read operation of the nonvolatile memory as a read-only operation as a possible read-only operation. memory, and when it is determined that it is identified as a read-only memory, explicitly notify the user to connect the relay device between the host device and the external storage device,

The relay device includes a notification unit configured to notify the host device that the host device is a read-only device when it is detected that the host device is activated,

The control unit uses an interface driver that supports only a read operation of a read and write operation of the external storage device as an interface driver that operates the relay device in response to a notification from the relay device.

24. A control method for an information processing device comprising a host device, an external storage device and a relay device, the external storage device includes a readable and writable non-volatile memory, and the relay device can be connected to the host device and to and from the external storage device to relay information between the host device and the external storage device, the method comprising:

Determining in the host device whether to identify the nonvolatile memory as a read operation that is only a read and write operation is a possible read-only memory based on information obtained from the external storage device, when it is determined that the non-volatile memory is identified as read-only When storing, explicitly notify the user to connect the relay device between the host device and the external storage device;

notifying the host device as a read-only device upon detection of activation of the host device;

An interface driver that supports a read operation of a read and write operation of the external storage device is used as an interface driver that operates the relay device in response to a notification from the relay device.

25. A relay device for relaying information between a host device and an external storage device, the relay device being connectable between:

The external storage device includes a readable and writable non-volatile memory;

The host device including a control unit that determines whether to identify a read operation of the nonvolatile memory as a read-only operation as a possible read-only operation based on information received from the external storage device The memory, when it is determined to be identified as a read-only memory, explicitly notifies the user to connect the relay device between the host device and the external storage device, wherein,

The relay device includes a notification unit configured to notify the host device that the host device is a read-only device when the host device is activated,

An interface driver supporting only a read operation of a read and write operation of the external storage device is used in the host device as an interface driver for operating the relay device by the notification unit to the host device. .