CN103391002B - The system and method for the predictability current feedback of switch mode regulator - Google Patents
The system and method for the predictability current feedback of switch mode regulator Download PDFInfo
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Abstract
The present invention relates to the system and method for the predictability current feedback of switch mode regulator.It specifically discloses that a kind of predictability current feedback system for switch mode regulator, this system comprises: sampling and maintenance network, and the voltage for the lower switch both sides to adjuster is sampled and is provided as the inhibit signal of its instruction; And predictability current feedback network, bias-adjusted is added to inhibit signal based on the duration of the pulsewidth of the pulse control signal formed by adjuster by it.Can sampling be completed when lower switch conducting, with pulse control signal for provide time low instruction inductor current retention value.When pulse signal is high, transient affair can be responded bias-adjusted is added to inhibit signal.After each delta time period of nominal time week after date, biased can be increment size, or variate when can be.Also adjustment can be made when pulse signal is low.
Description
The cross reference of related application
This application claims the U.S. Provisional Application S/N61/646 submitted on May 11st, 2012, the rights and interests of 007, the full content of this application is for institute is intentional and object is incorporated herein by reference.
Accompanying drawing explanation
By reference to the following description and accompanying drawing can understand benefit of the present invention, feature and advantage better, in the accompanying drawings:
Fig. 1 is the simplified block diagram of the electronic equipment being configured with power system according to one embodiment of the invention, and this power system has the adjuster realizing the modulator having predicted current to feed back;
Fig. 2 is the simplified schematic block diagram comprising the example regulator of the modulator of Fig. 1 realized according to an embodiment;
Fig. 3 is that the schematic block diagram of the predictability current feedback system realized according to embodiment and sequential chart represent;
The sequential chart of Fig. 4 to be the exemplary VIL curve of marking and drawing Fig. 3 together with a kind of composite signal HOLD+OFFSET of numeral configuration compare original HOLD signal;
Fig. 5 is the composite signal HOLD+OFFSET that marks and draws VIL and a kind of analog configuration sequential chart compared to original HOLD signal;
Fig. 6 is the simplification block diagram of the predictability current feedback system according to one embodiment of the invention realization; And
Fig. 7 marks and draws inductor current signal IL (corresponding to VIL), ISMPL, IHOLD, IOFS and IDROOP of overlapping each other relative to the zero level being illustrated as I0 to add PWM and MCK signal, and these signals are all plotted relative to the time.
Embodiment
By reference to the following description and accompanying drawing can understand benefit of the present invention, feature and advantage better.Provide following description can implement to make those of ordinary skill in the art under the background of application-specific and demand thereof and the present invention provided is provided.But General Principle as defined herein clearly, and will can be applied to other embodiment to those of ordinary skill in the art by the multiple amendment of preferred embodiment.Therefore, the present invention is not intended to be limited to the specific embodiment illustrating and describe herein, and should be given the widest scope consistent with principle disclosed herein and novel feature.
The electric current flowing through the output inductor of switch mode regulator is the parameter useful to various function, such as output voltage decline, ring adjustment, current monitoring and/or report (IMON) etc.There is many methods of planting sensing, measuring or otherwise predicting inductor current.
A kind ofly determine that the method for inductor current is monitoring or the voltage at series DC resistance (DCR) two ends measuring output inductor.DCR sensing has several shortcoming and deficiency.Because output inductor provides from outside relative to adjuster control integration circuit (IC) usually, therefore DCR sensing usually needs the voltage for detecting DCR two ends and additional external components is coupled to output inductor.Such as, external resistor-capacitor (RC) circuit is coupled to output inductor, and the terminal of the external capacitor of RC circuit is used to detect inductor current.DCR sensing also needs the NTC (negative temperature coefficient) for thermal drift to compensate usually, and network should be adjusted and carry out thermal compensation thus.NTC compensates and adds system complexity and cost to circuit designer.
The other method of sensing inductor current is to provide the sense resistor of connecting with output inductor.Independent sense resistor is costly, and consumption element will be had to be inserted in power train, reduces gross power conversion coefficient thus.
Buck adjuster generally includes pair of electrons device, and this current terminal to electronic device (such as drain electrode, source electrode) is in series coupling between input voltage VIN and reference voltage (such as).Electronic switch can be embodied as the transistor of any suitable type, such as metal-oxide semiconductor (MOS) (MOS) transistor, field-effect transistor (FET), MOSFET, bipolar junction transistor (BJT) and analog, igbt (IGBT) and analog, etc.The sensing (such as sensing the voltage at FET two ends, upper end) of upper end is difficult to complete inner (such as in control chip).A kind of high voltage guides or differential sensing method usually also should be accurate as much as possible by use.Upper end sensing to be the drift signal of reference again with ground.
Guide switch, the ratio version of such as actual switch FET, can produce proportional electric current to the electric current of those power devices.But acquisition has suitable common mode range (such as about 12V) and also has the accurate differential signal of transition time single digit nanosecond is difficult.
Drain-Source conducting resistance (the R of top and bottom FET switch
dS_ON) differential voltage measurement there is the difficulty identical with guide device.
To the R of lower end FET switch
dS_ONsampling compares both top and bottom devices and all carries out sampling more easy and cost is lower.Also allow the accuracy (such as externally microprocessor report average inductor current, this average inductor current is the instruction of load) of IMON function enough degree.Lower end sensing is enough for IMON function, but for the current feedback regulated with correctly perform output voltage decline function usual fast not enough.Especially, due to the sample delay during the load transient comprising load insertion transition and load releasing transition, the signal through sampling has larger error component.
As described herein, the gap during all load transient events can based on through the lower current information of sampling and the ON time estimated also " being filled " of pulse-width modulation (PWM) control signal.Inductor current level can be predicted during load transient between sample event.
Fig. 1 is the simplified block diagram of the electronic equipment 100 being configured with power system 101 according to the embodiment of the present invention, and this power system 101 has the adjuster 102 realizing the modulator 103 having predicted current to feed back.Power system 101 produces one or more supply power voltage, and the other system equipment that this one or more supply power voltage is electronic equipment 100 provides electric power.In the illustrated embodiment, electronic equipment 100 comprises processor 107 and peripheral system 109, processor 107 and peripheral system 109 are all coupled to receive the supply power voltage from power system 101 via bus 105, and bus 105 comprises any combination of power and/or intracellular signaling thing.In the illustrated embodiment, peripheral system 109 can comprise system storage 111(such as, comprise any combination of RAM and ROM types of devices and Memory Controller etc.) and any combination of I/O (I/O) system 113, this input/output 113 can comprise system controller etc., such as graphics controller, interrupt control unit, keyboard and mouse controller, system memory devices controller (such as, for the controller etc. of hard disk drive) etc.Illustrated system is exemplary, because it will be understood by those skilled in the art that multiple processor system and support equipment can be integrated in processor chips.
Electronic equipment 100 can be computer or the computing equipment of any type, such as computer system (such as, notebook, desktop computer, net book computer etc.), media flat-panel devices (such as, Kindle etc. that the iPad that Apple produces, Amazon Company produce), communication equipment (such as, cell phone, smart phone etc.), the electronic equipment (such as, media player, recording equipment etc.) of other types.Power system 101 can be configured to comprise battery (can fill again or non-can fill again) and/or can be configured to and work with exchanging together with (AC) adapter etc.
Fig. 2 is the simplification adaptability block diagram of the example regulator 102 comprising modulator 103 according to an embodiment realization.Adjuster 102 comprises the phase circuit 201 that can realize single phase system or polyphase system.Phase circuit 201 comprises gate drivers 203, and it receives pulse-width signal PWM and corresponding top gate signal UG is supplied to upper end electronic power switch Q1 and corresponding lower end signal LG is supplied to lower end electronic power switch Q2.Power switch Q1 and Q2 self have in series be coupling in input voltage VIN and common reference voltage GND(wherein GND represent ground connection or any other suitable plus or minus reference voltage level) between current terminal (such as drain electrode and source electrode).Note, GND can represent one or more reference node, comprises one or more earth level or node (such as signal ground, power ground connection, chassis ground etc.) or any other suitable reference voltage level.Switch Q1 and Q2 is coupled at mesophase spherule node 205 place, thus formed phase voltage VPH, and the coupled one end of output inductor L to phase node 205 and the other end be coupled to generation output voltage VO UT output node 207.Output capacitor CO and load 209 are coupling between output node 207 and GND.Load 209 represents any one or more load devices, arbitrary device of such as processor 107 and/or peripheral system 109.
The electric current I L flowing through inductor L is by analog sensing or otherwise synthesize, and the inductor current sensing signal ISENS of correspondence is provided to modulator 103.Modulator 103 receives feedback signal VFB and the ILSENS of VOUT and/or instruction VOUT, and produces the pwm signal being used for control phase circuit 201.VFB can be proportional signal that is that sense or instruction VOUT, such as, produced by voltage divider or analog (not shown).In operation, modulator 103 uses ISENS and VOUT (and/or VFB) and may use other signal sensed or parameter, and especially produces pwm signal in order to the loop adjustment function of such as IMON and voltage drop etc.Gate drivers 203 produces UG and LG, with electronic switch Q1 and Q2 that be turned on or off to regulate the voltage level of VOUT based on PWM.
The present invention uses buck switch mode voltage transducer to be described as switch mode regulator, and wherein input voltage is higher than output voltage.But be appreciated that, the present invention can be applicable to the electric pressure converter of other type equally, such as boosting type converter (wherein output voltage is boosted relative to input voltage to higher) and various compound mode, such as buck-boost and/or voltage boosting-reducing etc.Those skilled in that art should know and know, sensing inductor current can be applicable to the switch mode regulator of any type equally as described herein.
Fig. 3 is that the schematic block diagram of the predictability current feedback system realized according to embodiment and sequential chart represent.The output stage of adjuster 102 is illustrated as and comprises switch Q1, Q2, output inductor L, output capacitor CO and load 209.Sampling and keep (SNH) network 301 to have the positive pole input of drain electrode and the source electrode being coupled to Q2 (lower end FET) and negative pole inputs, effectively to sample to the level of VPH and to provide corresponding HOLD signal in its output when Q2 conducting.The diagram of SNH network 301 exports the exemplary illustrations describing HOLD signal in operation, and this output is overlapping with the relevant voltage signal VIL representing inductor current when PWM is low.When PWM is high, VIL is represented by dashed line in the drawings, does not wherein directly monitor the voltage of Q2 both sides.When sampling to the voltage of Q2 both sides when Q2 conducting, VIL solid line illustrates.Generally speaking, when PWM uprises, Q1 conducting and Q2 cut-off, thus make phase node 205 be coupled in input voltage VIN therefore make the input side of inductor L be coupled in input voltage VIN, make the upward change of inductor current thus.When PWM step-down, Q1 ends and Q2 conducting, thus makes phase node 205 be coupled in GND, makes inductor current become to declivity thus.
VIL is generally derived as the R of Q2
dS_ONbe multiplied by inductor current IL, or VIL=ILR
dS_ON.Therefore VIL characterizes inductor current IL when PWM is low.When PWM is conducting, VIL is illustrated as dotted line, because this part of VIL is without sampling.When PWM be cut off and Q2 conducting time, the voltage of Q2 both sides is sampled by SNH network 301 and subsequently sampled value is remained on the output of Q2, until exports next retention value.Generally speaking, have the nominal time cycle at the duration of the ON time of sampling period Q2 during limit, wherein SNH network 301 exports the large maintenance sampled value about the centre position in nominal time cycle.Point along HOLD signal represents when each retention value terminates to form HOLD signal in sampling period.
When Q2 conducting and PWM is low time, SNH network 301 only to VIL sampling to form HOLD signal.Originally, when load is low, HOLD signal is generally accurately and follows the DC level (and not having ripple) of VIL.But insert transition in response to load, VIL upwards skips to higher level, HOLD signal remains on level lower shown in time t1 simultaneously.Pwm signal remains conducting for a long time, thus makes VIL be increased to higher level.Due to Q2 remain off, the level of sampling before HOLD is maintained at, this causes larger difference between HOLD and the VIL shown in time t1 or error.When PWM finally dragged down and Q2 again conducting time, again sampled to VIL by SNH network 301, and export another retention value, this makes HOLD signal skip to higher level.
Remove transition in response to load, the difference between similar HOLD and VIL occurs, and approximately occurs in time t2 as shown in the figure.In this case, only have when Q2 conducting a retention value to be output, and Q2 keeps conducting in longer cycle, thus make VIL be down to lower level.Because VIL keeps conducting for a long time, therefore HOLD signal remains height, and this causes the relatively large difference at time t2 between HOLD and VIL.When PWM is high again, Q2 ends and Q1 conducting, does not still change to make HOLD signal.Finally, PWM step-down, thus make Q2 conducting and export a new HOLD value, HOLD signal skips to new DC level thus.
In short, HOLD follows VIL substantially, but deviates from significantly in VIL during load transient, when comprising load insertion and load releasing, as shown in time t1 and t2 in figure.
An input of predictable current feedback (PCF) network 303 is received in the HOLD signal of SNH network 301 output, and its another input receives PWM, and its output provides OFFSET signal.OFFSET is added to HOLD to form the signal HOLD+OFFSET through combination by combiner (such as adder) 305.PCF network 303 is configured to predict the level of VIL based on PWM and HOLD and produce OFFSET, is the more accurate characterization of inductor current to make the signal of combination.Providing the various methods for realizing PCF network 303, comprising digital scheme and modeling scheme.
The sequential chart of Fig. 4 to be the exemplary VIL curve of marking and drawing Fig. 3 together with a kind of composite signal HOLD+OFFSET of numeral configuration compare original HOLD signal.The digital signal of this combination is indicated by the solid line, wherein original HOLD signal deviate from represented by dashed line in the drawings.PCF network 303 monitors the ON time (t of pwm signal
oN) and with predetermined nominal ON time cycle t
oN_NOMcompare.Work as t
oNexceed t
oN_NOMone delta time period Δ t
oN(t
oN_NOM+ Δ t
oN) time, OFFSET is asserted to a predetermined increment bias OFFON by it, and this increment bias OFFON is added to HOLD.When PWM is at another delta time period Δ t
oN(t
oN_NOM+ 2 Δ t
oN) keep conducting time, OFFSET signal is doubly increased to doubles bias OFF
oN(2OFF
oN), this bias is added to HOLD increases another OFF to make the signal of combination further
oNincrement.When PWM is at another delta time period Δ t
oN(t
oN_NOM+ 3 Δ t
oN) keep conducting time, OFFSET signal is doubly increased to by three times and is three times in bias OFF
oN(3OFF
oN), this bias is added to SNH to be increased to make the signal of combination further.When PWM step-down and Q2 final conducting time, the signal through combination is kept, until obtain new sampling.
Remove between transient period in load afterwards, identical process can be performed.PCF network 303 monitors (t deadline of pwm signal
oFF) and with predetermined nominal cycle deadline t
oFF_NOMcompare.Work as t
oFFexceed t
oFF_NOMone delta time period Δ t
oFF(t
oFF_NOM+ Δ t
oFF) time, OFFSET is asserted to a predetermined increment bias OFF by it
oFF, this increment bias OFF
oFFbe added to HOLD.When PWM is at another delta time period Δ t
oFF(t
oFF_NOM+ Δ t
oFF) remain off time, OFFSET signal is doubly increased to doubles bias OFF
oFF(2OFF
oFF), this bias is subtracted to make the signal of combination reduce another OFF further from HOLD
oFFincrement.When PWM conducting next time, this process repeats.
In general, for numeral configuration, when PWM is than predetermined nominal time cycle longer ground conducting or cut-off, HOLD is in the conducting increased or increase after cycle deadline or reduce an incremental change.In one embodiment, the time cycle Δ t of each increase
oNfixing, and the bias OFF of each increase
oNalso be fixing, rise with fixing speed ladder through the HOLD signal of adjustment when PWM conducting thus.The time cycle increased constructs for a customized configuration with biased.Similarly, the time cycle Δ t of each increase
oFFfixing, and the bias OFF of each increase
oFFalso be fixing.In another embodiment, time cycle of increase and/or bias can be changes.In any case, the time cycle of design time increase and the biased of correspondence, closer follow VIL to make composite signal HOLD+OFFSET than independent HOLD.In one embodiment, bias OFF can be set based on operating parameter (voltage level of such as VIN) and component value adaptively by modulator 103
oNand OFF
oFF.
Fig. 5 is the composite signal HOLD+OFFSET that marks and draws VIL and a kind of analog configuration sequential chart compared to original HOLD signal.The analog signal of this combination is indicated by the solid line, wherein original HOLD signal deviate from represented by dashed line in the drawings.In one embodiment, once the ON time of PWM exceeds predetermined nominal ON time cycle t
oN_NOM, such as insert transition in response to load, OFFSET signal is just based on the upward change of simulation ratio of last lower end sampling, and HOLD+OFFSET is with the upward change of VIL speed estimated thus, until PWM is cut off.After PWM cut-off, normal sampling and maintenance operation continue, and do not exceed t simultaneously
oN_NOMwith predetermined nominal cycle deadline t
oFF_NOM.Predetermined nominal cycle deadline t is exceeded when the deadline of PWM
oFF_NOMtime, such as remove transition in response to load, SNH network 301 is operated in tracking and Holdover mode, and this mode tracking VIL is until assert PWM next time.Next when asserting PWM at time t1, retention value is maintained at this level, until export next retention value, and PWM is in normal sampling with during keeping operation at time t2 as shown in figure for cut-off.
Fig. 6 is the simplification block diagram of the predictability current feedback system 600 according to one embodiment of the invention realization.PWM is illustrated as the grid of driving Q1 and by phase inverter 603 paraphase, this phase inverter 603 exports at it paraphase version grid of Q2 being provided to PWM, or
this is a kind of simplification and functional descriptions of operation, and wherein the such as gate drivers of gate drivers 203 is generally used for driving power switch.Analog-digital converter (ADC) 601 is sampled to the phase voltage VPH (or VIL) of Q2 both sides when PWM is low.ADC601 provides digital current sampled value I in its output
sMPL, this digital current sampled value I
sMPLbe provided to the input of memory 605.Memory 605 provides clock by the memory clock signal MCK of the output of 2 input AND doors 629, and 2 input AND doors 629 receive in its input
with signal DO.
by the output of phase inverter 603 or provided by the output of another phase inverter 613.When DO is asserted to height and simultaneously
for time high, memory 605 exports at it I will received in its input
sMPLvalue remains digital current retention value I
s & H.I
s & Hbe provided to the input of I2CIMON report blocks 607, I2CIMON report blocks 607 for report inductor current through keeping version and without the need to correcting external devices.
D-A converter (DAC) 609 receives I in its input (or numeral input of correspondence)
s & H, and export analog current value I at it
hOLDbe supplied to electric current summing junction 610.I
s & H(numeral) and I
hOLD(simulation) is corresponding with previously described HOLD signal.Node 610 exports drop-out current I
dROOP, I
dROOPbe provided to decline network (not shown) to perform decline function.As understood in those skilled in that art, decline function is the premeditated adjustment because becoming the voltage level to output voltage VO UT in load.Requirement provides than by I
hOLDthe VIL more accurately provided characterizes.As described further herein, bias current I is passed through based on predictability current feedback
oFSto I
dROOPregulate, described predictability current feedback is for providing the more accurate characterization of inductor current IL.Therefore, I
dROOP=I
hOLD+ I
oFS, wherein I
dROOPcharacterize previously described composite signal HOLD+OFFSET (DIG).It should be noted that as described further herein, for lower COUNT value, I
oFSbe zero.
PWM is provided to the input of Edge check block 617, and this Edge check block 617 has the output that the clearing (CLR) that is provided to upwards counter 619 inputs.Upwards counter 619 has clock input (CLK), and what this clock input (CLK) reception was provided by clock generator 621 has frequency F
cLKclock signal clk.In one embodiment, CLK has corresponding over-sampling frequency (such as F
cLK=50MHz) over-sampling clock, although the clock frequency substituted also can be considered.Therefore, upwards counter 619 to be all cleared at the rising edge of PWM and trailing edge and with by F
cLKthe speed determined upwards counts (from predetermined minimum value or zero), and provides digital output value COUNT.COUNT is provided to decoder 612, and the output of this decoder 612 is by digital bias value I
oFFbe supplied to the corresponding input of another DAC611.DAC611 has the sampling receiving PWM and inputs, receives
maintenance input (via phase inverter 613) and provide simulation bias current signal I
oFSanalog current export, bias current signal I
oFSi
oFFanalog version.When PWM is asserted to high, switch 615 closes, and when closing switch 615 by electric current I
oFSbe supplied to node 610.The I when PWM is asserted to high
dROOPbe confirmed as I
hOLDadd I
oFS, the I when PWM is low
dROOPbe confirmed as I
hOLD(when switch 615 disconnects).
Numeral COUNT value is provided to the input of decoder 627, and another input of this decoder 627 receives the digital version of dutyfactor value D.Block 623 detects input voltage VIN and output voltage VO UT, and the analog version of duty ratio is defined as D=VOUT/VIN.The output of block 623 is provided to the input of ADC625, and the digital version of D is supplied to decoder 627 by ADC625.In the illustrated embodiment, as COUNT=((1-D)/2) TSF
cLKtime, decoder 627 its export make DO be high impulse to AND door 629, wherein TS is the switching cycle of adjuster 102.
In general, upwards counter 619 is used to provide COUNT, the duration of pulse duration when COUNT indicates PWM to be in conducting (such as high) and to be in cut-off (such as low).Decoder 627 uses COUNT to determine the suitable retention time (such as intermediate point) of PWM low time, and simultaneously Q2 conducting thinks that memory 605 provides clock with by the value I through sampling
sMPLremain I
s & H, I
s & Hinstruction inductor current.When PWM is high, decoder 612 uses COUNT to follow the tracks of t
oN_NOMwith Δ t
oN, and by I
oFFbe asserted to proper level with by drop-out current I
dROOPadjust a suitable amount of bias I
oFS.When PWM exceeds the nominal time amount t occurred when upwards counter 619 arrives the nominal count value determined by decoder 612
oN_NOMtime, regulate I according to equation below
oFS: I
oFS=(VIN-VOUT) TS/ (2L)+Δ t
oN(VIN-VOUT)/L, wherein " L " is the inductance of output inductor L, and Δ t
oNbe and describe the identical fixed increment time cycle above.
Fig. 7 marks and draws the inductor current signal IL (corresponding with VIL), the I that overlap each other relative to the zero level being illustrated as I0
sMPL, I
hOLD, I
oFSand I
dROOPand PWM and MCK signal is all relative to the sequential chart of time.When PWM is high, IL is upward straighten PWM step-down till, be such as illustrated as initial time t0, there IL to return become to declivity.When PWM becomes low at time t0, the sampled value I of inductor current
sMPLsaltus step is to reflect the level of IL.When PWM is low (thus
for height) and IL becomes to declivity time, I
sMPLvalue follows IL.As COUNT=((1-D)/2) TSF
cLKand PWM is when being low, such as, shown in time t1, decoder 627 makes DO pulse paramount, and this also makes MCK pulse paramount at time t1.Memory 605 at time t1 by I
s & Hassert into I
sMPLthrough retention value, and electric current I
hOLDinstruction I is kept at the remainder of circulation
s & Hvalue (and therefore at the I of time t1
sMPLretention value).Operate in next circulation shown in time t2 to repeat by this way, wherein MCK forms pulse with by I once again at time t2
s & Hremain on I
sMPLvalue.So, at the ON time t of PWM
oNdo not exceed t
oN_NOMtime, I
hOLDgeneral tracking IL mean value and there is no load transient.Within this time, electric current I
dROOPgenerally follow I
hOLD.
Pwm signal uprises again at time t3, and PWM keeps comparing t at time t4 in this circulation
oN_NOMhave more Delta Time t
oN, transition is inserted in this instruction load.Time t4 is the time t relative to time t3
oN_NOM+ Δ t
oN.At time t4, I
oFSrecruitment I
dC+ I
iNC, wherein I
dCinstruction I
hOLDinitial DC amount and I
iNCit is increment current level.Therefore at time t4, I
dROOPfrom I
hOLDlevel skips to I
hOLD+ I
dC+ I
iNChigh value, this high value is about same level of the IL at time t4.When PWM is for each additional incremental time Δ t
oNwhen keeping conducting, another increment current amount I
iNCbe added to I
oFS, as shown in time t5 in figure.Due to I
dROOP=I
hOLD+ I
oFS, I
dROOPincrease identical amount.Therefore, PWM keep high while I
dROOPand I
oFSincrease all in a step-wise manner, and I
hOLDat I
sMPLlast retention value remain unchanged.Therefore, I
dROOPincrementally increase with than I
hOLDfollow IL more closely.
Again start to become to declivity to make IL at the last step-down of ensuing time t6, PWM.I
sMPLupwards skip to the new level of IL and follow IL when it becomes to declivity, as described previously.I
dROOPtemporarily remain unchanged in the position of the peak level close to IL, until MCK is at time t7, subpulse is paramount again.At time t7, I
oFSto returning step-down to I0, I
hOLD(it is I to skip to the new level of IL
sMPLlevel at time t7), and I
dROOPskip to I downwards
hOLDlevel.I
hOLD, and then I
dROOP, all follow the average level of IL, until next load transient event.
At time t6, IL deviates from I
hOLDreach a significant quantity, thus I
hOLDtemporarily inaccurately reflect IL, until ensuing time t7.As shown in the figure, between time t4 to time t7, I
oFSwith I
hOLDaddition allow I
dROOPfollow IL more accurately.Although clearly do not illustrate in the figure 7, responsive load removes transition can there is identical operation, I in this case
oFSalong negative direction stepped change with relative to I
hOLDreduce I
dROOPto follow the tracks of IL more accurately.
Although with reference to some preferred version of the present invention to invention has been enough detailed description, but also can consider other version and variants.Those skilled in that art are to be understood that they can use disclosed theory and specific embodiment as designing and revising the basis of other structure with the object providing the present invention identical easily, and do not depart from the spirit and scope of the present invention as claims definition below.
Claims (15)
1., for a predictability current feedback system for switch mode regulator, comprising:
Sampling and maintenance network, the voltage for the power switch both sides to described adjuster is sampled and is provided as the inhibit signal of its instruction; And
Predictability current feedback network, bias-adjusted is added to described inhibit signal based on the duration of the pulsewidth of the pulse control signal formed by described adjuster by described predictability current feedback network,
Wherein, for the predetermined increment bias-adjusted of each predetermined delta time period during described bias-adjusted is included in described pulsewidth.
2. predictability current feedback system as claimed in claim 1, it is characterized in that, described in described predictability current feedback network adjustment, inhibit signal is to provide more accurately judging of the electric current of the output inductor by described adjuster.
3. predictability current feedback system as claimed in claim 1, it is characterized in that, described pulse control signal switches back and forth between conducting and cut-off, first amount of bias is added to described inhibit signal by wherein said predictability current feedback network while described pulse control signal conducting after at least one first delta time period each of the first name time cycle, and deduct the second amount of bias from described inhibit signal after described predictability current feedback network at least one second delta time period each while described pulse control signal ends after the second name time cycle.
4. predictability current feedback system as claimed in claim 1, it is characterized in that, described pulse control signal switches back and forth between conducting and cut-off, time varying signal is added to described inhibit signal by wherein said predictability current feedback network while described pulse control signal conducting after the first name time cycle, and described sampling and maintenance network follow the voltage of described power switch both sides while described pulse control signal ends after the second name time cycle.
5. an electronic equipment, comprising:
Modulator, described modulator receives output voltage sensing signal and current sensing signal also forms the pulse control signal indicated as it, for control switch adjuster with regulation output voltage;
Sampling and maintenance network, the voltage for the phase node to described switching regulaor is sampled and is provided as the inhibit signal of its instruction; And
Predictability current feedback network, described predictability current feedback network provides bias-adjusted to regulate described inhibit signal based on the pulsewidth duration of described pulse control signal, thus forms described current sensing signal,
Wherein, described predictability current feedback network to be configured to when described pulse control signal is high biased incrementally add to described inhibit signal to each delta time period by one after a nominal time cycle.
6. electronic equipment as claimed in claim 5, is characterized in that, also comprise:
Output node, described output node forms described output voltage; And
Load, described load coupling is to described output node.
7. electronic equipment as claimed in claim 6, it is characterized in that, described load comprises the processor being coupled to memory.
8. electronic equipment as claimed in claim 5, is characterized in that:
Described switching regulaor comprises:
Upper end switch, described upper end switch couples is between input voltage node and described phase node;
Lower switch, described lower switch is coupling between described phase node and datum node;
Output inductor, described output inductor is coupling between described phase node and output node, and described output node forms described output voltage; And
The conducting when described pulse control signal is high of described upper end switch, and the conducting when described pulse control signal is low of described lower switch;
Wherein said sampling and maintenance network are sampled to the voltage of described lower switch both sides when described pulse control signal is low, and form the described inhibit signal as its instruction.
9., for switch mode regulator provides a method for predictability current feedback, comprising:
During the first state of pulse control signal, the voltage of power switch both sides is sampled, and be provided as the retention value of its instruction; And
During the second state of described pulse control signal, described retention value is added to by biased in response to load transient,
Wherein, add biased be included in the second state of described pulse control signal during add the first bias after each first delta time period after the first name time cycle.
10. method as claimed in claim 9, is characterized in that, deducts the second bias after each second delta time period during being also included in the first state of described pulse control signal after the second name time cycle from described retention value.
11. methods as claimed in claim 9, is characterized in that, described in retention value is provided and describedly adds to described retention value and comprise by biased and produce a decline control signal to control output voltage decline based on load.
12. 1 kinds, for the predictability current feedback system of switch mode regulator, comprising:
Sampling and maintenance network, the voltage for the power switch both sides to described adjuster is sampled and is provided as the inhibit signal of its instruction; And
Predictability current feedback network, adds to described inhibit signal by an amount of bias after each of at least one delta time period of all after dates of the nominal time of described predictability current feedback network in the pulsewidth of the pulse control signal formed by described adjuster.
13. 1 kinds, for the predictability current feedback system of switch mode regulator, comprising:
Sampling and maintenance network, the voltage for the power switch both sides to described adjuster is sampled and is provided as the inhibit signal of its instruction;
Predictability current feedback network, a bias-adjusted is added to described inhibit signal based on the duration of the pulsewidth of the pulse control signal formed by described adjuster by described predictability current feedback network; And
Counter network, described counter network provide the ON time duration that indicates described pulse control signal and deadline duration count value;
Wherein, described sampling and keep network to comprise the first decoder, described first decoder determines the value when kept when described pulse control signal is cut-off through sampling during described deadline duration based on described count value; And
Wherein, described predictability current feedback network comprises the second decoder, based on described count value, described second decoder determines when the described ON time duration of described pulse control signal exceeds each delta time period and be provided as the corresponding bias of its instruction after the predetermined nominal time cycle.
14. predictability current feedback systems as claimed in claim 13, is characterized in that:
Described sampling and maintenance network comprise:
First transducer, the voltage transitions of described power switch both sides is become sampled value by described first transducer;
Memory, described memory receives described sampled value and also responds the maintenance instruction from described first decoder and provide retention value; And
Second transducer, described second transducer converts described retention value to maintenance electric current; And
Wherein, described predictability current feedback network comprises the 3rd transducer, and described 3rd transducer converts described bias to bias current, and described bias current is added to described maintenance electric current in the described ON time duration of described pulse control signal.
15. 1 kinds provide the method for predictability current feedback for switch mode regulator, comprising:
During the first state of pulse control signal, the voltage of power switch both sides sampled and be provided as its retention value indicated;
Be biased one during the second state of described pulse control signal in response to load transient and add to described retention value, wherein, add one biased be included in the second state of described pulse control signal during after the first name time cycle, add to described retention value by becoming bias for the moment; And
After the second name time cycle, the voltage of phase node is followed to regulate described retention value during the first state of described pulse control signal.
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| US13/531,751 US8901910B2 (en) | 2012-05-11 | 2012-06-25 | System and method of predictive current feedback for switched mode regulators |
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| US10008854B2 (en) | 2015-02-19 | 2018-06-26 | Enphase Energy, Inc. | Method and apparatus for time-domain droop control with integrated phasor current control |
| CN104767410B (en) * | 2015-03-31 | 2017-05-03 | 西安理工大学 | Current prediction control method for single-phase gird-connected inverter |
| CN104753351B (en) * | 2015-03-31 | 2017-03-29 | 西安理工大学 | It is a kind of to be used for inductive current forecast Control Algorithm in non-isolated charging Buck circuits |
| CN109245531B (en) * | 2018-10-29 | 2020-07-07 | 合肥鑫晟光电科技有限公司 | Duty ratio determining method and device, and pulse width modulation signal generating method and device |
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| CN101425750A (en) * | 2007-10-31 | 2009-05-06 | 半导体元件工业有限责任公司 | Power supply controller and method therefor |
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