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CN103389959B - A kind of Modular multi-data conversion equipment and conversion method thereof - Google Patents

A kind of Modular multi-data conversion equipment and conversion method thereof Download PDF

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CN103389959B
CN103389959B CN201310301178.5A CN201310301178A CN103389959B CN 103389959 B CN103389959 B CN 103389959B CN 201310301178 A CN201310301178 A CN 201310301178A CN 103389959 B CN103389959 B CN 103389959B
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CN103389959A (en
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陈伟
邢梅香
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Luoyang Institute of Science and Technology
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Abstract

一种模块式多数据转换装置及其转换方法,其模块式多数据转换装置由由基于ARM Cortex核微处理器的核心控制模块、电源模块、设置键盘模块、LCD显示模块和可选的通讯模块:蓝牙模块、Zigbee模块、CAN模块、RS485模块、Profibus模块组成。该模块式多数据转换装置可以根据实际需要在ARM Cortex核微处理器的核心控制模块的通讯接口上接插可选的通讯模块,以实现多种通讯数据间的数据格式转换和数据传输。本装置采用基于ARM Cortex核的高性能微处理器为核心控制芯片的设计方案,硬件上采用具有可裁剪性的模块式安装方式,同时利用ARM Cortex核微处理器高速的处理特性,很方便地实现多种通讯数据间的数据转换和数据传输功能,具有处理响应速度快、体积小、较高的灵活性、较强的环境适应性等优点。

A modular multi-data conversion device and conversion method thereof, its modular multi-data conversion device consists of a core control module based on an ARM Cortex core microprocessor, a power supply module, a keyboard module, an LCD display module and an optional communication module : Bluetooth module, Zigbee module, CAN module, RS485 module, Profibus module. The modular multi-data conversion device can be plugged with an optional communication module on the communication interface of the core control module of the ARM Cortex core microprocessor according to actual needs, so as to realize data format conversion and data transmission among various communication data. This device adopts a high-performance microprocessor based on the ARM Cortex core as the core control chip design. The hardware adopts a modular installation method with tailorability. At the same time, it uses the high-speed processing characteristics of the ARM Cortex core microprocessor to facilitate Realize the data conversion and data transmission functions between various communication data, and have the advantages of fast processing response speed, small size, high flexibility, and strong environmental adaptability.

Description

一种模块式多数据转换装置及其转换方法A modular multi-data conversion device and its conversion method

技术领域 technical field

本发明属于一种基于ARM Cortex核微处理器的多数据通讯转换的技术领域。特别是一种模块式安装、多数据转换的装置和数据转换方法。 The invention belongs to the technical field of multi-data communication conversion based on ARM Cortex core microprocessor. In particular, a modular installation, multi-data conversion device and data conversion method.

背景技术 Background technique

现场总线是应用在工业生产现场测量控制设备之间、现场测量控制设备与控制室之间双向串行多节点数字通讯系统。目前现场总线技术、工业以太网和无线通讯技术在工业生产领域中得到了广泛的应用,工业现场控制网络现已成为工业控制过程系统中必不可少的组成部分,但这带来工业生产现场中多种通讯总线协议、多种行业通信标准并存的问题。 Fieldbus is a two-way serial multi-node digital communication system used between on-site measurement and control equipment in industrial production, and between on-site measurement and control equipment and the control room. At present, fieldbus technology, industrial Ethernet and wireless communication technology have been widely used in the field of industrial production, and the industrial field control network has now become an indispensable part of the industrial control process system. The coexistence of multiple communication bus protocols and multiple industry communication standards.

目前国内外市场上已有的不同功能的数据转换器产品,如研华股份有限公司的ADAM-4520隔离型RS232/RS485转换器;北京鼎实创新科技有限公司的RS232/485转Profibus和RS232/485转CAN的总线接口产品;“一种双现场总线接口转换器” (CN200810048932.8)的技术、“HBS总线通信协议与RS-485总线通信协议的双向通信转换方法”(CN201010140325.1)的技术、“一种智能开关电源通信协议转换器”(CN200620155551.6)的技术、“通信协议接口系统及方法”(CN200610003054.9)的技术、“基于ARM的多串口通信协议转换器”(CN201220398667.8)的技术、“无线传感器网络接入Modbus总线的网关通信协议转换方法”(CN201010529440.8)的技术等。这些技术研究和产品在数据转换应用上取得了一定的进展,但是其接口在转换功能仍不能满足工业过程控制领域中多现场总线控制网络数据转换的需求。 At present, there are data converter products with different functions in the domestic and foreign markets, such as Advantech's ADAM-4520 isolated RS232/RS485 converter; Beijing Dingshi Innovation Technology Co., Ltd.'s RS232/485 to Profibus and RS232/485 CAN-to-CAN bus interface products; technology of "a dual field bus interface converter" (CN200810048932.8), technology of "two-way communication conversion method between HBS bus communication protocol and RS-485 bus communication protocol" (CN201010140325.1) , "An intelligent switching power supply communication protocol converter" (CN200620155551.6), the technology of "communication protocol interface system and method" (CN200610003054.9), "ARM-based multi-serial port communication protocol converter" (CN201220398667. 8) technology, "Gateway communication protocol conversion method for wireless sensor network access to Modbus bus" (CN201010529440.8), etc. These technical researches and products have made some progress in the application of data conversion, but the conversion function of the interface still cannot meet the needs of data conversion of multi-field bus control network in the field of industrial process control.

发明内容 Contents of the invention

本发明的目的是提供一种基于ARM Cortex核微处理器的、硬件采用可裁剪的模块式安装、体积小的模块式多数据转换装置及其转换方法,本发明基于ARM Cortex核微处理器芯片高性能的处理能力和通讯模块的硬件可裁剪性,可以根据转换功能的需要适当增加或减少通讯模块的数量,实现不同通讯协议设备间通讯数据的转换和数据传输,以实现不同总线网络设备的网络管理与资源共享,达到节省资金的目的。 The purpose of the present invention is to provide a modular multi-data conversion device and conversion method thereof based on an ARM Cortex core microprocessor, the hardware adopts a modular installation that can be cut, and the volume is small. The present invention is based on an ARM Cortex core microprocessor chip The high-performance processing capability and the hardware tailorability of the communication module can appropriately increase or decrease the number of communication modules according to the needs of the conversion function, and realize the conversion and data transmission of communication data between different communication protocol devices, so as to realize the communication between different bus network devices. Network management and resource sharing achieve the goal of saving money.

为了实现上述的目的,本发明的技术方案是:由基于ARM Cortex核微处理器的核心控制模块、电源模块、设置键盘模块、LCD显示模块和通讯模块组成,所述的通迅模块为蓝牙模块、Zigbee模块、CAN模块、RS485模块和Profibus模块中的两种或多种模块,该转换装置可以根据需要在ARM Cortex核微处理器的核心控制模块的通讯接口上接插可选的通讯模块,很方便地实现多种通讯数据间的数据格式转换和数据传输的功能。其中: In order to achieve the above-mentioned purpose, technical scheme of the present invention is: be made up of core control module based on ARM Cortex core microprocessor, power supply module, keyboard module, LCD display module and communication module, described communication module is bluetooth module , Zigbee module, CAN module, RS485 module and Profibus module, the conversion device can be plugged with an optional communication module on the communication interface of the core control module of the ARM Cortex core microprocessor as required, It is very convenient to realize the functions of data format conversion and data transmission among various communication data. in:

ARM Cortex核微处理器的核心控制模块的电压输入端与电源模块的电压输出端连接;设置键盘模块的键盘输出端与ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的键盘输入I/O端连接;LCD显示模块的LCD控制端、LCD数据端分别与ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的LCD控制I/O端、LCD数据端连接;蓝牙模块的蓝牙控制端和蓝牙数据端通过ARM Cortex核微处理器的核心控制模块的蓝牙接口分别与ARM Cortex核微处理器的蓝牙控制I/O端和蓝牙数据端连接;Zigbee模块的Zigbee控制端和Zigbee数据端通过ARM Cortex核微处理器的核心控制模块的Zigbee接口分别与ARM Cortex核微处理器的Zigbee控制I/O端和Zigbee数据I/O端连接;CAN模块的CAN数据端通过ARM Cortex核微处理器的核心控制模块的CAN接口分别与ARM Cortex核微处理器的CAN数据端连接;RS485模块的RS485数据端和RS485控制端通过ARM Cortex核微处理器的核心控制模块的RS485接口分别与ARM Cortex核微处理器的RS485数据端和RS485控制I/O端连接;Profibus模块的Profibus控制端和Profibus数据端、Profibus地址端通过ARM Cortex核微处理器的核心控制模块的Profibus接口分别与ARM Cortex核微处理器的Profibus控制I/O端口、Profibus数据端、Profibus地址端连接;ARM Cortex核微处理器的串口数据端与RS232串口模块的串口数据端连接,RS232串口模块的串口数据端与RS232设备的串口数据端连接;ARM Cortex核微处理器的EEPROM数据端、EEPROM控制端与EEPROM存储器的EEPROM数据、EEPROM控制端连接;ARM Cortex核微处理器的SRAM数据端、SRAM地址端、SRAM控制I/O端口分别与SRAM存储器的SRAM数据、SRAM地址端、SRAM控制端连接。 The voltage input end of the core control module of the ARM Cortex core microprocessor is connected with the voltage output end of the power supply module; The input I/O end is connected; the LCD control end and the LCD data end of the LCD display module are respectively connected with the LCD control I/O end and the LCD data end of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor; The Bluetooth control terminal and the Bluetooth data terminal of the Bluetooth module are respectively connected with the Bluetooth control I/O terminal and the Bluetooth data terminal of the ARM Cortex core microprocessor through the Bluetooth interface of the core control module of the ARM Cortex core microprocessor; the Zigbee control of the Zigbee module The terminal and the Zigbee data terminal are respectively connected with the Zigbee control I/O terminal and the Zigbee data I/O terminal of the ARM Cortex core microprocessor through the Zigbee interface of the core control module of the ARM Cortex core microprocessor; the CAN data terminal of the CAN module is connected through The CAN interface of the core control module of the ARM Cortex core microprocessor is respectively connected to the CAN data terminal of the ARM Cortex core microprocessor; The interface is respectively connected with the RS485 data terminal and the RS485 control I/O terminal of the ARM Cortex core microprocessor; the Profibus control terminal, the Profibus data terminal and the Profibus address terminal of the Profibus module pass through the Profibus interface of the core control module of the ARM Cortex core microprocessor Connect to the Profibus control I/O port, Profibus data port, and Profibus address port of the ARM Cortex core microprocessor respectively; the serial port data port of the ARM Cortex core microprocessor is connected to the serial port data port of the RS232 serial port module, and the serial port The data terminal is connected to the serial port data terminal of the RS232 device; the EEPROM data terminal and EEPROM control terminal of the ARM Cortex core microprocessor are connected to the EEPROM data and EEPROM control terminal of the EEPROM memory; the SRAM data terminal and SRAM address of the ARM Cortex core microprocessor The terminal and the SRAM control I/O port are respectively connected to the SRAM data terminal, the SRAM address terminal and the SRAM control terminal of the SRAM memory.

本发明所述的ARM Cortex核微处理器为ARM Cortex-M4 32位微处理器或 ARM Cortex-M3 32位微处理器。 ARM Cortex core microprocessor of the present invention is ARM Cortex-M4 32 bit microprocessors or ARM Cortex-M3 32 bit microprocessors.

本发明所述的转换装置的具体连接结构为: The concrete connection structure of conversion device described in the present invention is:

电源模块的电压输出端VDD、VCC分别与ARM Cortex核微处理器的核心控制模块的电压输入端VCC_5、VCC_3.3连接;ARM Cortex核微处理器的核心控制模块的电压输出端VCC_3.3分别与LCD显示模块的电压输入端VCC_3.3、蓝牙模块的电压输入端VCC_3.3、Zigbee模块的电压输入端VCC_3.3、CAN模块的电压输入端VCC_3.3、RS485模块的电压输入端VCC_3.3、Profibus模块的电压输入端VCC_3.3连接;ARM Cortex核微处理器的核心控制模块的电压输出端VCC_5与LCD显示模块的电压输入端VCC_5连接;电源模块的接地端GND与ARM Cortex核微处理器的核心控制模块的接地端GND连接;ARM Cortex核微处理器的核心控制模块的接地端GND分别与LCD显示模块的接地端GND、蓝牙模块的接地端GND、Zigbee模块的接地端GND、CAN模块的接地端GND、RS485模块的接地端GND、Profibus模块的接地端GND连接; The voltage output terminals VDD and VCC of the power module are respectively connected to the voltage input terminals VCC_5 and VCC_3.3 of the core control module of the ARM Cortex core microprocessor; the voltage output terminals VCC_3.3 of the core control module of the ARM Cortex core microprocessor are respectively The voltage input terminal VCC_3.3 of the LCD display module, the voltage input terminal VCC_3.3 of the Bluetooth module, the voltage input terminal VCC_3.3 of the Zigbee module, the voltage input terminal VCC_3.3 of the CAN module, and the voltage input terminal VCC_3 of the RS485 module. 3. The voltage input terminal VCC_3.3 of the Profibus module is connected; the voltage output terminal VCC_5 of the core control module of the ARM Cortex core microprocessor is connected to the voltage input terminal VCC_5 of the LCD display module; the ground terminal GND of the power module is connected to the ARM Cortex core micro The ground terminal GND of the core control module of the processor is connected; the ground terminal GND of the core control module of the ARM Cortex core microprocessor is respectively connected with the ground terminal GND of the LCD display module, the ground terminal GND of the Bluetooth module, the ground terminal GND of the Zigbee module, The ground terminal GND of the CAN module, the ground terminal GND of the RS485 module, and the ground terminal GND of the Profibus module are connected;

ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的LCD控制I/O端口PD3、PD4、PD5分别与LCD显示模块的LCD指令控制端RS、LCD读写控制端R/W、LCD片选端CE连接;ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的LCD数据端PC[0:7]与LCD显示模块的LCD数据端DB[0:7]连接; The LCD control I/O ports PD3, PD4, and PD5 of the ARM Cortex core microprocessor in the core control module of the ARM Cortex core microprocessor are respectively connected with the LCD command control terminal RS, LCD read and write control terminal R/W, and the LCD display module. The LCD chip selection terminal CE is connected; the LCD data terminal PC[0:7] of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor is connected with the LCD data terminal DB[0:7] of the LCD display module;

ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的键盘输入I/O端口PC10、PC11、PC12、PC13、PC14分别与设置键盘模块的键盘输出端左移键K1、右移键K2、上页键K3、下页键K4、设定键K5连接;ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的复位输入端Reset与设置键盘模块的复位输出端Reset连接; The keyboard input I/O ports PC10, PC11, PC12, PC13, and PC14 of the core control module of the ARM Cortex core microprocessor of the ARM Cortex core microprocessor are respectively connected with the keyboard output terminals of the keyboard module, the left shift key K1 and the right shift key K2, page up key K3, page down key K4, and setting key K5 are connected; the reset input terminal Reset of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor is connected with the reset output terminal Reset of the keyboard module ;

ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的蓝牙数据RXD1、TXD1分别与蓝牙接口的蓝牙数据端RXD1、TXD1连接,蓝牙接口的蓝牙数据端RXD1、TXD1分别与蓝牙模块的蓝牙数据端RXD1、TXD1连接;ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的蓝牙控制I/O端口PD0、PD1分别与蓝牙接口的蓝牙控制I/O端口PD0、PD1连接,蓝牙接口的蓝牙控制I/O端口PD0、PD1分别与蓝牙模块的蓝牙流控制端CTS1、RTS1连接;ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的蓝牙复位I/O端口PC8与蓝牙接口的蓝牙复位I/O端口PC8连接,蓝牙接口的蓝牙复位I/O端口PC8与蓝牙模块的蓝牙复位控制端BL_RESET连接; The Bluetooth data RXD1 and TXD1 of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor are respectively connected with the Bluetooth data terminals RXD1 and TXD1 of the Bluetooth interface, and the Bluetooth data terminals RXD1 and TXD1 of the Bluetooth interface are respectively connected with the Bluetooth module. Bluetooth data terminals RXD1 and TXD1 are connected; the Bluetooth control I/O ports PD0 and PD1 of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor are respectively connected with the Bluetooth control I/O ports PD0 and PD1 of the Bluetooth interface , the Bluetooth control I/O ports PD0 and PD1 of the Bluetooth interface are respectively connected with the Bluetooth flow control terminals CTS1 and RTS1 of the Bluetooth module; the Bluetooth reset I/O of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor Port PC8 is connected with the Bluetooth reset I/O port PC8 of the Bluetooth interface, and the Bluetooth reset I/O port PC8 of the Bluetooth interface is connected with the Bluetooth reset control terminal BL_RESET of the Bluetooth module;

ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的Zigbee数据I/O端口PA4、PA5分别与Zigbee接口的Zigbee数据I/O端口PA4、PA5连接,Zigbee接口的Zigbee数据I/O端口PA4、PA5分别与Zigbee模块的Zigbee数据输出端SO1、Zigbee数据输入端SI1连接;ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15分别与Zigbee接口的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15连接,Zigbee接口的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15分别与Zigbee模块的Zigbee时钟输入端SCLK1、Zigbee片选控制端CSn1、Zigbee发送缓冲控制端FIFO、Zigbee接受缓冲控制端FIFOA、Zigbee复位端ZG_RESET连接; The Zigbee data I/O ports PA4 and PA5 of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor are connected with the Zigbee data I/O ports PA4 and PA5 of the Zigbee interface respectively, and the Zigbee data I/O ports of the Zigbee interface O port PA4, PA5 are respectively connected with Zigbee data output end SO1, Zigbee data input end SI1 of Zigbee module; Zigbee control I/O port PA2, PD2 of the ARM Cortex core microprocessor of ARM Cortex core microprocessor core control module , PD8, PD9, and PC15 are respectively connected to the Zigbee control I/O ports PA2, PD2, PD8, PD9, and PC15 of the Zigbee interface, and the Zigbee control I/O ports PA2, PD2, PD8, PD9, and PC15 of the Zigbee interface are respectively connected to the Zigbee module The Zigbee clock input terminal SCLK1, the Zigbee chip selection control terminal CSn1, the Zigbee sending buffer control terminal FIFO, the Zigbee receiving buffer control terminal FIFOA, and the Zigbee reset terminal ZG_RESET are connected;

ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的CAN数据端CANTX、CANRX分别与CAN接口的CAN数据端CANTX、CANRX连接,CAN接口的CAN数据端CANTX、CANRX分别与CAN模块的CAN数据端CANRX、CANTX连接; The CAN data terminals CANTX and CANRX of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor are respectively connected with the CAN data terminals CANTX and CANRX of the CAN interface, and the CAN data terminals CANTX and CANRX of the CAN interface are respectively connected with the CAN module The CAN data terminal CANRX and CANTX are connected;

ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的RS485数据端RXD2、TXD2分别与RS485接口的RS485数据端RXD2、TXD2连接,RS485接口的RS485数据端RXD2、TXD2分别与RS485模块的RS485数据端RXD2、TXD2连接;ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的RS485控制I/O端口PB13、PB14分别与RS485接口的RS485控制I/O端口PB13、PB14连接,RS485接口的RS485控制I/O端口PB13、PB14分别与RS485模块的RS485接收使能端RE2、RS485发送使能端TE2连接; The RS485 data terminals RXD2 and TXD2 of the ARM Cortex core microprocessor in the core control module of the ARM Cortex core microprocessor are respectively connected to the RS485 data terminals RXD2 and TXD2 of the RS485 interface, and the RS485 data terminals RXD2 and TXD2 of the RS485 interface are respectively connected to the RS485 module The RS485 data terminal RXD2, TXD2 connection; the RS485 control I/O port PB13, PB14 of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor and the RS485 control I/O port PB13, PB14 of the RS485 interface respectively Connection, the RS485 control I/O ports PB13 and PB14 of the RS485 interface are respectively connected to the RS485 receiving enabling end RE2 and RS485 sending enabling end TE2 of the RS485 module;

ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的数据端/地址端PIE[0:7]、地址端PIE[8:15]分别与Profibus接口的数据端/地址端PIE[0:7]、地址端PIE[8:15]连接,Profibus接口的数据端/地址端PIE[0:7]、地址端PIE[8:15]分别与Profibus模块的Profibus数据端DB[0:7]、地址端AB[8:15]连接;ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0分别与Profibus接口的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0连接,Profibus接口的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0分别与Profibus模块的Profibus读控制端RD3、Profibus写控制端WR3、地址锁存控制端ALE3、 Profibus中断输出端XINT、Profibus复位端PF_RESET连接。 The data end/address end PIE[0:7] and the address end PIE[8:15] of the ARM Cortex core microprocessor in the core control module of the ARM Cortex core microprocessor are respectively connected with the data end/address end PIE[0:15] of the Profibus interface 0:7] and address terminal PIE[8:15] are connected, the data terminal/address terminal PIE[0:7] and address terminal PIE[8:15] of the Profibus interface are connected with the Profibus data terminal DB[0:15] of the Profibus module respectively. 7], the address terminal AB[8:15] is connected; the Profibus control signal I/O port PD15, PD14, PD13, PE4, PA0 of the core control module of the ARM Cortex core microprocessor of the ARM Cortex core microprocessor communicate with Profibus respectively The Profibus control signal I/O ports PD15, PD14, PD13, PE4, and PA0 of the interface are connected, and the Profibus control signal I/O ports PD15, PD14, PD13, PE4, and PA0 of the Profibus interface are respectively connected to the Profibus reading control terminals RD3 and RD3 of the Profibus module. Profibus write control terminal WR3, address latch control terminal ALE3, Profibus interrupt output terminal XINT, and Profibus reset terminal PF_RESET are connected.

ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的串口数据端TXD0、RXD0分别与RS232串口模块的串口数据端TXD0、RXD0连接;RS232串口模块的数据端TXD02、RXD02分别与RS232设备的串口数据端连接;ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的接地端GND与RS232串口模块的的接地端GND连接,RS232串口模块的接地端GND与RS232设备的接地端GND连接。 The serial data ports TXD0 and RXD0 of the ARM Cortex core microprocessor in the core control module of the ARM Cortex core microprocessor are respectively connected to the serial data ports TXD0 and RXD0 of the RS232 serial port module; the data ports TXD02 and RXD02 of the RS232 serial port module are connected to the RS232 serial port module respectively The serial port data terminal connection of the device; the ground terminal GND of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor is connected with the ground terminal GND of the RS232 serial port module, and the ground terminal GND of the RS232 serial port module is connected with the ground terminal GND of the RS232 device Connect to the ground terminal GND.

ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的I2C端口SCL、SDA分别与EEPROM存储器的I2C端口SCL、SDA连接。 The I2C ports SCL and SDA of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor are respectively connected with the I2C ports SCL and SDA of the EEPROM memory.

ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的数据/地址端PIE[0:7]分别与锁存器的数据输入端D[0:7]、SRAM存储器的数据端DB[0:7]连接;锁存器的数据输出端Q[0:7]与SRAM存储器的地址端AB[0:7]连接;ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的地址端PIE[8:15]与SRAM存储器的地址端AB[8:15]连接;ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的地址锁存I/O控制端PJ6与锁存器的地址锁存控制端LE连接;ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的SRAM控制I/O端口PH6、PH7、PJ4、PJ5分别与SRAM存储器的片使能控制端SCE1、片使能控制端SCE2、输出使能控制端SOE、写使能控制端SWE连接。 The data/address terminal PIE[0:7] of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor is respectively connected with the data input terminal D[0:7] of the latch and the data terminal DB of the SRAM memory [0:7] is connected; the data output terminal Q[0:7] of the latch is connected with the address terminal AB[0:7] of the SRAM memory; the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor The address terminal PIE[8:15] of the device is connected with the address terminal AB[8:15] of the SRAM memory; the address latch I/O control terminal of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor PJ6 is connected with the address latch control terminal LE of the latch; the SRAM control I/O ports PH6, PH7, PJ4, and PJ5 of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor are respectively connected with the SRAM memory The chip enable control terminal SCE1, the chip enable control terminal SCE2, the output enable control terminal SOE, and the write enable control terminal SWE are connected.

本发明所述的蓝牙模块的结构为: The structure of bluetooth module of the present invention is:

蓝牙模块的蓝牙控制器的蓝牙数据端RXD1、TXD1分别与ARM Cortex核微处理器的核心控制模块的蓝牙接口的蓝牙数据端RXD1、TXD1连接,蓝牙接口的蓝牙数据端RXD1、TXD1分别与ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的蓝牙数据端RXD1、TXD1连接;蓝牙模块的蓝牙控制器的蓝牙流控制端CTS1、RTS1分别与ARM Cortex核微处理器的核心控制模块的蓝牙接口的蓝牙控制I/O端口PD0、PD1连接,蓝牙接口的蓝牙控制I/O端口PD0、PD1分别与ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的蓝牙控制I/O端口PD0、PD1连接;蓝牙模块的蓝牙控制器的蓝牙复位控制端BL_RESET与ARM Cortex核微处理器的核心控制模块的蓝牙接口的蓝牙复位I/O端口PC8连接,蓝牙接口的蓝牙复位I/O端口PC8与ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的蓝牙复位I/O端口PC8连接;蓝牙模块的天线输入端RF_IN、天线输出端RF_OUT与天线连接;蓝牙模块的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块的电压输出端VCC_3.3连接;蓝牙模块的接地端GND 与ARM Cortex核微处理器的核心控制模块的接地端GND连接。 The Bluetooth data terminals RXD1 and TXD1 of the Bluetooth controller of the Bluetooth module are respectively connected with the Bluetooth data terminals RXD1 and TXD1 of the Bluetooth interface of the core control module of the ARM Cortex core microprocessor, and the Bluetooth data terminals RXD1 and TXD1 of the Bluetooth interface are respectively connected with the ARM Cortex The Bluetooth data terminals RXD1 and TXD1 of the ARM Cortex core microprocessor of the core control module of the core microprocessor are connected; The Bluetooth control I/O ports PD0 and PD1 of the Bluetooth interface are connected, and the Bluetooth control I/O ports PD0 and PD1 of the Bluetooth interface are respectively connected with the Bluetooth control I of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor. /O ports PD0, PD1 are connected; the Bluetooth reset control terminal BL_RESET of the Bluetooth controller of the Bluetooth module is connected with the Bluetooth reset I/O port PC8 of the Bluetooth interface of the core control module of the ARM Cortex core microprocessor, and the Bluetooth reset I of the Bluetooth interface /O port PC8 is connected with the Bluetooth reset I/O port PC8 of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor; the antenna input terminal RF_IN of the Bluetooth module, the antenna output terminal RF_OUT are connected with the antenna; the Bluetooth module The voltage input terminal VCC_3.3 of the ARM Cortex core microprocessor is connected to the voltage output terminal VCC_3.3 of the core control module; the ground terminal GND of the Bluetooth module is connected to the ground terminal GND of the core control module of the ARM Cortex core microprocessor.

本发明所述的Zigbee模块的结构为: The structure of the Zigbee module of the present invention is:

Zigbee模块的Zigbee控制器的Zigbee数据输出端SO1、Zigbee数据输入端SI1分别与ARM Cortex核微处理器的核心控制模块的Zigbee接口的Zigbee数据I/O端口PA4、PA5连接,Zigbee接口的Zigbee数据I/O端口PA4、PA5分别与ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的Zigbee数据I/O端口PA4、PA5连接;Zigbee模块的Zigbee控制器的Zigbee时钟输入端SCLK1、Zigbee片选控制端CSn1、Zigbee发送缓冲控制端FIFO、Zigbee接受缓冲控制端FIFOA、Zigbee复位端ZG_RESET分别与ARM Cortex核微处理器的核心控制模块的Zigbee接口的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15连接,Zigbee接口的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15分别与ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15连接;Zigbee模块的天线输入端RF_IN、天线输出端RF_OUT与天线连接;Zigbee模块的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块的电压输出端VCC_3.3连接;Zigbee模块的接地端GND 与ARM Cortex核微处理器的核心控制模块的接地端GND连接。 The Zigbee data output terminal SO1 and the Zigbee data input terminal SI1 of the Zigbee controller of the Zigbee module are respectively connected with the Zigbee data I/O ports PA4 and PA5 of the Zigbee interface of the core control module of the ARM Cortex core microprocessor, and the Zigbee data of the Zigbee interface I/O port PA4, PA5 are respectively connected with the Zigbee data I/O port PA4, PA5 of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor; the Zigbee clock input terminal SCLK1 of the Zigbee controller of the Zigbee module , Zigbee chip select control terminal CSn1, Zigbee send buffer control terminal FIFO, Zigbee receive buffer control terminal FIFOA, Zigbee reset terminal ZG_RESET respectively with the Zigbee control I/O port PA2 of the Zigbee interface of the core control module of ARM Cortex core microprocessor PD2, PD8, PD9, PC15 are connected, the Zigbee control I/O ports PA2, PD2, PD8, PD9, PC15 of Zigbee interface are respectively connected with the Zigbee control I of the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor. /O port PA2, PD2, PD8, PD9, PC15 are connected; the antenna input terminal RF_IN and the antenna output terminal RF_OUT of the Zigbee module are connected to the antenna; the voltage input terminal VCC_3.3 of the Zigbee module is connected to the core control module of the ARM Cortex core microprocessor The voltage output terminal VCC_3.3 is connected; the ground terminal GND of the Zigbee module is connected to the ground terminal GND of the core control module of the ARM Cortex core microprocessor.

本发明所述的CAN模块的结构为: The structure of the CAN module of the present invention is:

CAN模块的CAN驱动器的CAN数据端 CANTX、CANRX分别与ARM Cortex核微处理器的核心控制模块的CAN接口的CAN数据端CANTX、CANRX连接,CAN接口的CAN数据端CANTX、CANRX分别与ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的CAN数据端CANTX、CANRX连接;CAN模块的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块的电压输出端VCC_3.3连接;CAN模块的接地端GND 与ARM Cortex核微处理器的核心控制模块的接地端GND连接。 The CAN data terminals CANTX and CANRX of the CAN driver of the CAN module are respectively connected to the CAN data terminals CANTX and CANRX of the CAN interface of the core control module of the ARM Cortex core microprocessor, and the CAN data terminals CANTX and CANRX of the CAN interface are respectively connected to the ARM Cortex core The CAN data terminals CANTX and CANRX of the ARM Cortex core microprocessor of the core control module of the microprocessor are connected; the voltage input terminal VCC_3.3 of the CAN module is connected with the voltage output terminal VCC_3.3 of the core control module of the ARM Cortex core microprocessor Connection; the ground terminal GND of the CAN module is connected to the ground terminal GND of the core control module of the ARM Cortex core microprocessor.

本发明所述的RS485模块的结构为: The structure of the RS485 module of the present invention is:

RS485模块的RS485驱动器的RS485数据端TXD2、RXD2分别与ARM Cortex核微处理器的核心控制模块的RS485接口的RS485数据端RXD2、TXD2连接,RS485接口的RS485数据端RXD2、TXD2分别与ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的RS485数据端RXD2、TXD2连接;RS485模块的RS485驱动器的RS485接收使能端RE2、RS485发送使能端TE2 分别与ARM Cortex核微处理器的核心控制模块的RS485接口的RS485控制I/O端口PB13、PB14连接,RS485接口的RS485控制I/O端口PB13、PB14分别与ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的RS485控制I/O端口PB13、PB14连接;RS485模块的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块的电压输出端VCC_3.3连接;RS485模块的接地端GND 与ARM Cortex核微处理器的核心控制模块的接地端GND连接。 The RS485 data terminals TXD2 and RXD2 of the RS485 driver of the RS485 module are respectively connected to the RS485 data terminals RXD2 and TXD2 of the RS485 interface of the core control module of the ARM Cortex core microprocessor, and the RS485 data terminals RXD2 and TXD2 of the RS485 interface are respectively connected to the ARM Cortex core The RS485 data terminals RXD2 and TXD2 of the ARM Cortex core microprocessor of the core control module of the microprocessor are connected; The RS485 control I/O ports PB13 and PB14 of the RS485 interface of the core control module are connected, and the RS485 control I/O ports PB13 and PB14 of the RS485 interface are respectively connected with the ARM Cortex core microprocessor of the core control module of the ARM Cortex core microprocessor The RS485 control I/O ports PB13 and PB14 are connected; the voltage input terminal VCC_3.3 of the RS485 module is connected to the voltage output terminal VCC_3.3 of the core control module of the ARM Cortex core microprocessor; the ground terminal GND of the RS485 module is connected to the ARM Cortex The ground terminal GND of the core control module of the core microprocessor is connected.

本发明所述的Profibus模块的结构为: The structure of the Profibus module of the present invention is:

Profibus模块的Profibus控制器的Profibus数据端DB[0:7]、地址端AB[8:15]分别与ARM Cortex核微处理器的核心控制模块的Profibus接口的Profibus数据端/地址端PIE[0:7]、地址端PIE[8:15]连接,Profibus接口的数据端/地址端PIE[0:7]、地址端PIE[8:15]分别与ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的Profibus数据端/地址端PIE[0:7]、地址端PIE[8:15]连接;Profibus模块的Profibus控制器的Profibus读控制端RD3、Profibus写控制端WR3、Profibus地址锁存控制端ALE3、Profibus中断输出端XINT、Profibus复位端PF_RESET分别与ARM Cortex核微处理器的核心控制模块的Profibus接口的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0连接,Profibus接口的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0分别与ARM Cortex核微处理器的核心控制模块的ARM Cortex核微处理器的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0连接;Profibus模块的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块的电压输出端VCC_3.3连接;Profibus模块的接地端GND 与ARM Cortex核微处理器的核心控制模块的接地端GND连接。 The Profibus data terminal DB[0:7] and the address terminal AB[8:15] of the Profibus controller of the Profibus module are respectively connected with the Profibus data terminal/address terminal PIE[0 of the Profibus interface of the core control module of the ARM Cortex core microprocessor. :7], address terminal PIE[8:15] connection, the data terminal/address terminal PIE[0:7], address terminal PIE[8:15] of the Profibus interface are respectively connected with the core control module of the ARM Cortex core microprocessor The Profibus data terminal/address terminal PIE[0:7] and address terminal PIE[8:15] of the ARM Cortex core microprocessor are connected; the Profibus read control terminal RD3 of the Profibus controller of the Profibus module, the Profibus write control terminal WR3, Profibus The address latch control terminal ALE3, the Profibus interrupt output terminal XINT, and the Profibus reset terminal PF_RESET are respectively connected to the Profibus control signal I/O ports PD15, PD14, PD13, PE4, and PA0 of the Profibus interface of the core control module of the ARM Cortex core microprocessor , the Profibus control signal I/O ports PD15, PD14, PD13, PE4, PA0 of the Profibus interface are respectively connected with the Profibus control signal I/O ports PD15, PD14 of the ARM Cortex core microprocessor core control module of the ARM Cortex core microprocessor , PD13, PE4, PA0 are connected; the voltage input terminal VCC_3.3 of the Profibus module is connected with the voltage output terminal VCC_3.3 of the core control module of the ARM Cortex core microprocessor; the ground terminal GND of the Profibus module is connected with the ARM Cortex core microprocessor Connect to the ground terminal GND of the core control module.

一种模块式多数据转换装置的转换方法包括以下步骤: A conversion method of a modular multi-data conversion device comprises the following steps:

1)ARM Cortex核微处理器的核心控制模块上电初始化,完成模块式多数据转换装置的初始化程序和数据的加载,并将SRAM存储器的存储空间划分为:蓝牙、Zigbee、CAN、RS485、Profibus、RS232等数据通讯收发通道的缓存区; 1) The core control module of the ARM Cortex core microprocessor is powered on and initialized, the initialization program and data loading of the modular multi-data conversion device are completed, and the storage space of the SRAM memory is divided into: Bluetooth, Zigbee, CAN, RS485, Profibus , RS232 and other data communication transceiver channels buffer area;

2)用户通过设置键盘模块,对模块式多数据转换装置的各通讯模块的硬件参数进行配置,并执行相应通讯子程序的使能或屏蔽操作; 2) The user configures the hardware parameters of each communication module of the modular multi-data conversion device by setting the keyboard module, and executes the enabling or shielding operation of the corresponding communication subroutine;

3)将各通讯模块的配置参数存储在EEPROM存储器内; 3) Store the configuration parameters of each communication module in the EEPROM memory;

4)执行使能通讯模块的初始化子程序,完成其硬件配置参数的设置; 4) Execute the initialization subroutine that enables the communication module to complete the setting of its hardware configuration parameters;

5)模块式多数据转换装置的数据转换与控制程序由数据帧的中断接收子程序、多数据转换处理子程序、以及轮询数据转发传输子程序等三部分组成,其中中断接收子程序负责对蓝牙模块、Zigbee模块、CAN模块、RS485模块、Profibus模块、RS232等通讯模块的数据帧进行接收,根据ARM Cortex核微处理器中各模块的中断的优先等级,实现相应各通讯模块的接收数据的处理;多数据转换处理子程序负责对接收到的数据帧按照目的地地址进行检测,并按照发送的地址,依次将接受的数据帧存储到SRAM存储器各相应的数据通讯发送通道的缓存区内;轮询数据转发传输子程序则负责对SRAM存储器内的各个数据通讯发送通道的缓存区的头、尾指针是否相等进行检测,如果数据通讯发送通道的缓存区的头、尾指针不相等,依次将数据通讯发送通道的缓存区中的数据发送到各通讯模块的发送缓冲区内。 5) The data conversion and control program of the modular multi-data conversion device consists of three parts: the interrupt receiving subroutine of the data frame, the multi-data conversion processing subroutine, and the polling data forwarding and transmission subroutine, among which the interrupt receiving subroutine is responsible for Bluetooth module, Zigbee module, CAN module, RS485 module, Profibus module, RS232 and other communication modules to receive data frames, according to the interrupt priority of each module in the ARM Cortex core microprocessor, to achieve the corresponding data received by each communication module Processing; the multi-data conversion processing subroutine is responsible for detecting the received data frame according to the destination address, and according to the address sent, the received data frame is stored in the buffer area of each corresponding data communication transmission channel of the SRAM memory in turn; The polling data forwarding transmission subroutine is responsible for detecting whether the head and tail pointers of the buffer areas of each data communication transmission channel in the SRAM memory are equal. If the head and tail pointers of the buffer areas of the data communication transmission channels are not equal, the The data in the buffer area of the data communication sending channel is sent to the sending buffer of each communication module.

由于采用上述技术方案,本发明采用在硬件上具有可裁剪性的模块式安装方式,同时利用ARM Cortex核微处理器高速的处理特性,很方便地实现多种通讯数据间的数据转换和数据传输功能。因此,本发明具有处理响应速度快、体积小、较高的灵活性、较强的环境适应性等优点。 Due to the adoption of the above technical scheme, the present invention adopts a modular installation method with tailorability in hardware, and utilizes the high-speed processing characteristics of the ARM Cortex core microprocessor to conveniently realize data conversion and data transmission among various communication data Function. Therefore, the present invention has the advantages of fast processing response speed, small volume, high flexibility, strong environmental adaptability and the like.

附图说明 Description of drawings

图1是本发明模块式多数据转换装置的结构示意图; Fig. 1 is a schematic structural view of a modular multi-data conversion device of the present invention;

图2是本发明ARM Cortex核微处理器的核心控制模块的电路示意图; Fig. 2 is the schematic circuit diagram of the core control module of ARM Cortex core microprocessor of the present invention;

图3是本发明蓝牙模块的电路示意图; Fig. 3 is the circuit diagram of bluetooth module of the present invention;

图4是本发明Zigbee模块的电路示意图; Fig. 4 is the schematic circuit diagram of Zigbee module of the present invention;

图5是本发明CAN模块的电路示意图; Fig. 5 is the circuit diagram of CAN module of the present invention;

图6是本发明RS485模块的电路示意图; Fig. 6 is the circuit diagram of RS485 module of the present invention;

图7是本发明Profibus模块的电路示意图; Fig. 7 is the circuit diagram of Profibus module of the present invention;

图8是模块式多数据转换装置的主程序流程图。 Fig. 8 is a flow chart of the main program of the modular multi-data conversion device.

图9是中断接收子程序流程图; Fig. 9 is a flow chart of the interrupt receiving subroutine;

图10是多数据处理子程序流程图; Fig. 10 is a multi-data processing subroutine flowchart;

图11是轮询数据转发子程序流程图; Fig. 11 is a polling data forwarding subroutine flow chart;

图中:1、核心控制模块、2、蓝牙模块,3、Zigbee模块,4、CAN模块,5、RS485模块,6、Profibus模块。 In the figure: 1. Core control module, 2. Bluetooth module, 3. Zigbee module, 4. CAN module, 5. RS485 module, 6. Profibus module.

具体实施方式 Detailed ways

下面结合实施例对本发明作进一步的描述: Below in conjunction with embodiment the present invention will be further described:

    本实施例如图1所示,一种模块式多数据转转装置是由基于ARM Cortex核微处理器的核心控制模块1、电源模块、设置键盘模块、LCD显示模块和通讯模块组成,所述的通迅模块为蓝牙模块2、Zigbee模块3、CAN模块4、RS485模块5和Profibus模块6中的两种或多种模块,该转换装置可以根据需要在ARM Cortex核微处理器的核心控制模块1的通讯接口上接插可选的通讯模块,很方便地实现多种通讯数据间的数据格式转换和数据传输的功能。其中: Present embodiment such as shown in Figure 1, a kind of modular multi-data transfer device is made up of core control module 1, power supply module, setting keyboard module, LCD display module and communication module based on ARM Cortex nuclear microprocessor, described The communication module is two or more modules in Bluetooth module 2, Zigbee module 3, CAN module 4, RS485 module 5 and Profibus module 6. An optional communication module can be plugged into the communication interface, which can conveniently realize the functions of data format conversion and data transmission among various communication data. in:

ARM Cortex核微处理器的核心控制模块1的电压输入端与电源模块的电压输出端连接;设置键盘模块的键盘输出端与ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的键盘输入I/O端连接;LCD显示模块的LCD控制端、LCD数据端分别与ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的LCD控制I/O端、LCD数据端连接;蓝牙模块2的蓝牙控制端和蓝牙数据端通过ARM Cortex核微处理器的核心控制模块1的蓝牙接口分别与ARM Cortex核微处理器的蓝牙控制I/O端和蓝牙数据端连接;Zigbee模块3的Zigbee控制端和Zigbee数据端通过ARM Cortex核微处理器的核心控制模块1的Zigbee接口分别与ARM Cortex核微处理器的Zigbee控制I/O端和Zigbee数据I/O端连接;CAN模块4的CAN数据端通过ARM Cortex核微处理器的核心控制模块1的CAN接口分别与ARM Cortex核微处理器的CAN数据端连接;RS485模块5的RS485数据端和RS485控制端通过ARM Cortex核微处理器的核心控制模块1的RS485接口分别与ARM Cortex核微处理器的RS485数据端和RS485控制I/O端连接;Profibus模块6的Profibus控制端和Profibus数据端、Profibus地址端通过ARM Cortex核微处理器的核心控制模块1的Profibus接口分别与ARM Cortex核微处理器的Profibus控制I/O端口、Profibus数据端、Profibus地址端连接;ARM Cortex核微处理器的串口数据端与RS232串口模块的串口数据端连接,RS232串口模块的串口数据端与RS232设备的串口数据端连接;ARM Cortex核微处理器的EEPROM数据端、EEPROM控制端与EEPROM存储器的EEPROM数据、EEPROM控制端连接;ARM Cortex核微处理器的SRAM数据端、SRAM地址端、SRAM控制I/O端口分别与SRAM存储器的SRAM数据、SRAM地址端、SRAM控制端连接。 The voltage input end of the core control module 1 of the ARM Cortex core microprocessor is connected with the voltage output end of the power supply module; The keyboard input I/O terminal of the LCD display module is connected with the LCD control terminal and the LCD data terminal of the LCD display module respectively with the LCD control I/O terminal and the LCD data terminal of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor. The bluetooth control end and the bluetooth data end of the bluetooth module 2 are respectively connected with the bluetooth control I/O end and the bluetooth data end of the ARM Cortex core microprocessor by the bluetooth interface of the core control module 1 of the ARM Cortex core microprocessor; The Zigbee control end and the Zigbee data end of the Zigbee module 3 are respectively connected with the Zigbee control I/O end and the Zigbee data I/O end of the ARM Cortex core microprocessor through the Zigbee interface of the core control module 1 of the ARM Cortex core microprocessor; The CAN data end of CAN module 4 is connected to the CAN data end of the ARM Cortex core microprocessor through the CAN interface of the core control module 1 of the ARM Cortex core microprocessor; the RS485 data end and RS485 control end of the RS485 module 5 are connected through the ARM Cortex core microprocessor. The RS485 interface of the core control module 1 of the nuclear microprocessor is connected with the RS485 data terminal and the RS485 control I/O terminal of the ARM Cortex nuclear microprocessor respectively; The Profibus interface of the core control module 1 of the Cortex core microprocessor is respectively connected with the Profibus control I/O port, the Profibus data terminal and the Profibus address terminal of the ARM Cortex core microprocessor; the serial data terminal of the ARM Cortex core microprocessor is connected with the RS232 The serial port data port of the serial port module is connected, the serial port data port of the RS232 serial port module is connected with the serial port data port of the RS232 device; the EEPROM data port and the EEPROM control port of the ARM Cortex core microprocessor are connected with the EEPROM data and the EEPROM control port of the EEPROM memory; The SRAM data terminal, SRAM address terminal, and SRAM control I/O port of the ARM Cortex core microprocessor are respectively connected to the SRAM data, SRAM address terminal, and SRAM control terminal of the SRAM memory.

本装置中,ARM Cortex核微处理器的核心控制模块1如图2所示, In this device, the core control module 1 of the ARM Cortex core microprocessor is as shown in Figure 2,

电源模块的电压输出端VDD、VCC分别与ARM Cortex核微处理器的核心控制模块1的电压输入端VCC_5、VCC_3.3连接;ARM Cortex核微处理器的核心控制模块1的电压输出端VCC_3.3分别与LCD显示模块的电压输入端VCC_3.3、蓝牙模块2的电压输入端VCC_3.3、Zigbee模块3的电压输入端VCC_3.3、CAN模块4的电压输入端VCC_3.3、RS485模块5的电压输入端VCC_3.3、Profibus模块6的电压输入端VCC_3.3连接;ARM Cortex核微处理器的核心控制模块1的电压输出端VCC_5与LCD显示模块的电压输入端VCC_5连接;电源模块的接地端GND与ARM Cortex核微处理器的核心控制模块1的接地端GND连接;ARM Cortex核微处理器的核心控制模块1的接地端GND分别与LCD显示模块的接地端GND、蓝牙模块2的接地端GND、Zigbee模块3的接地端GND、CAN模块4的接地端GND、RS485模块5的接地端GND、Profibus模块6的接地端GND连接; The voltage output terminals VDD and VCC of the power module are respectively connected to the voltage input terminals VCC_5 and VCC_3.3 of the core control module 1 of the ARM Cortex core microprocessor; the voltage output terminal VCC_3 of the core control module 1 of the ARM Cortex core microprocessor. 3 are respectively connected with the voltage input terminal VCC_3.3 of the LCD display module, the voltage input terminal VCC_3.3 of the Bluetooth module 2, the voltage input terminal VCC_3.3 of the Zigbee module 3, the voltage input terminal VCC_3.3 of the CAN module 4, and the RS485 module 5 The voltage input terminal VCC_3.3 of the Profibus module 6 is connected to the voltage input terminal VCC_3.3; the voltage output terminal VCC_5 of the core control module 1 of the ARM Cortex core microprocessor is connected to the voltage input terminal VCC_5 of the LCD display module; The ground terminal GND is connected to the ground terminal GND of the core control module 1 of the ARM Cortex core microprocessor; the ground terminal GND of the core control module 1 of the ARM Cortex core microprocessor is connected to the ground terminal GND of the LCD display module and the Bluetooth module 2 respectively. Connect the ground terminal GND, the ground terminal GND of Zigbee module 3, the ground terminal GND of CAN module 4, the ground terminal GND of RS485 module 5, and the ground terminal GND of Profibus module 6;

ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的LCD控制I/O端口PD3、PD4、PD5分别与LCD显示模块的LCD指令控制端RS、LCD读写控制端R/W、LCD片选端CE连接;ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的LCD数据端PC[0:7]与LCD显示模块的LCD数据端DB[0:7]连接; The LCD control I/O ports PD3, PD4, and PD5 of the ARM Cortex core microprocessor in the core control module 1 of the ARM Cortex core microprocessor are respectively connected with the LCD command control terminal RS and the LCD read and write control terminal R/W of the LCD display module , LCD chip selection terminal CE connection; the LCD data terminal PC[0:7] of the ARM Cortex core microprocessor core control module 1 of the ARM Cortex core microprocessor and the LCD data terminal DB[0:7] of the LCD display module connect;

ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的键盘输入I/O端口PC10、PC11、PC12、PC13、PC14分别与设置键盘模块的键盘输出端左移键K1、右移键K2、上页键K3、下页键K4、设定键K5连接;ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的复位输入端Reset与设置键盘模块的复位输出端Reset连接; The keyboard input I/O ports PC10, PC11, PC12, PC13, and PC14 of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor are respectively connected with the keyboard output terminals of the keyboard module to move left and right. Key K2, page up key K3, page down key K4, and setting key K5 are connected; the reset input terminal Reset of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor and the reset output terminal of the keyboard module are set Reset connection;

ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的蓝牙数据RXD1、TXD1分别与蓝牙接口的蓝牙数据端RXD1、TXD1连接,蓝牙接口的蓝牙数据端RXD1、TXD1分别与蓝牙模块2的蓝牙数据端RXD1、TXD1连接;ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的蓝牙控制I/O端口PD0、PD1分别与蓝牙接口的蓝牙控制I/O端口PD0、PD1连接,蓝牙接口的蓝牙控制I/O端口PD0、PD1分别与蓝牙模块2的蓝牙流控制端CTS1、RTS1连接;ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的蓝牙复位I/O端口PC8与蓝牙接口的蓝牙复位I/O端口PC8连接,蓝牙接口的蓝牙复位I/O端口PC8与蓝牙模块2的蓝牙复位控制端BL_RESET连接; The Bluetooth data RXD1 and TXD1 of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor are respectively connected with the Bluetooth data terminals RXD1 and TXD1 of the Bluetooth interface, and the Bluetooth data terminals RXD1 and TXD1 of the Bluetooth interface are respectively connected with the Bluetooth module The bluetooth data terminal RXD1, TXD1 of 2 are connected; the bluetooth control I/O port PD0, PD1 of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor is respectively connected with the bluetooth control I/O port PD0 of the bluetooth interface , PD1 connection, the bluetooth control I/O ports PD0, PD1 of the bluetooth interface are respectively connected with the bluetooth stream control terminal CTS1, RTS1 of the bluetooth module 2; The Bluetooth reset I/O port PC8 is connected with the Bluetooth reset I/O port PC8 of the Bluetooth interface, and the Bluetooth reset I/O port PC8 of the Bluetooth interface is connected with the Bluetooth reset control terminal BL_RESET of the Bluetooth module 2;

ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的Zigbee数据I/O端口PA4、PA5分别与Zigbee接口的Zigbee数据I/O端口PA4、PA5连接,Zigbee接口的Zigbee数据I/O端口PA4、PA5分别与Zigbee模块3的Zigbee数据输出端SO1、Zigbee数据输入端SI1连接;ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15分别与Zigbee接口的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15连接,Zigbee接口的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15分别与Zigbee模块3的Zigbee时钟输入端SCLK1、Zigbee片选控制端CSn1、Zigbee发送缓冲控制端FIFO、Zigbee接受缓冲控制端FIFOA、Zigbee复位端ZG_RESET连接; The Zigbee data I/O ports PA4 and PA5 of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor are connected with the Zigbee data I/O ports PA4 and PA5 of the Zigbee interface respectively, and the Zigbee data I of the Zigbee interface /O port PA4, PA5 are connected with Zigbee data output end SO1, Zigbee data input end SI1 of Zigbee module 3 respectively; PA2, PD2, PD8, PD9, and PC15 are respectively connected to the Zigbee control I/O ports PA2, PD2, PD8, PD9, and PC15 of the Zigbee interface, and the Zigbee control I/O ports PA2, PD2, PD8, PD9, and PC15 of the Zigbee interface are respectively Connect with Zigbee clock input terminal SCLK1 of Zigbee module 3, Zigbee chip select control terminal CSn1, Zigbee send buffer control terminal FIFO, Zigbee receive buffer control terminal FIFOA, Zigbee reset terminal ZG_RESET;

ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的CAN数据端CANTX、CANRX分别与CAN接口的CAN数据端CANTX、CANRX连接,CAN接口的CAN数据端CANTX、CANRX分别与CAN模块4的CAN数据端CANRX、CANTX连接; The CAN data terminals CANTX and CANRX of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor are respectively connected with the CAN data terminals CANTX and CANRX of the CAN interface, and the CAN data terminals CANTX and CANRX of the CAN interface are connected with the CAN data terminals respectively. The CAN data terminal CANRX and CANTX of module 4 are connected;

ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的RS485数据端RXD2、TXD2分别与RS485接口的RS485数据端RXD2、TXD2连接,RS485接口的RS485数据端RXD2、TXD2分别与RS485模块5的RS485数据端RXD2、TXD2连接;ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的RS485控制I/O端口PB13、PB14分别与RS485接口的RS485控制I/O端口PB13、PB14连接,RS485接口的RS485控制I/O端口PB13、PB14分别与RS485模块5的RS485接收使能端RE2、RS485发送使能端TE2连接; The RS485 data terminals RXD2 and TXD2 of the ARM Cortex core microprocessor in the core control module 1 of the ARM Cortex core microprocessor are respectively connected to the RS485 data terminals RXD2 and TXD2 of the RS485 interface, and the RS485 data terminals RXD2 and TXD2 of the RS485 interface are respectively connected to the RS485 The RS485 data terminal RXD2 and TXD2 of module 5 are connected; the core control of the ARM Cortex core microprocessor of the ARM Cortex core microprocessor. PB13 and PB14 are connected, and the RS485 control I/O ports PB13 and PB14 of the RS485 interface are respectively connected to the RS485 receiving enabling end RE2 and RS485 sending enabling end TE2 of the RS485 module 5;

ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的数据端/地址端PIE[0:7]、地址端PIE[8:15]分别与Profibus接口的数据端/地址端PIE[0:7]、地址端PIE[8:15]连接,Profibus接口的数据端/地址端PIE[0:7]、地址端PIE[8:15]分别与Profibus模块6的Profibus数据端DB[0:7]、地址端AB[8:15]连接;ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0分别与Profibus接口的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0连接,Profibus接口的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0分别与Profibus模块6的Profibus读控制端RD3、Profibus写控制端WR3、地址锁存控制端ALE3、 Profibus中断输出端XINT、Profibus复位端PF_RESET连接。 The data terminal/address terminal PIE[0:7] and the address terminal PIE[8:15] of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor are respectively connected with the data terminal/address terminal PIE of the Profibus interface [0:7], address terminal PIE[8:15] are connected, the data terminal/address terminal PIE[0:7] and address terminal PIE[8:15] of the Profibus interface are connected with the Profibus data terminal DB[ of Profibus module 6 respectively 0:7], address terminal AB[8:15] connection; Profibus control signal I/O ports PD15, PD14, PD13, PE4, PA0 of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor Connect with the Profibus control signal I/O ports PD15, PD14, PD13, PE4, and PA0 of the Profibus interface respectively, and the Profibus control signal I/O ports PD15, PD14, PD13, PE4, and PA0 of the Profibus interface are connected with the Profibus reading The control terminal RD3, the Profibus write control terminal WR3, the address latch control terminal ALE3, the Profibus interrupt output terminal XINT, and the Profibus reset terminal PF_RESET are connected.

ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的串口数据端TXD0、RXD0分别与RS232串口模块的串口数据端TXD0、RXD0连接;RS232串口模块的数据端TXD02、RXD02分别与RS232设备的串口数据端连接;ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的接地端GND与RS232串口模块的的接地端GND连接,RS232串口模块的接地端GND与RS232设备的接地端GND连接。 The serial port data ports TXD0 and RXD0 of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor are respectively connected with the serial port data ports TXD0 and RXD0 of the RS232 serial port module; the data ports TXD02 and RXD02 of the RS232 serial port module are respectively connected with RS232 equipment serial port data terminal connection; ARM Cortex core microprocessor core control module 1 ARM Cortex core microprocessor ground terminal GND and RS232 serial port module ground terminal GND connection, RS232 serial port module ground terminal GND and RS232 The ground terminal of the device is connected to GND.

ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的I2C端口SCL、SDA分别与EEPROM存储器的I2C端口SCL、SDA连接。 The I2C ports SCL and SDA of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor are respectively connected with the I2C ports SCL and SDA of the EEPROM memory.

ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的数据/地址端PIE[0:7]分别与锁存器的数据输入端D[0:7]、SRAM存储器的数据端DB[0:7]连接;锁存器的数据输出端Q[0:7]与SRAM存储器的地址端AB[0:7]连接;ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的地址端PIE[8:15]与SRAM存储器的地址端AB[8:15]连接;ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的地址锁存I/O控制端PJ6与锁存器的地址锁存控制端LE连接;ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的SRAM控制I/O端口PH6、PH7、PJ4、PJ5分别与SRAM存储器的片使能控制端SCE1、片使能控制端SCE2、输出使能控制端SOE、写使能控制端SWE连接。 The data/address end PIE[0:7] of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor is respectively connected with the data input end D[0:7] of the latch and the data end of the SRAM memory DB[0:7] is connected; the data output terminal Q[0:7] of the latch is connected with the address terminal AB[0:7] of the SRAM memory; the ARM Cortex core of the core control module 1 of the ARM Cortex core microprocessor The address end PIE[8:15] of the microprocessor is connected with the address end AB[8:15] of the SRAM memory; the address latch I/O of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor O control terminal PJ6 is connected with the address latch control terminal LE of the latch; the SRAM control I/O ports PH6, PH7, PJ4, PJ5 of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor are respectively It is connected with the chip enable control terminal SCE1, the chip enable control terminal SCE2, the output enable control terminal SOE, and the write enable control terminal SWE of the SRAM memory.

本装置中蓝牙模块2如图3所示,蓝牙模块2的蓝牙控制器的蓝牙数据端RXD1、TXD1分别与ARM Cortex核微处理器的核心控制模块1的蓝牙接口的蓝牙数据端RXD1、TXD1连接,蓝牙接口的蓝牙数据端RXD1、TXD1分别与ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的蓝牙数据端RXD1、TXD1连接;蓝牙模块2的蓝牙控制器的蓝牙流控制端CTS1、RTS1分别与ARM Cortex核微处理器的核心控制模块1的蓝牙接口的蓝牙控制I/O端口PD0、PD1连接,蓝牙接口的蓝牙控制I/O端口PD0、PD1分别与ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的蓝牙控制I/O端口PD0、PD1连接;蓝牙模块2的蓝牙控制器的蓝牙复位控制端BL_RESET与ARM Cortex核微处理器的核心控制模块1的蓝牙接口的蓝牙复位I/O端口PC8连接,蓝牙接口的蓝牙复位I/O端口PC8与ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的蓝牙复位I/O端口PC8连接;蓝牙模块2的天线输入端RF_IN、天线输出端RF_OUT与天线连接;蓝牙模块2的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块1的电压输出端VCC_3.3连接;蓝牙模块2的接地端GND 与ARM Cortex核微处理器的核心控制模块1的接地端GND连接。 The bluetooth module 2 in this device is shown in Figure 3, and the bluetooth data end RXD1, TXD1 of the bluetooth controller of the bluetooth module 2 are respectively connected with the bluetooth data end RXD1, TXD1 of the bluetooth interface of the core control module 1 of the ARM Cortex core microprocessor , the bluetooth data end RXD1, TXD1 of the bluetooth interface are respectively connected with the bluetooth data end RXD1, TXD1 of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor; the bluetooth flow control of the bluetooth controller of the bluetooth module 2 Terminals CTS1 and RTS1 are respectively connected to the Bluetooth control I/O ports PD0 and PD1 of the Bluetooth interface of the core control module 1 of the ARM Cortex core microprocessor, and the Bluetooth control I/O ports PD0 and PD1 of the Bluetooth interface are respectively connected to the ARM Cortex core microprocessor. The Bluetooth control I/O ports PD0 and PD1 of the ARM Cortex core microprocessor of the core control module 1 of the processor are connected; the Bluetooth reset control terminal BL_RESET of the Bluetooth controller of the Bluetooth module 2 is connected with the core control module of the ARM Cortex core microprocessor The Bluetooth reset I/O port PC8 of the Bluetooth interface of 1 is connected, and the Bluetooth reset I/O port PC8 of the Bluetooth interface is connected with the core control module of the ARM Cortex core microprocessor of the ARM Cortex core microprocessor 1. The Bluetooth reset I/O port of the ARM Cortex core microprocessor PC8 connection; the antenna input terminal RF_IN and the antenna output terminal RF_OUT of the Bluetooth module 2 are connected to the antenna; the voltage input terminal VCC_3.3 of the Bluetooth module 2 is connected to the voltage output terminal VCC_3.3 of the core control module 1 of the ARM Cortex core microprocessor ; The ground terminal GND of the Bluetooth module 2 is connected with the ground terminal GND of the core control module 1 of the ARM Cortex core microprocessor.

     本装置中,Zigbee模块3如图4所示,Zigbee模块3的Zigbee控制器的Zigbee数据输出端SO1、Zigbee数据输入端SI1分别与ARM Cortex核微处理器的核心控制模块1的Zigbee接口的Zigbee数据I/O端口PA4、PA5连接,Zigbee接口的Zigbee数据I/O端口PA4、PA5分别与ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的Zigbee数据I/O端口PA4、PA5连接;Zigbee模块3的Zigbee控制器的Zigbee时钟输入端SCLK1、Zigbee片选控制端CSn1、Zigbee发送缓冲控制端FIFO、Zigbee接受缓冲控制端FIFOA、Zigbee复位端ZG_RESET分别与ARM Cortex核微处理器的核心控制模块1的Zigbee接口的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15连接,Zigbee接口的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15分别与ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15连接;Zigbee模块3的天线输入端RF_IN、天线输出端RF_OUT与天线连接;Zigbee模块3的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块1的电压输出端VCC_3.3连接;Zigbee模块3的接地端GND 与ARM Cortex核微处理器的核心控制模块1的接地端GND连接。 In this device, Zigbee module 3 as shown in Figure 4, the Zigbee data output end SO1 of the Zigbee controller of Zigbee module 3, the Zigbee data input end SI1 are respectively connected with the Zigbee interface of the core control module 1 of ARM Cortex nuclear microprocessor. Data I/O ports PA4, PA5 are connected, Zigbee data I/O ports PA4, PA5 of Zigbee interface are respectively connected with the Zigbee data I/O port PA4 of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor , PA5 connection; Zigbee clock input terminal SCLK1 of the Zigbee controller of Zigbee module 3, Zigbee chip selection control terminal CSn1, Zigbee sending buffer control terminal FIFO, Zigbee receiving buffer control terminal FIFOA, Zigbee reset terminal ZG_RESET and ARM Cortex core microprocessing respectively The Zigbee control I/O ports PA2, PD2, PD8, PD9, and PC15 of the Zigbee interface of the core control module 1 of the device are connected, and the Zigbee control I/O ports PA2, PD2, PD8, PD9, and PC15 of the Zigbee interface are respectively connected to the ARM Cortex core The Zigbee control I/O port PA2, PD2, PD8, PD9, PC15 of the ARM Cortex core microprocessor of the core control module 1 of the microprocessor is connected; the antenna input terminal RF_IN of the Zigbee module 3, the antenna output terminal RF_OUT are connected with the antenna; The voltage input terminal VCC_3.3 of the Zigbee module 3 is connected with the voltage output terminal VCC_3.3 of the core control module 1 of the ARM Cortex core microprocessor; the ground terminal GND of the Zigbee module 3 is connected with the core control module 1 of the ARM Cortex core microprocessor The ground terminal GND connection.

本装置中,CAN模块4如图5所示,CAN模块4的CAN驱动器的CAN数据端 CANTX、CANRX分别与ARM Cortex核微处理器的核心控制模块1的CAN接口的CAN数据端CANTX、CANRX连接,CAN接口的CAN数据端CANTX、CANRX分别与ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的CAN数据端CANTX、CANRX连接;CAN模块4的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块1的电压输出端VCC_3.3连接;CAN模块4的接地端GND 与ARM Cortex核微处理器的核心控制模块1的接地端GND连接。 In this device, CAN module 4 as shown in Figure 5, the CAN data end CANTX, CANRX of the CAN driver of CAN module 4 is respectively connected with the CAN data end CANTX, CANRX of the CAN interface of the core control module 1 of ARM Cortex core microprocessor , the CAN data ends CANTX, CANRX of the CAN interface are respectively connected with the CAN data ends CANTX, CANRX of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor; the voltage input end VCC_3.3 of the CAN module 4 is connected with The voltage output terminal VCC_3.3 of the core control module 1 of the ARM Cortex core microprocessor is connected; the ground terminal GND of the CAN module 4 is connected with the ground terminal GND of the core control module 1 of the ARM Cortex core microprocessor.

    本装置中,RS485模块5如图6所示,RS485模块5的RS485驱动器的RS485数据端TXD2、RXD2分别与ARM Cortex核微处理器的核心控制模块1的RS485接口的RS485数据端RXD2、TXD2连接,RS485接口的RS485数据端RXD2、TXD2分别与ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的RS485数据端RXD2、TXD2连接;RS485模块5的RS485驱动器的RS485接收使能端RE2、RS485发送使能端TE2 分别与ARM Cortex核微处理器的核心控制模块1的RS485接口的RS485控制I/O端口PB13、PB14连接,RS485接口的RS485控制I/O端口PB13、PB14分别与ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的RS485控制I/O端口PB13、PB14连接;RS485模块5的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块1的电压输出端VCC_3.3连接;RS485模块5的接地端GND 与ARM Cortex核微处理器的核心控制模块1的接地端GND连接。 In this device, the RS485 module 5 is shown in Figure 6, and the RS485 data terminals TXD2 and RXD2 of the RS485 driver of the RS485 module 5 are respectively connected with the RS485 data terminals RXD2 and TXD2 of the RS485 interface of the core control module 1 of the ARM Cortex core microprocessor , the RS485 data terminals RXD2 and TXD2 of the RS485 interface are respectively connected with the RS485 data terminals RXD2 and TXD2 of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor; the RS485 receiving enable of the RS485 driver of the RS485 module 5 Terminal RE2 and RS485 sending enabling terminal TE2 are respectively connected with RS485 control I/O ports PB13 and PB14 of the RS485 interface of the core control module 1 of the ARM Cortex core microprocessor, and RS485 control I/O ports PB13 and PB14 of the RS485 interface are respectively Connect with the RS485 control I/O port PB13, PB14 of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor; the voltage input terminal VCC_3.3 of the RS485 module 5 is connected with the core of the ARM Cortex core microprocessor The voltage output terminal VCC_3.3 of the control module 1 is connected; the ground terminal GND of the RS485 module 5 is connected to the ground terminal GND of the core control module 1 of the ARM Cortex core microprocessor.

本装置中, Profibus模块6 如图7所示,Profibus模块6的Profibus控制器的Profibus数据端DB[0:7]、地址端AB[8:15]分别与ARM Cortex核微处理器的核心控制模块1的Profibus接口的Profibus数据端/地址端PIE[0:7]、地址端PIE[8:15]连接,Profibus接口的数据端/地址端PIE[0:7]、地址端PIE[8:15]分别与ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的Profibus数据端/地址端PIE[0:7]、地址端PIE[8:15]连接;Profibus模块6的Profibus控制器的Profibus读控制端RD3、Profibus写控制端WR3、Profibus地址锁存控制端ALE3、Profibus中断输出端XINT、Profibus复位端PF_RESET分别与ARM Cortex核微处理器的核心控制模块1的Profibus接口的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0连接,Profibus接口的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0分别与ARM Cortex核微处理器的核心控制模块1的ARM Cortex核微处理器的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0连接;Profibus模块6的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块1的电压输出端VCC_3.3连接;Profibus模块6的接地端GND 与ARM Cortex核微处理器的核心控制模块1的接地端GND连接。 In this device, the Profibus module 6 is shown in Figure 7, and the Profibus data terminal DB[0:7] and the address terminal AB[8:15] of the Profibus controller of the Profibus module 6 are respectively connected with the core control of the ARM Cortex core microprocessor The Profibus data terminal/address terminal PIE[0:7] and address terminal PIE[8:15] of the Profibus interface of module 1 are connected, and the data terminal/address terminal PIE[0:7] and address terminal PIE[8: 15] respectively connected with the Profibus data end/address end PIE[0:7] and address end PIE[8:15] of the ARM Cortex core microprocessor of the core control module 1 of the ARM Cortex core microprocessor; the Profibus module 6 The Profibus read control terminal RD3, Profibus write control terminal WR3, Profibus address latch control terminal ALE3, Profibus interrupt output terminal XINT, and Profibus reset terminal PF_RESET of the Profibus controller are respectively connected to the Profibus interface of the core control module 1 of the ARM Cortex core microprocessor The Profibus control signal I/O ports PD15, PD14, PD13, PE4, PA0 are connected, and the Profibus control signal I/O ports PD15, PD14, PD13, PE4, PA0 of the Profibus interface are respectively connected with the core control module of the ARM Cortex core microprocessor The Profibus control signal I/O port PD15, PD14, PD13, PE4, PA0 of the ARM Cortex core microprocessor of 1 is connected; the voltage input terminal VCC_3.3 of the Profibus module 6 is connected with the core control module 1 of the ARM Cortex core microprocessor The voltage output terminal VCC_3.3 is connected; the ground terminal GND of the Profibus module 6 is connected with the ground terminal GND of the core control module 1 of the ARM Cortex core microprocessor.

本装置中,模块式多数据转换装置的数据处理、转发流程图如图8、9、10、11所示,其步骤为: In this device, the data processing and forwarding flowcharts of the modular multi-data conversion device are shown in Figures 8, 9, 10, and 11, and the steps are as follows:

1)ARM Cortex核微处理器的核心控制模块1上电初始化,完成模块式多数据转换装置的初始化程序和数据的加载,并将SRAM存储器的存储空间划分为:蓝牙、Zigbee、CAN、RS485、Profibus、RS232等数据通讯收发通道的缓存区; 1) The core control module 1 of the ARM Cortex core microprocessor is powered on and initialized, and the initialization program and data loading of the modular multi-data conversion device are completed, and the storage space of the SRAM memory is divided into: Bluetooth, Zigbee, CAN, RS485, The buffer area of data communication sending and receiving channels such as Profibus and RS232;

2)用户通过设置键盘模块,对模块式多数据转换装置的各通讯模块的硬件参数进行配置,并执行相应通讯子程序的使能或屏蔽操作; 2) The user configures the hardware parameters of each communication module of the modular multi-data conversion device by setting the keyboard module, and executes the enabling or shielding operation of the corresponding communication subroutine;

3)将各通讯模块的配置参数存储在EEPROM存储器内; 3) Store the configuration parameters of each communication module in the EEPROM memory;

4)执行使能通讯模块的初始化子程序,完成其硬件配置参数的设置; 4) Execute the initialization subroutine that enables the communication module to complete the setting of its hardware configuration parameters;

5)模块式多数据转换装置的数据转换与控制程序由数据帧的中断接收子程序、多数据转换处理子程序、以及轮询数据转发传输子程序等三部分组成,其中中断接收子程序负责对蓝牙模块2、Zigbee模块3、CAN模块4、RS485模块5、Profibus模块6、RS232等通讯模块的数据帧进行接收,根据ARM Cortex核微处理器中各模块的中断的优先等级,实现相应各通讯模块的接收数据的处理;多数据转换处理子程序负责对接收到的数据帧按照目的地地址进行检测,并按照发送的地址,依次将接受的数据帧存储到SRAM存储器各相应的数据通讯发送通道的缓存区内;轮询数据转发传输子程序则负责对SRAM存储器内的各个数据通讯发送通道的缓存区的头、尾指针是否相等进行检测,如果数据通讯发送通道的缓存区的头、尾指针不相等,依次将数据通讯发送通道的缓存区中的数据发送到各通讯模块的发送缓冲区内。 5) The data conversion and control program of the modular multi-data conversion device consists of three parts: the interrupt receiving subroutine of the data frame, the multi-data conversion processing subroutine, and the polling data forwarding and transmission subroutine, among which the interrupt receiving subroutine is responsible for Receive data frames from communication modules such as Bluetooth module 2, Zigbee module 3, CAN module 4, RS485 module 5, Profibus module 6, RS232, etc., and realize corresponding communication according to the interrupt priority level of each module in the ARM Cortex core microprocessor. The processing of the received data of the module; the multi-data conversion processing subroutine is responsible for detecting the received data frame according to the destination address, and sequentially storing the received data frame into the corresponding data communication transmission channel of the SRAM memory according to the sent address In the buffer area; the polling data forwarding transmission subroutine is responsible for detecting whether the head and tail pointers of the buffer areas of each data communication sending channel in the SRAM memory are equal, if the head and tail pointers of the buffer area of the data communication sending channel Not equal, send the data in the buffer area of the data communication sending channel to the sending buffer of each communication module in turn.

本具体实施方式采用硬件上具有可裁剪性的模块式安装方式,同时利用ARM Cortex核微处理器高速的处理特性,很方便地实现多通讯数据间的数据转换、数据传输功能。因此,本发明具有处理响应速度快、体积小、较高的灵活性、较强的环境适应性等优点。 This specific embodiment adopts a modular installation method with tailorability on the hardware, and at the same time utilizes the high-speed processing characteristics of the ARM Cortex core microprocessor to conveniently realize the data conversion and data transmission functions between multiple communication data. Therefore, the present invention has the advantages of fast processing response speed, small volume, high flexibility, strong environmental adaptability and the like.

Claims (7)

1.一种模块式多数据转换装置,其特征在于:由基于ARM Cortex核微处理器的核心控制模块(1)、电源模块、设置键盘模块、LCD显示模块和通讯模块组成,所述的通迅模块为蓝牙模块(2)、Zigbee模块(3)、CAN模块(4)、RS485模块(5)和Profibus模块(6)中的两种或多种模块,该转换装置可以根据需要在ARM Cortex核微处理器的核心控制模块(1)的通讯接口上接插可选的通讯模块,以实现多种通讯数据间的数据格式转换和数据传输的功能,其中: 1. A modular multi-data conversion device is characterized in that: it is made up of a core control module (1), a power supply module, a keyboard module, an LCD display module and a communication module based on an ARM Cortex core microprocessor, and the described communication module Xun module is two or more modules in Bluetooth module (2), Zigbee module (3), CAN module (4), RS485 module (5) and Profibus module (6). An optional communication module is plugged into the communication interface of the core control module (1) of the core microprocessor to realize the functions of data format conversion and data transmission among various communication data, among which: ARM Cortex核微处理器的核心控制模块(1)的电压输入端与电源模块的电压输出端连接;设置键盘模块的键盘输出端与ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的键盘输入I/O端连接;LCD显示模块的LCD控制端、LCD数据端分别与ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的LCD控制I/O端、LCD数据端连接;蓝牙模块(2)的蓝牙控制端和蓝牙数据端通过ARM Cortex核微处理器的核心控制模块(1)的蓝牙接口分别与ARM Cortex核微处理器的蓝牙控制I/O端和蓝牙数据端连接;Zigbee模块(3)的Zigbee控制端和Zigbee数据端通过ARM Cortex核微处理器的核心控制模块(1)的Zigbee接口分别与ARM Cortex核微处理器的Zigbee控制I/O端和Zigbee数据I/O端连接;CAN模块(4)的CAN数据端通过ARM Cortex核微处理器的核心控制模块(1)的CAN接口分别与ARM Cortex核微处理器的CAN数据端连接;RS485模块(5)的RS485数据端和RS485控制端通过ARM Cortex核微处理器的核心控制模块(1)的RS485接口分别与ARM Cortex核微处理器的RS485数据端和RS485控制I/O端连接;Profibus模块(6)的Profibus控制端和Profibus数据端、Profibus地址端通过ARM Cortex核微处理器的核心控制模块(1)的Profibus接口分别与ARM Cortex核微处理器的Profibus控制I/O端口、Profibus数据端、Profibus地址端连接;ARM Cortex核微处理器的串口数据端与RS232串口模块的串口数据端连接,RS232串口模块的串口数据端与RS232设备的串口数据端连接;ARM Cortex核微处理器的EEPROM数据端、EEPROM控制端与EEPROM存储器的EEPROM数据、EEPROM控制端连接;ARM Cortex核微处理器的SRAM数据端、SRAM地址端、SRAM控制I/O端口分别与SRAM存储器的SRAM数据、SRAM地址端、SRAM控制端连接; The voltage input terminal of the core control module (1) of the ARM Cortex core microprocessor is connected with the voltage output terminal of the power supply module; The keyboard input I/O end of the core microprocessor is connected; the LCD control terminal and the LCD data end of the LCD display module are respectively connected with the LCD control I of the ARM Cortex core microprocessor of the core control module (1) of the ARM Cortex core microprocessor. /O terminal and LCD data terminal are connected; the Bluetooth control terminal and the Bluetooth data terminal of the Bluetooth module (2) are respectively connected with the Bluetooth control of the ARM Cortex core microprocessor through the Bluetooth interface of the core control module (1) of the ARM Cortex core microprocessor The I/O end is connected to the Bluetooth data end; the Zigbee control end and the Zigbee data end of the Zigbee module (3) are respectively connected to the Zigbee interface of the ARM Cortex core microprocessor through the Zigbee interface of the core control module (1) of the ARM Cortex core microprocessor. The control I/O terminal is connected to the Zigbee data I/O terminal; the CAN data terminal of the CAN module (4) is connected to the CAN interface of the ARM Cortex core microprocessor through the CAN interface of the core control module (1) of the ARM Cortex core microprocessor. Data end connection; the RS485 data end and RS485 control end of the RS485 module (5) are respectively connected to the RS485 data end and the RS485 control I of the ARM Cortex core microprocessor through the RS485 interface of the core control module (1) of the ARM Cortex core microprocessor. /O terminal connection; the Profibus control terminal, Profibus data terminal and Profibus address terminal of the Profibus module (6) are respectively controlled by the Profibus interface of the core control module (1) of the ARM Cortex core microprocessor and the Profibus control of the ARM Cortex core microprocessor I/O port, Profibus data terminal and Profibus address terminal are connected; the serial data terminal of the ARM Cortex core microprocessor is connected with the serial data terminal of the RS232 serial port module, and the serial data terminal of the RS232 serial port module is connected with the serial data terminal of the RS232 device; The EEPROM data end and EEPROM control end of the ARM Cortex core microprocessor are connected to the EEPROM data and EEPROM control end of the EEPROM memory; the SRAM data end, SRAM address end, and SRAM control I/O port of the ARM Cortex core microprocessor are respectively connected to the SRAM The SRAM data of the memory, the SRAM address terminal, and the SRAM control terminal are connected; 所述的ARM Cortex核微处理器为ARM Cortex-M4 32位微处理器或 ARM Cortex-M3 32位微处理器; Described ARM Cortex core microprocessor is ARM Cortex-M4 32 bit microprocessors or ARM Cortex-M3 32 bit microprocessors; 电源模块的电压输出端VDD、VCC分别与ARM Cortex核微处理器的核心控制模块(1)的电压输入端VCC_5、VCC_3.3连接;ARM Cortex核微处理器的核心控制模块(1)的电压输出端VCC_3.3分别与LCD显示模块的电压输入端VCC_3.3、蓝牙模块(2)的电压输入端VCC_3.3、Zigbee模块(3)的电压输入端VCC_3.3、CAN模块(4)的电压输入端VCC_3.3、RS485模块(5)的电压输入端VCC_3.3、Profibus模块(6)的电压输入端VCC_3.3连接;ARM Cortex核微处理器的核心控制模块(1)的电压输出端VCC_5与LCD显示模块的电压输入端VCC_5连接;电源模块的接地端GND与ARM Cortex核微处理器的核心控制模块(1)的接地端GND连接;ARM Cortex核微处理器的核心控制模块(1)的接地端GND分别与LCD显示模块的接地端GND、蓝牙模块(2)的接地端GND、Zigbee模块(3)的接地端GND、CAN模块(4)的接地端GND、RS485模块(5)的接地端GND、Profibus模块(6)的接地端GND连接; The voltage output terminals VDD and VCC of the power module are respectively connected to the voltage input terminals VCC_5 and VCC_3.3 of the core control module (1) of the ARM Cortex core microprocessor; the voltage of the core control module (1) of the ARM Cortex core microprocessor The output terminal VCC_3.3 is respectively connected to the voltage input terminal VCC_3.3 of the LCD display module, the voltage input terminal VCC_3.3 of the Bluetooth module (2), the voltage input terminal VCC_3.3 of the Zigbee module (3), and the voltage input terminal of the CAN module (4). The voltage input terminal VCC_3.3, the voltage input terminal VCC_3.3 of the RS485 module (5), the voltage input terminal VCC_3.3 of the Profibus module (6) are connected; the voltage output of the core control module (1) of the ARM Cortex core microprocessor The terminal VCC_5 is connected to the voltage input terminal VCC_5 of the LCD display module; the ground terminal GND of the power supply module is connected to the ground terminal GND of the core control module (1) of the ARM Cortex core microprocessor; the core control module of the ARM Cortex core microprocessor ( The ground terminal GND of 1) is connected with the ground terminal GND of the LCD display module, the ground terminal GND of the Bluetooth module (2), the ground terminal GND of the Zigbee module (3), the ground terminal GND of the CAN module (4), and the RS485 module (5 ) to the ground GND of the Profibus module (6) and the ground GND of the Profibus module (6); ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的LCD控制I/O端口PD3、PD4、PD5分别与LCD显示模块的LCD指令控制端RS、LCD读写控制端R/W、LCD片选端CE连接;ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的LCD数据端PC[0:7]与LCD显示模块的LCD数据端DB[0:7]连接; The core control module of the ARM Cortex core microprocessor (1) The LCD control I/O ports PD3, PD4, and PD5 of the ARM Cortex core microprocessor are respectively connected with the LCD command control terminal RS and the LCD read and write control terminal R of the LCD display module /W, LCD chip selection terminal CE connection; the LCD data terminal PC[0:7] of the ARM Cortex core microprocessor core control module (1) of the ARM Cortex core microprocessor and the LCD data terminal DB[ of the LCD display module 0:7] connect; ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的键盘输入I/O端口PC10、PC11、PC12、PC13、PC14分别与设置键盘模块的键盘输出端左移键K1、右移键K2、上页键K3、下页键K4、设定键K5连接;ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的复位输入端Reset与设置键盘模块的复位输出端Reset连接; The keyboard input I/O ports PC10, PC11, PC12, PC13, and PC14 of the ARM Cortex core microprocessor of the core control module (1) of the ARM Cortex core microprocessor are respectively connected with the keyboard output terminal left shift key K1, Right shift key K2, page up key K3, page down key K4, and setting key K5 are connected; the core control module of the ARM Cortex core microprocessor (1) resets the input terminal Reset of the ARM Cortex core microprocessor and sets the keyboard module The reset output terminal Reset is connected; ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的蓝牙数据端RXD1、TXD1分别与蓝牙接口的蓝牙数据端RXD1、TXD1连接,蓝牙接口的蓝牙数据端RXD1、TXD1分别与蓝牙模块(2)的蓝牙数据端RXD1、TXD1连接;ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的蓝牙控制I/O端口PD0、PD1分别与蓝牙接口的蓝牙控制I/O端口PD0、PD1连接,蓝牙接口的蓝牙控制I/O端口PD0、PD1分别与蓝牙模块(2)的蓝牙流控制端CTS1、RTS1连接;ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的蓝牙复位I/O端口PC8与蓝牙接口的蓝牙复位I/O端口PC8连接,蓝牙接口的蓝牙复位I/O端口PC8与蓝牙模块(2)的蓝牙复位控制端BL_RESET连接; The core control module of the ARM Cortex core microprocessor (1) The Bluetooth data terminals RXD1 and TXD1 of the ARM Cortex core microprocessor are respectively connected with the Bluetooth data terminals RXD1 and TXD1 of the Bluetooth interface, and the Bluetooth data terminals RXD1 and TXD1 of the Bluetooth interface are respectively Connect with the Bluetooth data terminals RXD1 and TXD1 of the Bluetooth module (2); the Bluetooth control I/O ports PD0 and PD1 of the ARM Cortex core microprocessor of the ARM Cortex core microprocessor in the ARM Cortex core control module (1) are respectively connected to the Bluetooth interface The Bluetooth control I/O ports PD0 and PD1 are connected, and the Bluetooth control I/O ports PD0 and PD1 of the Bluetooth interface are respectively connected to the Bluetooth flow control terminals CTS1 and RTS1 of the Bluetooth module (2); the core control module of the ARM Cortex core microprocessor (1) The Bluetooth reset I/O port PC8 of the ARM Cortex core microprocessor is connected to the Bluetooth reset I/O port PC8 of the Bluetooth interface, and the Bluetooth reset I/O port PC8 of the Bluetooth interface is connected to the Bluetooth reset I/O port of the Bluetooth module (2) Control terminal BL_RESET connection; ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的Zigbee数据I/O端口PA4、PA5分别与Zigbee接口的Zigbee数据I/O端口PA4、PA5连接,Zigbee接口的Zigbee数据I/O端口PA4、PA5分别与Zigbee模块(3)的Zigbee数据输出端SO1、Zigbee数据输入端SI1连接;ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15分别与Zigbee接口的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15连接,Zigbee接口的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15分别与Zigbee模块(3)的Zigbee时钟输入端SCLK1、Zigbee片选控制端CSn1、Zigbee发送缓冲控制端FIFO、Zigbee接受缓冲控制端FIFOA、Zigbee复位端ZG_RESET连接; The core control module of the ARM Cortex core microprocessor (1) is connected with the Zigbee data I/O ports PA4 and PA5 of the Zigbee data I/O ports PA4 and PA5 of the ARM Cortex core microprocessor respectively, and the Zigbee interface of the Zigbee interface The data I/O ports PA4 and PA5 are respectively connected with the Zigbee data output terminal SO1 and the Zigbee data input terminal SI1 of the Zigbee module (3); the ARM Cortex core microprocessor of the ARM Cortex core microprocessor core control module (1) The Zigbee control I/O ports PA2, PD2, PD8, PD9, and PC15 are respectively connected to the Zigbee control I/O ports PA2, PD2, PD8, PD9, and PC15 of the Zigbee interface, and the Zigbee control I/O ports PA2, PD2, and PD8, PD9, and PC15 are respectively connected to the Zigbee clock input terminal SCLK1, Zigbee chip selection control terminal CSn1, Zigbee sending buffer control terminal FIFO, Zigbee receiving buffer control terminal FIFOA, and Zigbee reset terminal ZG_RESET of the Zigbee module (3); ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的CAN数据端CANTX、CANRX分别与CAN接口的CAN数据端CANTX、CANRX连接,CAN接口的CAN数据端CANTX、CANRX分别与CAN模块(4)的CAN数据端CANRX、CANTX连接; The CAN data terminals CANTX and CANRX of the ARM Cortex core microprocessor of the core control module (1) of the ARM Cortex core microprocessor are respectively connected with the CAN data terminals CANTX and CANRX of the CAN interface, and the CAN data terminals CANTX and CANRX of the CAN interface are respectively Connect with the CAN data terminals CANRX and CANTX of the CAN module (4); ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的RS485数据端RXD2、TXD2分别与RS485接口的RS485数据端RXD2、TXD2连接,RS485接口的RS485数据端RXD2、TXD2分别与RS485模块(5)的RS485数据端RXD2、TXD2连接;ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的RS485控制I/O端口PB13、PB14分别与RS485接口的RS485控制I/O端口PB13、PB14连接,RS485接口的RS485控制I/O端口PB13、PB14分别与RS485模块(5)的RS485接收使能端RE2、RS485发送使能端TE2连接; The core control module of the ARM Cortex core microprocessor (1) RS485 data terminals RXD2 and TXD2 of the ARM Cortex core microprocessor are respectively connected with the RS485 data terminals RXD2 and TXD2 of the RS485 interface, and the RS485 data terminals RXD2 and TXD2 of the RS485 interface are respectively Connect with the RS485 data terminals RXD2 and TXD2 of the RS485 module (5); the RS485 control I/O ports PB13 and PB14 of the ARM Cortex core microprocessor of the core control module (1) of the ARM Cortex core microprocessor are respectively connected to the RS485 interface The RS485 control I/O ports PB13 and PB14 are connected, and the RS485 control I/O ports PB13 and PB14 of the RS485 interface are respectively connected to the RS485 receiving enabling terminal RE2 and RS485 transmitting enabling terminal TE2 of the RS485 module (5); ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的数据端/地址端PIE[0:7]、地址端PIE[8:15]分别与Profibus接口的数据端/地址端PIE[0:7]、地址端PIE[8:15]连接,Profibus接口的数据端/地址端PIE[0:7]、地址端PIE[8:15]分别与Profibus模块(6)的Profibus数据端DB[0:7]、地址端AB[8:15]连接;ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0分别与Profibus接口的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0连接,Profibus接口的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0分别与Profibus模块(6)的Profibus读控制端RD3、Profibus写控制端WR3、地址锁存控制端ALE3、 Profibus中断输出端XINT、Profibus复位端PF_RESET连接; The core control module of the ARM Cortex core microprocessor (1) The data terminal/address terminal PIE[0:7] and the address terminal PIE[8:15] of the ARM Cortex core microprocessor are respectively connected to the data terminal/address of the Profibus interface Terminal PIE[0:7], address terminal PIE[8:15] are connected, and the data terminal/address terminal PIE[0:7] and address terminal PIE[8:15] of the Profibus interface are respectively connected to the Profibus of the Profibus module (6). Data terminal DB[0:7], address terminal AB[8:15] connection; ARM Cortex core microprocessor core control module (1) Profibus control signal I/O port PD15, PD14 of ARM Cortex core microprocessor , PD13, PE4, and PA0 are respectively connected to the Profibus control signal I/O ports PD15, PD14, PD13, PE4, and PA0 of the Profibus interface, and the Profibus control signal I/O ports PD15, PD14, PD13, PE4, and PA0 of the Profibus interface are respectively connected to Profibus module (6) Profibus read control terminal RD3, Profibus write control terminal WR3, address latch control terminal ALE3, Profibus interrupt output terminal XINT, Profibus reset terminal PF_RESET are connected; ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的串口数据端TXD0、RXD0分别与RS232串口模块的串口数据端TXD0、RXD0连接;RS232串口模块的数据端TXD02、RXD02分别与RS232设备的串口数据端连接;ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的接地端GND与RS232串口模块的的接地端GND连接,RS232串口模块的接地端GND与RS232设备的接地端GND连接; The core control module of the ARM Cortex core microprocessor (1) The serial port data ports TXD0 and RXD0 of the ARM Cortex core microprocessor are respectively connected to the serial port data ports TXD0 and RXD0 of the RS232 serial port module; the data ports TXD02 and RXD02 of the RS232 serial port module Connect to the serial port data port of the RS232 device respectively; the ground terminal GND of the ARM Cortex core microprocessor core control module (1) of the ARM Cortex core microprocessor is connected to the ground terminal GND of the RS232 serial port module, and the ground terminal of the RS232 serial port module The terminal GND is connected to the ground terminal GND of the RS232 device; ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的I2C端口SCL、SDA分别与EEPROM存储器的I2C端口SCL、SDA连接; The I2C ports SCL and SDA of the ARM Cortex core microprocessor of the core control module (1) of the ARM Cortex core microprocessor are respectively connected with the I2C ports SCL and SDA of the EEPROM memory; ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的数据/地址端PIE[0:7]分别与锁存器的数据输入端D[0:7]、SRAM存储器的数据端DB[0:7]连接;锁存器的数据输出端Q[0:7]与SRAM存储器的地址端AB[0:7]连接;ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的地址端PIE[8:15]与SRAM存储器的地址端AB[8:15]连接;ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的地址锁存I/O控制端PJ6与锁存器的地址锁存控制端LE连接;ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的SRAM控制I/O端口PH6、PH7、PJ4、PJ5分别与SRAM存储器的片使能控制端SCE1、片使能控制端SCE2、输出使能控制端SOE、写使能控制端SWE连接。 The data/address terminal PIE[0:7] of the ARM Cortex core microprocessor in the core control module (1) of the ARM Cortex core microprocessor is connected with the data input terminal D[0:7] of the latch and the SRAM memory respectively. The data terminal DB[0:7] is connected; the data output terminal Q[0:7] of the latch is connected to the address terminal AB[0:7] of the SRAM memory; the core control module of the ARM Cortex core microprocessor (1) The address terminal PIE[8:15] of the ARM Cortex core microprocessor is connected with the address terminal AB[8:15] of the SRAM memory; the core control module (1) of the ARM Cortex core microprocessor of the ARM Cortex core microprocessor The address latch I/O control terminal PJ6 of the latch is connected to the address latch control terminal LE of the latch; the SRAM control I/O port of the ARM Cortex core microprocessor core control module (1) of the ARM Cortex core microprocessor PH6, PH7, PJ4, and PJ5 are respectively connected to the chip enable control terminal SCE1, the chip enable control terminal SCE2, the output enable control terminal SOE, and the write enable control terminal SWE of the SRAM memory. 2.根据权利要求1所述一种模块式多数据转换装置,其特征在于:所述的蓝牙模块(2)的结构为: 2. A modular multi-data conversion device according to claim 1, characterized in that: the structure of the Bluetooth module (2) is: 蓝牙模块(2)的蓝牙控制器的蓝牙数据端RXD1、TXD1分别与ARM Cortex核微处理器的核心控制模块(1)的蓝牙接口的蓝牙数据端RXD1、TXD1连接,蓝牙接口的蓝牙数据端RXD1、TXD1分别与ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的蓝牙数据端RXD1、TXD1连接;蓝牙模块(2)的蓝牙控制器的蓝牙流控制端CTS1、RTS1分别与ARM Cortex核微处理器的核心控制模块(1)的蓝牙接口的蓝牙控制I/O端口PD0、PD1连接,蓝牙接口的蓝牙控制I/O端口PD0、PD1分别与ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的蓝牙控制I/O端口PD0、PD1连接;蓝牙模块(2)的蓝牙控制器的蓝牙复位控制端BL_RESET与ARM Cortex核微处理器的核心控制模块(1)的蓝牙接口的蓝牙复位I/O端口PC8连接,蓝牙接口的蓝牙复位I/O端口PC8与ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的蓝牙复位I/O端口PC8连接;蓝牙模块(2)的天线输入端RF_IN、天线输出端RF_OUT与天线连接;蓝牙模块(2)的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块(1)的电压输出端VCC_3.3连接;蓝牙模块(2)的接地端GND 与ARM Cortex核微处理器的核心控制模块(1)的接地端GND连接。 The Bluetooth data terminals RXD1 and TXD1 of the Bluetooth controller of the Bluetooth module (2) are respectively connected with the Bluetooth data terminals RXD1 and TXD1 of the Bluetooth interface of the ARM Cortex core microprocessor core control module (1), and the Bluetooth data terminals RXD1 of the Bluetooth interface , TXD1 are respectively connected with the Bluetooth data terminals RXD1 and TXD1 of the ARM Cortex core microprocessor core control module (1) of the ARM Cortex core microprocessor; the Bluetooth flow control terminals CTS1 and RTS1 of the Bluetooth controller of the Bluetooth module (2) Connect with the Bluetooth control I/O ports PD0 and PD1 of the Bluetooth interface of the core control module (1) of the ARM Cortex core microprocessor respectively, and the Bluetooth control I/O ports PD0 and PD1 of the Bluetooth interface are respectively connected to the ARM Cortex core microprocessor The Bluetooth control I/O ports PD0 and PD1 of the ARM Cortex core microprocessor of the core control module (1) are connected; the Bluetooth reset control terminal BL_RESET of the Bluetooth controller of the Bluetooth module (2) is connected with the core of the ARM Cortex core microprocessor The Bluetooth reset I/O port PC8 of the Bluetooth interface of the control module (1) is connected, and the Bluetooth reset I/O port PC8 of the Bluetooth interface is connected with the core control module (1) of the ARM Cortex core microprocessor of the ARM Cortex core microprocessor The Bluetooth reset I/O port is connected to PC8; the antenna input terminal RF_IN and the antenna output terminal RF_OUT of the Bluetooth module (2) are connected to the antenna; the voltage input terminal VCC_3.3 of the Bluetooth module (2) is connected to the core control of the ARM Cortex core microprocessor The voltage output terminal VCC_3.3 of the module (1) is connected; the ground terminal GND of the Bluetooth module (2) is connected to the ground terminal GND of the core control module (1) of the ARM Cortex core microprocessor. 3.根据权利要求1所述一种模块式多数据转换装置,其特征在于:所述的Zigbee模块(3)的结构为: 3. A modular multi-data conversion device according to claim 1, characterized in that: the structure of the Zigbee module (3) is: Zigbee模块(3)的Zigbee控制器的Zigbee数据输出端SO1、Zigbee数据输入端SI1分别与ARM Cortex核微处理器的核心控制模块(1)的Zigbee接口的Zigbee数据I/O端口PA4、PA5连接,Zigbee接口的Zigbee数据I/O端口PA4、PA5分别与ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的Zigbee数据I/O端口PA4、PA5连接;Zigbee模块(3)的Zigbee控制器的Zigbee时钟输入端SCLK1、Zigbee片选控制端CSn1、Zigbee发送缓冲控制端FIFO、Zigbee接受缓冲控制端FIFOA、Zigbee复位端ZG_RESET分别与ARM Cortex核微处理器的核心控制模块(1)的Zigbee接口的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15连接,Zigbee接口的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15分别与ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的Zigbee控制I/O端口PA2、PD2、PD8、PD9、PC15连接;Zigbee模块(3)的天线输入端RF_IN、天线输出端RF_OUT与天线连接;Zigbee模块(3)的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块(1)的电压输出端VCC_3.3连接;Zigbee模块(3)的接地端GND 与ARM Cortex核微处理器的核心控制模块(1)的接地端GND连接。 The Zigbee data output terminal SO1 and the Zigbee data input terminal SI1 of the Zigbee controller of the Zigbee module (3) are respectively connected with the Zigbee data I/O ports PA4 and PA5 of the Zigbee interface of the core control module (1) of the ARM Cortex core microprocessor , the Zigbee data I/O ports PA4, PA5 of the Zigbee interface are connected with the Zigbee data I/O ports PA4, PA5 of the ARM Cortex core microprocessor of the core control module (1) of the ARM Cortex core microprocessor respectively; Zigbee module ( 3) The Zigbee clock input terminal SCLK1, Zigbee chip selection control terminal CSn1, Zigbee transmission buffer control terminal FIFO, Zigbee receiving buffer control terminal FIFOA, Zigbee reset terminal ZG_RESET of the Zigbee controller are respectively connected with the core control module of the ARM Cortex core microprocessor (1) The Zigbee control I/O ports PA2, PD2, PD8, PD9, and PC15 of the Zigbee interface are connected, and the Zigbee control I/O ports PA2, PD2, PD8, PD9, and PC15 of the Zigbee interface are respectively connected to the ARM Cortex core microprocessor The core control module (1) is connected to the Zigbee control I/O ports PA2, PD2, PD8, PD9, and PC15 of the ARM Cortex core microprocessor; the antenna input terminal RF_IN and the antenna output terminal RF_OUT of the Zigbee module (3) are connected to the antenna ; The voltage input terminal VCC_3.3 of the Zigbee module (3) is connected to the voltage output terminal VCC_3.3 of the core control module (1) of the ARM Cortex core microprocessor; the ground terminal GND of the Zigbee module (3) is connected to the ARM Cortex core microprocessor Connect to the ground terminal GND of the core control module (1) of the processor. 4.根据权利要求1所述一种模块式多数据转换装置,其特征在于:所述的CAN模块(4)的结构为: 4. A modular multi-data conversion device according to claim 1, characterized in that: the structure of the CAN module (4) is: CAN模块(4)的CAN驱动器的CAN数据端 CANTX、CANRX分别与ARM Cortex核微处理器的核心控制模块(1)的CAN接口的CAN数据端CANTX、CANRX连接,CAN接口的CAN数据端CANTX、CANRX分别与ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的CAN数据端CANTX、CANRX连接;CAN模块(4)的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块(1)的电压输出端VCC_3.3连接;CAN模块(4)的接地端GND 与ARM Cortex核微处理器的核心控制模块(1)的接地端GND连接。 The CAN data terminals CANTX and CANRX of the CAN driver of the CAN module (4) are respectively connected with the CAN data terminals CANTX and CANRX of the CAN interface of the ARM Cortex core microprocessor core control module (1), and the CAN data terminals CANTX and CANRX of the CAN interface are connected. CANRX is respectively connected with the CAN data terminals CANTX and CANRX of the ARM Cortex core microprocessor core control module (1) of the ARM Cortex core microprocessor; the voltage input terminal VCC_3.3 of the CAN module (4) is connected with the ARM Cortex core microprocessor The voltage output terminal VCC_3.3 of the core control module (1) of the device is connected; the ground terminal GND of the CAN module (4) is connected with the ground terminal GND of the core control module (1) of the ARM Cortex core microprocessor. 5.根据权利要求1所述一种模块式多数据转换装置,其特征在于所述的RS485模块(5)的结构为: 5. A modular multi-data conversion device according to claim 1, characterized in that the structure of the RS485 module (5) is: RS485模块(5)的RS485驱动器的RS485数据端TXD2、RXD2分别与ARM Cortex核微处理器的核心控制模块(1)的RS485接口的RS485数据端RXD2、TXD2连接,RS485接口的RS485数据端RXD2、TXD2分别与ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的RS485数据端RXD2、TXD2连接;RS485模块(5)的RS485驱动器的RS485接收使能端RE2、RS485发送使能端TE2 分别与ARM Cortex核微处理器的核心控制模块(1)的RS485接口的RS485控制I/O端口PB13、PB14连接,RS485接口的RS485控制I/O端口PB13、PB14分别与ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的RS485控制I/O端口PB13、PB14连接;RS485模块(5)的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块(1)的电压输出端VCC_3.3连接;RS485模块(5)的接地端GND 与ARM Cortex核微处理器的核心控制模块(1)的接地端GND连接。 The RS485 data terminals TXD2 and RXD2 of the RS485 driver of the RS485 module (5) are respectively connected to the RS485 data terminals RXD2 and TXD2 of the RS485 interface of the core control module (1) of the ARM Cortex core microprocessor, and the RS485 data terminals RXD2 and TXD2 of the RS485 interface are respectively connected. TXD2 is respectively connected with the RS485 data terminals RXD2 and TXD2 of the ARM Cortex core microprocessor core control module (1) of the ARM Cortex core microprocessor; The enabling terminal TE2 is respectively connected to the RS485 control I/O ports PB13 and PB14 of the RS485 interface of the core control module (1) of the ARM Cortex core microprocessor, and the RS485 control I/O ports PB13 and PB14 of the RS485 interface are respectively connected to the ARM Cortex The RS485 control I/O ports PB13 and PB14 of the ARM Cortex core microprocessor of the core control module (1) of the core microprocessor are connected; the voltage input terminal VCC_3.3 of the RS485 module (5) is connected with the ARM Cortex core microprocessor The voltage output terminal VCC_3.3 of the core control module (1) is connected; the ground terminal GND of the RS485 module (5) is connected to the ground terminal GND of the core control module (1) of the ARM Cortex core microprocessor. 6.根据权利要求1所述一种模块式多数据转换装置,其特征在于:所述的Profibus模块(6)的结构为: 6. A modular multi-data conversion device according to claim 1, characterized in that: the structure of the Profibus module (6) is: Profibus模块(6)的Profibus控制器的Profibus数据端DB[0:7]、地址端AB[8:15]分别与ARM Cortex核微处理器的核心控制模块(1)的Profibus接口的Profibus数据端/地址端PIE[0:7]、地址端PIE[8:15]连接,Profibus接口的数据端/地址端PIE[0:7]、地址端PIE[8:15]分别与ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的Profibus数据端/地址端PIE[0:7]、地址端PIE[8:15]连接;Profibus模块(6)的Profibus控制器的Profibus读控制端RD3、Profibus写控制端WR3、Profibus地址锁存控制端ALE3、Profibus中断输出端XINT、Profibus复位端PF_RESET分别与ARM Cortex核微处理器的核心控制模块(1)的Profibus接口的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0连接,Profibus接口的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0分别与ARM Cortex核微处理器的核心控制模块(1)的ARM Cortex核微处理器的Profibus控制信号I/O端口PD15、PD14、PD13、PE4、PA0连接;Profibus模块(6)的电压输入端VCC_3.3与ARM Cortex核微处理器的核心控制模块(1)的电压输出端VCC_3.3连接;Profibus模块(6)的接地端GND 与ARM Cortex核微处理器的核心控制模块(1)的接地端GND连接。 The Profibus data terminal DB[0:7] and the address terminal AB[8:15] of the Profibus controller of the Profibus module (6) are respectively connected with the Profibus data terminal of the Profibus interface of the core control module (1) of the ARM Cortex core microprocessor /Address terminal PIE[0:7], address terminal PIE[8:15] are connected, the data terminal of Profibus interface/address terminal PIE[0:7], address terminal PIE[8:15] are respectively connected with ARM Cortex core microprocessing The Profibus data terminal/address terminal PIE[0:7] and address terminal PIE[8:15] of the ARM Cortex core microprocessor of the core control module (1) of the controller are connected; the Profibus of the Profibus controller of the Profibus module (6) Read control terminal RD3, Profibus write control terminal WR3, Profibus address latch control terminal ALE3, Profibus interrupt output terminal XINT, Profibus reset terminal PF_RESET are respectively connected to Profibus control of the Profibus interface of the core control module (1) of the ARM Cortex core microprocessor The signal I/O ports PD15, PD14, PD13, PE4, PA0 are connected, and the Profibus control signal I/O ports PD15, PD14, PD13, PE4, PA0 of the Profibus interface are respectively connected with the core control module of the ARM Cortex core microprocessor (1) The Profibus control signal I/O ports PD15, PD14, PD13, PE4, PA0 of the ARM Cortex core microprocessor are connected; the voltage input terminal VCC_3.3 of the Profibus module (6) is connected with the core control module ( 1) The voltage output terminal VCC_3.3 is connected; the ground terminal GND of the Profibus module (6) is connected to the ground terminal GND of the core control module (1) of the ARM Cortex core microprocessor. 7.根据权利要求1所述一种模块式多数据转换装置的转换方法,其特征在于:该转换方法包括以下步骤: 7. The conversion method of a modular multi-data conversion device according to claim 1, characterized in that: the conversion method comprises the following steps: 1)ARM Cortex核微处理器的核心控制模块(1)上电初始化,完成模块式多数据转换装置的初始化程序和数据的加载,并将SRAM存储器的存储空间划分为:蓝牙、Zigbee、CAN、RS485、Profibus、RS232等数据通讯收发通道的缓存区; 1) The core control module of the ARM Cortex core microprocessor (1) Power-on initialization, complete the initialization program and data loading of the modular multi-data conversion device, and divide the storage space of the SRAM memory into: Bluetooth, Zigbee, CAN, Buffer areas for data communication transceiver channels such as RS485, Profibus, and RS232; 2)用户通过设置键盘模块,对模块式多数据转换装置的各通讯模块的硬件参数进行配置,并执行相应通讯子程序的使能或屏蔽操作; 2) The user configures the hardware parameters of each communication module of the modular multi-data conversion device by setting the keyboard module, and executes the enabling or shielding operation of the corresponding communication subroutine; 3)将各通讯模块的配置参数存储在EEPROM存储器内; 3) Store the configuration parameters of each communication module in the EEPROM memory; 4)执行使能通讯模块的初始化子程序,完成其硬件配置参数的设置; 4) Execute the initialization subroutine that enables the communication module to complete the setting of its hardware configuration parameters; 5)模块式多数据转换装置的数据转换与控制程序由数据帧的中断接收子程序、多数据转换处理子程序、以及轮询数据转发传输子程序等三部分组成,其中中断接收子程序负责对蓝牙模块(2)、Zigbee模块(3)、CAN模块(4)、RS485模块(5)、Profibus模块(6)、RS232等通讯模块的数据帧进行接收,根据ARM Cortex核微处理器中各模块的中断的优先等级,实现相应各通讯模块的接收数据的处理;多数据转换处理子程序负责对接收到的数据帧按照目的地地址进行检测,并按照发送的地址,依次将接受的数据帧存储到SRAM存储器各相应的数据通讯发送通道的缓存区内;轮询数据转发传输子程序则负责对SRAM存储器内的各个数据通讯发送通道的缓存区的头、尾指针是否相等进行检测,如果数据通讯发送通道的缓存区的头、尾指针不相等,依次将数据通讯发送通道的缓存区中的数据发送到各通讯模块的发送缓冲区内。 5) The data conversion and control program of the modular multi-data conversion device consists of three parts: the interrupt receiving subroutine of the data frame, the multi-data conversion processing subroutine, and the polling data forwarding and transmission subroutine, among which the interrupt receiving subroutine is responsible for Bluetooth module (2), Zigbee module (3), CAN module (4), RS485 module (5), Profibus module (6), RS232 and other communication modules receive data frames, according to each module in the ARM Cortex core microprocessor The priority level of the interrupt, to realize the processing of the received data of the corresponding communication modules; the multi-data conversion processing subroutine is responsible for detecting the received data frame according to the destination address, and sequentially storing the received data frame according to the sent address to the buffer area of each corresponding data communication transmission channel in the SRAM memory; the polling data forwarding transmission subroutine is responsible for detecting whether the head and tail pointers of the buffer areas of each data communication transmission channel in the SRAM memory are equal. The head and tail pointers of the buffer area of the sending channel are not equal, and the data in the buffer area of the data communication sending channel are sent to the sending buffers of each communication module in sequence.
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