CN103295965B - The manufacture method of semiconductor structure - Google Patents
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- CN103295965B CN103295965B CN201210053855.1A CN201210053855A CN103295965B CN 103295965 B CN103295965 B CN 103295965B CN 201210053855 A CN201210053855 A CN 201210053855A CN 103295965 B CN103295965 B CN 103295965B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 100
- 238000000034 method Methods 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 230000001020 rhythmical effect Effects 0.000 claims abstract description 37
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 34
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 32
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 32
- 230000001360 synchronised effect Effects 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 128
- 238000010276 construction Methods 0.000 claims description 85
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- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 8
- 150000004767 nitrides Chemical group 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 7
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
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- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 6
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- 229920005591 polysilicon Polymers 0.000 description 4
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- 238000000231 atomic layer deposition Methods 0.000 description 3
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- 238000002955 isolation Methods 0.000 description 3
- 229910005883 NiSi Inorganic materials 0.000 description 2
- 229910010037 TiAlN Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
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- 229910010038 TiAl Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
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- PXNDALNSUJQINT-UHFFFAOYSA-N [Sc].[Ta] Chemical compound [Sc].[Ta] PXNDALNSUJQINT-UHFFFAOYSA-N 0.000 description 1
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
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- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
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- 238000004151 rapid thermal annealing Methods 0.000 description 1
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- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
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- 229910021324 titanium aluminide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A manufacture method for semiconductor structure, comprising: on the PMOS, nmos transistor region of Semiconductor substrate, form first, second rhythmic structure of the fence, and it comprises gate dielectric layer, grid layer, first, second hard mask, forms side wall in its relative both sides; Form SiGe stressor layer in the region of the pre-formed PMOS transistor source and drain of substrate, then remove the second hard mask; PMOS, nmos pass transistor source and drain areas form silicide, then synchronous metallic contact material layer and the first hard mask removing remnants; The side wall of first, second rhythmic structure of the fence both sides is etched, makes its reduced thickness.In manufacturing process, can not cause due to side wall be etched before above grid layer hard mask thickness inconsistent cause PMOS, silicide in nmos pass transistor source and drain is by too much etching or hard mask is caused transistor gate height to reduce by too much grinding in follow-up chemical mechanical milling tech problem.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly relate to a kind of manufacture method of semiconductor structure.
Background technology
A popular tendency in modern integrated circuits manufacture produces to have the transistor of very small-feature-size, and transistor mostly comprise by material be the gate dielectric layer of silica (or silicon oxynitride etc.), material is the laminated construction that the grid of polysilicon is formed.Along with transistor size becomes more and more less, there is many problems in transistor, and as grid current leakage, depletion of polysilicon, boron penetration effects etc., these all have impact on further developing of integrated circuit.For solving the problem, people have studied a kind of novel transistor: the material of gate dielectric layer is replaced with includes high-k dielectric (K here refers to a kind of dielectric constant) by silica, the material of grid is replaced with metal by polysilicon by it, thus substantially increases the performance of integrated circuit.
The performance how improving transistor is to greatest extent the target that technical field of semiconductors is persisted in the ambition, because stress can change energy gap and the charge carrier (electronics in nmos pass transistor of silicon materials, hole in PMOS transistor) mobility, the channel region therefore by stress being applied to transistor becomes more and more conventional means with the performance improving transistor.Described stress can utilize stress film (stressfilm) to produce.Such as, the U.S. patent documents that name is called " EmbeddedStressedNitrideLinersforCMOSPerformanceImproveme nt ", publication number is US20050258515 discloses a kind of by forming nitride liner (NitrideLiner) to improve the method for carrier mobility above transistor.As shown in Figure 1, Semiconductor substrate 1 is formed with transistor, it comprises the rhythmic structure of the fence be made up of gate dielectric layer 2, grid layer 3, hard mask 4, the side wall 5 be formed on rhythmic structure of the fence sidewall, is positioned at the source and drain 6 of rhythmic structure of the fence both sides, the material of side wall 5 is generally silicon nitride, silicon oxynitride etc., and channel region 7 is between source and drain 6.The top of transistor is coated with nitride liner 8 (being foregoing stress film), and namely the top of source and drain 6, rhythmic structure of the fence is covered by nitride liner 8.Nitride liner 8 can produce stress to the channel region 7 of transistor.Stress neighbour technology (StressProximityTechnique, SPT) shows, when stress film is larger the closer to the stress acted on channel region during the channel region of transistor.
By suitable proof stress, the carrier mobility of transistor can be improved, and then improve drive current, greatly improve the performance of transistor with this.Generally speaking, for nmos pass transistor, wish to produce tension stress (tensilestress) at source electrode to the channel region of drain directions, and for PMOS transistor, it is desirable to produce compression (compressivestress) at source electrode to the channel region of drain directions.Therefore, PMOS transistor requires not identical with the stress of nmos pass transistor.
For PMOS transistor, embedded silicon germanium technologies (EmbeddedSiGeTechnology) also can be adopted to produce compression with the channel region at transistor, and then improve carrier mobility.So-called embedded silicon germanium technologies refers to embedding silicon germanium material in the Semiconductor substrate of next-door neighbour's PMOS transistor channel region, because the lattice between silicon with SiGe (SiGe) is not identical, therefore can produce compression to channel region.
In view of above-mentioned reason, prior art proposes a kind of manufacture method of semiconductor structure comprising PMOS transistor, nmos pass transistor, and the method utilizes stress film and embedded silicon germanium technologies to improve the carrier mobility of transistor.Particularly, described manufacture method comprises:
As shown in Figure 2, Semiconductor substrate 10 is provided, it comprises PMOS transistor region (being positioned on the left of Semiconductor substrate), nmos transistor region (being positioned on the right side of Semiconductor substrate), PMOS transistor overlying regions is formed above first grid laminated construction 11, nmos transistor region and is formed with second gate laminated construction 12, first grid laminated construction 11, second gate laminated construction 12 comprise gate dielectric layer 13, grid layer 14, hard mask 15 from the bottom to top successively, and the material of hard mask 15 generally adopts silicon nitride.The relative both sides of first grid laminated construction 11, second gate laminated construction 12 are formed with side wall 16.
As shown in Figure 3, above the nmos transistor region of Semiconductor substrate 10, form mask 17, as photoresist, make its completely masked 17 coverings.Then, utilize the technique of dry etching or wet etching or both combinations to form groove (recess) in the region of the pre-formed PMOS transistor source and drain of Semiconductor substrate 10, after forming groove, in groove, form SiGe stressor layer 18.The formation method of SiGe stressor layer 18 is preferably selective epitaxial growth (SelectiveEpitaxyGrowth, SEG) method.
As shown in Figure 4, remove the mask 17 above nmos transistor region, deposit layer of metal contact material layer 19 over the semiconductor substrate 10, as Ni, then carry out annealing in process, make part metals contact material layer 19 and silicon react and generate silicide, as NiSi.
As shown in Figure 5, remove the metallic contact material layer 19 that Semiconductor substrate 10 does not react with silicon, now, only have the source and drain (not shown) of the SiGe stressor layer 18 of PMOS transistor, nmos pass transistor top to be formed with silicide 20.
As previously mentioned, according to stress neighbour technology, larger stress is applied to improve the performance of transistor further to the channel region of transistor for making the stress film above PMOS transistor, nmos pass transistor, can make first grid laminated construction 11, second gate laminated construction 12 both sides side wall 16 thickness h thinning, to make stress film can closer to the channel region of transistor.
Given this, as shown in Figure 6, the side wall 16 of first grid laminated construction 11, second gate laminated construction 12 is etched, make its thickness h as shown in Figure 5 be thinned to h ' in Fig. 6 to remove part side wall.Then, as shown in Figure 7, form stress film 21, interlayer dielectric layer 22 successively over the semiconductor substrate 10, chemico-mechanical polishing (CMP) process is carried out until expose the surface of grid layer 14 in first grid laminated construction 11, second gate laminated construction 12 to it.
As shown in Figure 3, a kind of phenomenon is there will be: the hard mask 15 exposed in first grid laminated construction 11 can be caused its thickness to reduce by gas or etchant, corrosion while etched recesses, growth SiGe stressor layer 18, because second gate laminated construction 12 masked 17 covers, therefore, the thickness of the hard mask 15 in second gate laminated construction 12 remains unchanged, and causes the variable thickness of the hard mask 15 in the thickness of the hard mask 15 in first grid laminated construction 11 and second gate laminated construction 12 to cause.In actual fabrication process, a kind of even more serious phenomenon is that hard mask 15 in first grid laminated construction 11 likely can be completely removed and causes the grid layer 14 below hard mask 15 to come out, after metallic contact material layer 19 shown in causing in the diagram, the top of grid layer 14 also can form silicide 20, silicide on grid layer 14 is difficult to be removed so that likely can remain in first grid laminated construction 11, thus affects the performance of transistor.
After thinning side wall, according to the needs of subsequent technique, the hard mask in first grid laminated construction, second gate laminated construction also needs to be completely removed.Because mask hard in the process of etching side wall also can be etched, for making the manufacture craft of semiconductor structure simplify the most, therefore wish to realize removing hard mask, thinning side wall completely in an etching process simultaneously.But in view of as previously mentioned: before thinning side wall, the thickness of the hard mask in first grid laminated construction and second gate laminated construction is also inconsistent, synchronous remove hard mask, thinning side wall time can there is following problem:
As shown in Figure 5, in the process of thinning side wall 16, etching agent or etching gas can etch the silicide 20 above PMOS transistor and nmos pass transistor source and drain simultaneously, and shown in composition graphs 3, in second gate laminated construction 12, the thickness of hard mask 15 is greater than the thickness of hard mask 15 in first grid laminated construction 11, if when thinning side wall 16, the hard mask 15 that will realize in second gate laminated construction 12 is completely removed (the hard mask 15 now in first grid laminated construction 11 also can be completely removed) simultaneously, then hard etch period needed for mask 15 can lengthen, the time that silicide 20 above transistor source and drain is etched also lengthens thereupon, cause the silicide loss in transistor source and drain too much, affect the performance of semiconductor structure, if the hard mask 15 that will realize in first grid laminated construction 11 is completely removed when thinning side wall 16 simultaneously, hard mask 15 then in second gate laminated construction 12 has residual, as shown in Figure 6, at this moment for making the manufacture craft of semiconductor structure simplify the most, wish in cmp (CMP) processing procedure as shown in Figure 7, residual hard mask 15 to be removed in the lump, for guaranteeing that the hard mask 15 remained can be completely removed, often milled processed was carried out to semiconductor structure, cause first grid laminated construction 11, grid layer 14 in second gate laminated construction 12 is also polished, its thickness is reduced, cause PMOS transistor, the gate height of nmos pass transistor reduces, affect the performance of semiconductor structure.
Summary of the invention
The problem to be solved in the present invention is to provide a kind of manufacture method of semiconductor structure comprising PMOS transistor, nmos pass transistor, can not cause synchronously realizing thinning rhythmic structure of the fence side wall, silicide when removing hard mask above PMOS transistor and nmos pass transistor source and drain is by too much etching or hard mask is caused transistor gate height to reduce by too much grinding in follow-up chemical mechanical milling tech problem when utilizing the method to form semiconductor structure.
For solving the problems of the technologies described above, the semiconductor structure manufacture method in the present invention comprises:
There is provided Semiconductor substrate, it comprises PMOS transistor region, nmos transistor region;
The PMOS transistor region of described Semiconductor substrate forms first grid laminated construction, nmos transistor region is formed second gate laminated construction, first, second rhythmic structure of the fence described comprises gate dielectric layer, be positioned at grid layer above gate dielectric layer, be positioned at the hard mask of first above grid layer, be positioned at the second hard mask above the first hard mask, at the relative both sides formation side wall of first, second rhythmic structure of the fence described;
Form SiGe stressor layer in the region of the pre-formed PMOS transistor source and drain of described Semiconductor substrate, then clean, remove the second hard mask in first, second rhythmic structure of the fence described, the first hard mask below the second hard mask is come out;
After cleaning, form metallic contact material layer and carry out annealing in process, to form silicide on the source and drain areas of PMOS transistor, nmos pass transistor, then synchronous metallic contact material layer and the first hard mask removing remnants;
The side wall of first, second rhythmic structure of the fence both sides described is etched, to remove part side wall, makes its reduced thickness;
Form stress film, then form interlayer dielectric layer, carry out planarization until expose the surface of grid layer in first, second rhythmic structure of the fence;
Remove the grid layer in first, second rhythmic structure of the fence, gate dielectric layer to form groove, in described groove, fill includes high-k dielectric, metal gate material layer successively.
Alternatively, the material of the described first hard mask is Al
2o
3or TiN or TaN or WSi.
Alternatively, the thickness of the described first hard mask is
Alternatively, the material of the described second hard mask is silica or silicon nitride.
Alternatively, the thickness of the described second hard mask is
Alternatively, the material of described metallic contact material layer is Ni/Pt or Co.
Alternatively, the step forming SiGe stressor layer in the region of the pre-formed PMOS transistor source and drain of described Semiconductor substrate comprises:
The region except PMOS transistor region of described Semiconductor substrate forms mask;
Sigma type groove is formed in the region of the pre-formed PMOS transistor source and drain of described Semiconductor substrate;
Selective epitaxial growth process is utilized to form SiGe stressor layer in described sigma type groove.
Alternatively, the material of described stress film is nitride.
Alternatively, the material of described stress film is silicon nitride.
Compared with prior art, the invention has the advantages that:
Before the side wall of rhythmic structure of the fence etches in semiconductor structure, the first hard mask in rhythmic structure of the fence on PMOS transistor region and nmos transistor region above grid layer, the second hard mask are removed all, can not cause due to side wall be etched before silicide above grid layer above the inconsistent PMOS transistor that causes of hard mask thickness and nmos pass transistor source and drain by too much etching or hard mask is caused transistor gate height to reduce by too much grinding in follow-up chemical mechanical milling tech problem.And when the material of the first hard mask be silica or silicon nitride time, the first hard mask can synchronously can be removed in the cleaning step above transistor source and drain before Formation of silicide, when the material of the second hard mask is Al
2o
3or during TiN or TaN or WSi, the second hard mask can synchronously can be removed in the cleaning step above transistor source and drain after Formation of silicide, achieves the simplification of semiconductor structure manufacture craft.
In addition; on the PMOS transistor region of Semiconductor substrate when etched recesses, formation SiGe stressor layer; although the second hard mask can be etched, corrode in the rhythmic structure of the fence on PMOS transistor region; but the first hard mask below the second hard mask is difficult to be etched, corrode or be etched, corrode less; make the grid layer below the second hard mask can not expose and form silicide, so that affect the performance of transistor.
Accompanying drawing explanation
By the more specifically explanation of the preferred embodiment shown in accompanying drawing, above-mentioned purpose of the present invention, Characteristics and advantages will be more clear.Accompanying drawing not drawn on scale, focus on purport of the present invention is shown, in the accompanying drawings for clarity sake, be exaggerated the size in layer and region.
Fig. 1 is existing a kind of by forming nitride liner to improve the method schematic diagram of transistor carrier mobility above transistor.
Fig. 2 to Fig. 7 is the structural representation of existing a kind of semiconductor structure in manufacturing process.
Fig. 8 is the Making programme figure of semiconductor structure in one embodiment of the present of invention.
Fig. 9 to Figure 20 is the structural representation of semiconductor structure in manufacturing process in an embodiment of semiconductor structure manufacture method of the present invention.
Embodiment
The problem to be solved in the present invention is to provide a kind of manufacture method of semiconductor structure comprising PMOS transistor, nmos pass transistor, can not cause synchronously realizing thinning rhythmic structure of the fence side wall, silicide when removing hard mask above PMOS transistor and nmos pass transistor source and drain is by too much etching or hard mask is caused transistor gate height to reduce by too much grinding in follow-up chemical mechanical milling tech problem when utilizing the method to form semiconductor structure.
For solving the problem, the present invention forms first grid laminated construction, on nmos transistor region, forms second gate laminated construction on the PMOS transistor region of Semiconductor substrate, and first, second rhythmic structure of the fence comprises gate dielectric layer, grid layer, the first hard mask, the second hard mask from the bottom to top successively.By selecting the first suitable hard mask material, second hard mask material, to make in semiconductor structure before the side wall of rhythmic structure of the fence etches, the first hard mask in rhythmic structure of the fence on PMOS transistor region and nmos transistor region above grid layer, second hard mask is removed all, can not cause due to side wall be etched before silicide above grid layer above the inconsistent PMOS transistor that causes of hard mask thickness and nmos pass transistor source and drain by too much etching, or the problem that hard mask is caused transistor gate height to reduce by too much grinding in follow-up chemical mechanical milling tech.
Below in conjunction with accompanying drawing, by specific embodiment, carry out clear, complete description to technical scheme of the present invention, obviously, described embodiment is only a part for embodiment of the present invention, instead of they are whole.According to these embodiments, those of ordinary skill in the art's obtainable other execution modes all under without the need to the prerequisite of creative work, all belong to protection scope of the present invention.
Fig. 8 is the Making programme figure of semiconductor structure in an embodiment of semiconductor structure manufacture method of the present invention.As shown in Figure 8, described manufacture method comprises:
Step S100: provide Semiconductor substrate, it comprises PMOS transistor region, nmos transistor region.
Step S102: form first grid laminated construction on PMOS transistor region, form second gate laminated construction on nmos transistor region, first, second rhythmic structure of the fence comprises gate dielectric layer, grid layer, the first hard mask, the second hard mask from the bottom to top successively, forms side wall in the relative both sides of first, second rhythmic structure of the fence.
Step S104: form SiGe stressor layer in the region of the pre-formed PMOS transistor source and drain of Semiconductor substrate.
Step S106: thoroughly clean Semiconductor substrate, removes the second hard mask in first grid laminated construction, second gate laminated construction, the first hard mask below the second hard mask is come out.
Step S108: form metallic contact material layer on a semiconductor substrate and carry out annealing in process, to form silicide on the source and drain areas of PMOS transistor, nmos pass transistor, then, synchronous metallic contact material layer and the first hard mask removing remnants.
Step S110: the side wall of first grid laminated construction, second gate laminated construction both sides is etched, to remove part side wall, makes its reduced thickness.
Step S112: form stress film on a semiconductor substrate, to give PMOS transistor or nmos pass transistor channel region stress application.
Step S114: form interlayer dielectric layer on a semiconductor substrate, carry out planarization until expose the surface of grid layer in first grid laminated construction, second gate laminated construction, then remove the grid layer in first, second rhythmic structure of the fence, gate dielectric layer to form groove, in groove, fill includes high-k dielectric, metal gate material layer successively.
Fig. 9 to Figure 20 is the structural representation of semiconductor structure in manufacturing process in an embodiment of semiconductor structure manufacture method of the present invention.Below Fig. 9 to Figure 20 is combined with Fig. 8 and the manufacture method of semiconductor structure is described.
First the step S100 in Fig. 8 is performed: provide Semiconductor substrate, it comprises PMOS transistor region, nmos transistor region.
As shown in Figure 9, Semiconductor substrate 30 can be body silicon (bulksilicon) substrate or silicon-on-insulator (silicon-on-insulator) substrate.Alternatively, in Semiconductor substrate 30, also can comprise other material, as germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs, gallium antimonide etc.Certainly, the material of Semiconductor substrate 30 can also be other suitable backing material.The preformed semiconductor structure of the present invention at least comprises the transistor of a pair complementation, namely at least comprises a PMOS transistor, a nmos pass transistor, and therefore, Semiconductor substrate 30 at least needs to comprise a PMOS transistor region, a nmos transistor region.In the present embodiment to make the semiconductor structure only comprising a PMOS transistor, nmos pass transistor, in other embodiments, multiple (two or more) PMOS transistor, multiple (two or more) nmos pass transistor can be made in the semiconductor substrate simultaneously simultaneously.Isolation structure 9 can be formed, to define the active region of Semiconductor substrate in Semiconductor substrate 30.It is fleet plough groove isolation structure (ShallowTrenchIsolation, STI) that this isolation structure 9 can be.
Then perform as the step S102 in Fig. 8: on PMOS transistor region, form first grid laminated construction, on nmos transistor region, form second gate laminated construction, first, second rhythmic structure of the fence comprises gate dielectric layer, grid layer, the first hard mask, the second hard mask from the bottom to top successively, forms side wall in the relative both sides of first, second rhythmic structure of the fence.
As shown in Figure 10, the PMOS transistor region of Semiconductor substrate 30 forms first grid laminated construction 31, the nmos transistor region of Semiconductor substrate 30 formed second gate laminated construction 32, first grid laminated construction 31, second gate laminated construction 32 comprise gate dielectric layer 33, be positioned at grid layer 34 above gate dielectric layer 33, be positioned at the hard mask 35 of first above grid layer 34, be positioned at the second hard mask 36 above the first hard mask 35.The material of gate dielectric layer 33 can be the suitable dielectric material such as silica, and it can utilize the formation such as thermal oxidation method, atomic layer deposition method (AtomicLayerDeposition, ALD).The material of grid layer 34 can be polysilicon.The hard mask 36 of first hard mask 35, second is for graphical grid layer 34, gate dielectric layer 33.After forming first grid laminated construction 31, second gate laminated construction 32, Semiconductor substrate 30 deposits the material layer of one deck for the formation of rhythmic structure of the fence (first grid laminated construction, second gate laminated construction) side wall, then etch this material layer, the material layer remained on first grid laminated construction 31, second gate laminated construction 32 sidewall forms the side wall 37 of rhythmic structure of the fence.The material of side wall 37 can be the conventional spacer material such as silicon nitride, silicon oxynitride.In another embodiment of the present invention, after the relative both sides of first grid laminated construction 31, second gate laminated construction 32 form side wall 37, one deck side wall can be formed again in the side of side wall 37, so that the making of subsequent technique.
Then perform as the step S104 in Fig. 8: form SiGe stressor layer in the region of the pre-formed PMOS transistor source and drain of Semiconductor substrate.
SiGe stressor layer is formed to improve the carrier mobility of PMOS transistor at the channel region of next-door neighbour's PMOS transistor for utilizing embedded silicon germanium technologies (EmbeddedSiGeTechnology), as shown in figure 11, the nmos transistor region of Semiconductor substrate 30 forms mask 38, mask 38 is covered above second gate laminated construction 32 and side wall 37 thereof.The material of mask 38 can be photoresist.
The mode forming SiGe stressor layer in the region of the pre-formed PMOS transistor source and drain of Semiconductor substrate 30 has multiple.In one embodiment of the invention, first can form groove (recess) in the region of the pre-formed PMOS transistor source and drain of Semiconductor substrate 30, the shape of groove can be square, U-shaped, sigma (∑) type etc., preferably, the shape of groove is sigma type, this shape distance reduced between PMOS transistor source and drain makes the stress being applied to transistor channel region effectively increase, and then improves the performance of transistor.After forming groove, in groove, form SiGe stressor layer 39, then to implanting p-type dopant in SiGe stressor layer 39, as B.The formation method of groove is dry etching (being applicable to square or U-shaped groove) or dry etching, wet etching combines (being applicable to sigma type groove).The formation method of SiGe stressor layer 39 is preferably selective epitaxial growth method (SelectiveEpitaxyGrowth).The SiGe stressor layer 39 be formed in groove is the source and drain of PMOS transistor.In another embodiment of the present invention, first can be formed the source and drain of PMOS transistor by ion implantation technology, then above this source and drain, form SiGe stressor layer 39, the same like this effect reaching raising transistor carrier mobility.In other embodiments, also SiGe stressor layer is formed by alternate manner in the region of the pre-formed source and drain of Semiconductor substrate.
While etched recesses, formation SiGe stressor layer, gas or etching agent may etch the second hard mask 36 exposed in first grid laminated construction 31, and hard mask 36 thickness of second in first grid laminated construction 31 is reduced.Because second gate laminated construction 32 masked 38 covers, the thickness of the in second gate laminated construction 32 second hard mask 36 can remain unchanged.For ensureing that the first hard mask 35 that the second hard mask 36 can not be etched completely away so that be positioned at below the second hard mask 36 in the process of etched recesses, formation SiGe stressor layer exposes, preferably, the thickness of the second hard mask 36 is
after forming SiGe stressor layer 39, remove the mask 38 above nmos transistor region.
Eliminate the forming process of nmos pass transistor source and drain in this step, the technique that this manufacturing process is well known to those skilled in the art, therefore be not repeated herein, protection scope of the present invention should do not limited with this.
Then perform the step S106 in Fig. 8: Semiconductor substrate is thoroughly cleaned, remove the second hard mask in first grid laminated construction, second gate laminated construction, the first hard mask below the second hard mask is come out.
Form silicide above the source and drain of PMOS transistor, nmos pass transistor before, thoroughly need clean Semiconductor substrate, to remove staining and oxide of semiconductor substrate surface.When the material of the second hard mask 36 is chosen as silica or silicon nitride, in the process of cleaning Semiconductor substrate 30, in first grid laminated construction, second gate laminated construction second hard mask 36 can synchronously be removed, the the first hard mask 35 be positioned at below the second hard mask 36 is come out, achieves the simplification of semiconductor structure manufacture craft.So far the semiconductor structure formed as shown in figure 12.The reason that in first grid laminated construction 31, second gate laminated construction 32 first hard mask 35 is come out is convenient in subsequent step S108, first hard mask 35 synchronously can be removed, to simplify the manufacture craft of semiconductor structure with metal material layer residual in Semiconductor substrate.
Then the step S108 in Fig. 8 is performed: form metallic contact material layer on a semiconductor substrate and carry out annealing in process, to form silicide on the source and drain areas of PMOS transistor, nmos pass transistor, then, synchronous metallic contact material layer and the first hard mask removing remnants.
As shown in figure 13, Semiconductor substrate 30 forms metallic contact material layer 40.The material of metallic contact material layer 40 can be Ni/Pt or Co etc., and it can utilize sputtering technology to be formed.When the material of metallic contact material layer 40 is Ni/Pt, refer to that material is doped with Pt in the metallic contact material layer of Ni.Then carry out annealing in process to it, preferably, this annealing treating process is short annealing process (RapidThermalAnnealing).High temperature makes part metals contact material layer 40 react with the silicon in Semiconductor substrate 30 and generate silicide, another part metallic contact material layer can not react, as the metallic contact material layer 40 above the first hard mask 35 in first grid laminated construction 31, second gate laminated construction 32.As shown in figure 14, remove the metallic contact material layer remaining in Semiconductor substrate 30 surface, the source and drain of transistor is formed silicide 41.When the material of the first hard mask 35 is Al
2o
3or during TiN or TaN or WSi, while removing residual metallic contact material layer 40, the first hard mask 35 also can synchronously be removed, and achieves the simplification of semiconductor structure manufacture craft, and can not cause loss to established silicide 41.In one embodiment, the material of metallic contact material layer 40 is Ni/Pt, the material of the first hard mask 35 is Al
2o
3, can H be utilized
2sO
4with H
2o
2mixed solution realize residual metallic contact material layer 40 and the synchronous removal of the first hard mask 35, and H
2sO
4with H
2o
2mixed solution can not cause damage to NiSi (silicide that Ni and pasc reaction are formed).
It should be noted that, in step before this step S108, nmos pass transistor source and drain (not shown) makes formation, therefore, except the SiGe stressor layer 39 on PMOS transistor source and drain areas is formed except silicide 41, the source and drain areas (not shown) of nmos pass transistor is also formed with silicide 41, and silicide 41 can improve the performance of transistor.For making the first hard mask 35 more easily be removed, to shorten the removal time, to reduce the fabrication cycle of semiconductor structure, the thickness of the first hard mask 35 can be made to be
Then the step S110 in Fig. 8 is performed: the side wall of first grid laminated construction, second gate laminated construction both sides is etched, to remove part side wall, makes its reduced thickness.
As previously mentioned, according to stress neighbour technology (StressProximityTechnique, SPT), for making the stress film that formed above PMOS transistor, nmos pass transistor apply larger stress to improve the performance of transistor further to the channel region of transistor, first grid laminated construction 31 can be made, the side wall 37 thickness h as shown in Figure 14 of second gate laminated construction 32 both sides is thinned to the h ' (h > h ') shown in Figure 15.
Then the step S112 in Fig. 8 is performed: form stress film on a semiconductor substrate, to give PMOS transistor or nmos pass transistor channel region stress application.
As shown in figure 16, Semiconductor substrate 30 forms stress film 42, first grid laminated construction 31 or second gate laminated construction 32 are covered by stress film 42.Stress film 42 can pair pmos transistor, nmos pass transistor channel region produce stress, to improve the carrier mobility of transistor.The material of stress film 42 can be nitride, as Si
3n
4.(stress needed for PMOS transistor is compression to stress difference needed for PMOS transistor, nmos pass transistor channel region, stress needed for nmos pass transistor is tension stress), therefore the stress film of unlike material can be formed as required on PMOS transistor, nmos pass transistor, or when forming the stress film of identical material on PMOS transistor, nmos pass transistor, because stress film may make the stress in one of them transistor channel region weaken, the stress film on this transistor can be removed as required.
Finally perform the step S114 in Fig. 8: form interlayer dielectric layer on a semiconductor substrate, carry out planarization until expose the surface of grid layer in first grid laminated construction, second gate laminated construction, then remove the grid layer in first, second rhythmic structure of the fence, gate dielectric layer to form groove, in groove, fill includes high-k dielectric, metal gate material layer successively.
As shown in figure 17, stress film 42 forms interlayer dielectric layer 43, its material can be silica.
As shown in figure 18, planarization is carried out until expose the surface of grid layer 34 in first grid laminated construction 31, second gate laminated construction 32 to the Semiconductor substrate being formed with interlayer dielectric layer 43.Described planarization technique can be chemico-mechanical polishing (CMP).
Then, as shown in figure 19, grid layer 34, the gate dielectric layer 33 in first grid laminated construction 31, second gate laminated construction 32 is removed, to form groove G.
As shown in figure 20, in groove G, fill includes high-k dielectric 44, its material can be the suitable high-k dielectric material such as hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum, lead niobate zinc.Then, in groove G, fill metal gate material layer 45, its material can be Ta (tantalum), TaN (tantalum nitride), TaC (ramet), W (tungsten), WN (tungsten nitride), Al (aluminium), TiAl (titanium aluminide), TiAlN (TiAlN), TiN (titanium nitride).Metal gate material layer needed for PMOS transistor is different from the metal gate material layer 45 needed for nmos pass transistor.The metal gate material layer of PMOS transistor and nmos pass transistor need be selected as required.
In sum, compared with prior art, the invention has the advantages that:
Before the side wall of rhythmic structure of the fence etches in semiconductor structure, the first hard mask in rhythmic structure of the fence on PMOS transistor region and nmos transistor region above grid layer, the second hard mask are removed all, can not cause due to side wall be etched before silicide above grid layer above the inconsistent PMOS transistor that causes of hard mask thickness and nmos pass transistor source and drain by too much etching or hard mask is caused transistor gate height to reduce by too much grinding in follow-up chemical mechanical milling tech problem.And when the material of the first hard mask be silica or silicon nitride time, the first hard mask can synchronously can be removed in the cleaning step above transistor source and drain before Formation of silicide, when the material of the second hard mask is Al
2o
3or during TiN or TaN or WSi, the second hard mask can synchronously can be removed in the cleaning step above transistor source and drain after Formation of silicide, achieves the simplification of semiconductor structure manufacture craft.
In addition; on the PMOS transistor region of Semiconductor substrate when etched recesses, formation SiGe stressor layer; although the second hard mask can be etched, corrode in the rhythmic structure of the fence on PMOS transistor region; but the first hard mask below the second hard mask is difficult to be etched, corrode or be etched, corrode less; make the grid layer below the second hard mask can not expose and form silicide, so that affect the performance of transistor.
Above by the explanation of embodiment, professional and technical personnel in the field should be able to be made to understand the present invention better, and can reproduce and use the present invention.Those skilled in the art can be apparent to above-described embodiment do various changes and modifications when not departing from the spirit and scope of the invention according to principle described herein.Therefore, the present invention should not be understood to be limited to above-described embodiment shown in this article, and its protection range should be defined by appending claims.
Claims (8)
1. a manufacture method for semiconductor structure, is characterized in that, described manufacture method comprises:
There is provided Semiconductor substrate, it comprises PMOS transistor region, nmos transistor region;
The PMOS transistor region of described Semiconductor substrate forms first grid laminated construction, nmos transistor region is formed second gate laminated construction, first, second rhythmic structure of the fence described comprises gate dielectric layer, be positioned at grid layer above gate dielectric layer, be positioned at the hard mask of first above grid layer, be positioned at the second hard mask above the first hard mask, form side wall in the relative both sides of first, second rhythmic structure of the fence described, the material of the described first hard mask is Al
2o
3or TiN or TaN or WSi;
Form SiGe stressor layer in the region of the pre-formed PMOS transistor source and drain of described Semiconductor substrate, then clean, remove the second hard mask in first, second rhythmic structure of the fence described, the first hard mask below the second hard mask is come out;
After cleaning, form metallic contact material layer and carry out annealing in process, to form silicide on the source and drain areas of PMOS transistor, nmos pass transistor, then synchronous metallic contact material layer and the first hard mask removing remnants;
The side wall of first, second rhythmic structure of the fence both sides described is etched, to remove part side wall, makes its reduced thickness;
Form stress film, then form interlayer dielectric layer, carry out planarization until expose the surface of grid layer in first, second rhythmic structure of the fence;
Remove the grid layer in first, second rhythmic structure of the fence, gate dielectric layer to form groove, in described groove, fill includes high-k dielectric, metal gate material layer successively.
2. manufacture method according to claim 1, is characterized in that, the thickness of the described first hard mask is
3. manufacture method according to claim 1, is characterized in that, the material of the described second hard mask is silica or silicon nitride.
4. manufacture method according to claim 1, is characterized in that, the thickness of the described second hard mask is
5. manufacture method according to claim 1, is characterized in that, the material of described metallic contact material layer is Ni/Pt or Co.
6. manufacture method according to claim 1, is characterized in that, the step forming SiGe stressor layer in the region of the pre-formed PMOS transistor source and drain of described Semiconductor substrate comprises:
The region except PMOS transistor region of described Semiconductor substrate forms mask;
Sigma type groove is formed in the region of the pre-formed PMOS transistor source and drain of described Semiconductor substrate;
Selective epitaxial growth process is utilized to form SiGe stressor layer in described sigma type groove.
7. manufacture method according to claim 1, is characterized in that, the material of described stress film is nitride.
8. manufacture method according to claim 7, is characterized in that, the material of described stress film is silicon nitride.
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