CN103295895B - A kind of lithographic method improving self-aligned silicide barrier layer step effect - Google Patents
A kind of lithographic method improving self-aligned silicide barrier layer step effect Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 142
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 55
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 55
- 230000004888 barrier function Effects 0.000 title claims abstract description 51
- 230000000694 effects Effects 0.000 title claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 144
- 230000008569 process Effects 0.000 claims abstract description 85
- 239000004065 semiconductor Substances 0.000 claims abstract description 66
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 238000007781 pre-processing Methods 0.000 claims abstract description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 28
- 239000003595 mist Substances 0.000 claims description 16
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 10
- 229910052731 fluorine Inorganic materials 0.000 claims description 10
- 239000011737 fluorine Substances 0.000 claims description 10
- 230000001360 synchronised effect Effects 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 239000004215 Carbon black (E152) Substances 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 229930195733 hydrocarbon Natural products 0.000 claims description 5
- 150000002430 hydrocarbons Chemical class 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 description 20
- 239000010408 film Substances 0.000 description 14
- 238000000151 deposition Methods 0.000 description 11
- 230000008021 deposition Effects 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 8
- 238000009826 distribution Methods 0.000 description 6
- 238000009616 inductively coupled plasma Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 230000009467 reduction Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000002985 plastic film Substances 0.000 description 3
- 229920006255 plastic film Polymers 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000011002 quantification Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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Abstract
The invention provides a kind of lithographic method improving self-aligned silicide barrier layer step effect in semiconductor device layer, this self-aligned silicide barrier layer is type silicon oxide, comprise preliminary treatment and main etching two processes, preprocessing process comprises: form the plasma with isotropic etching ability; The plasma with isotropic etching ability is utilized to carry out selective etch to the top of the stepped area on self-aligned silicide barrier layer; Main etching process comprises: form the plasma with anisotropic etching ability; Utilize the plasma with anisotropic etching ability to the top of the stepped area on self-aligned silicide barrier layer, sidewall and bottom carry out near-synchronous etc. speed etching.Lithographic method of the present invention, effectively can remove the step effect on self-aligned silicide barrier layer, realize the uniform fold on self-aligned silicide barrier layer, to reduce the difficulty that successive process removes self-aligned silicide barrier layer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, be specifically related to a kind of lithographic method improving self-aligned silicide barrier layer step effect.
Background technology
In fabrication of semiconductor device, after formation semiconductor device layer, need to form metal silicide in specific region, for reducing contact resistance.In the process, usually need to adopt self-aligned silicide to generate barrier layer (Self-alignedsilicideblocklayer, SAB) and protect region semiconductor device layer not needing to be formed metal silicide.Industry now widely used self-aligned silicide scheme silica type SAB layer and the combined SAB layer of silica/silicon nitride.For silica SAB layered scheme, desirable SAB layer film has uniform Step Coverage, that is to say at each part thickness of step even, to reduce the technology difficulty of successive process.
But, along with the development of semiconductor technology, dimensions of semiconductor devices reduces gradually, spacing between live width and live width becomes more and more narrow, type silicon oxide SAB layer is caused to occur covering non-uniform phenomenon in semiconductor device layer, be called step effect, this is because the load effect of film deposition rate at different pattern density area causes, this can cause the step formed in semiconductor device layer to occur that cover film is uneven, the deposited atop speed of such as grid is larger, and deposition rate is less on base semiconductor device layer between grid, thus this step bottom deposit of Thickness Ratio large of the film of the top surface deposition of step that formed of area of grid, refer to Fig. 1, Fig. 1 is the step effect schematic diagram that the self-aligned silicide barrier film of chemical vapour deposition (CVD) is formed, Semiconductor substrate 1 ' is provided with grid 2 ', be positioned at the divider wall 3 ' of grid 2 ' two side, and cover grid 2 ' top and sidewall surfaces, with the self-aligned silicide barrier layer 4 ' in Semiconductor substrate 1 '.As shown in Figure 1, self-aligned silicide barrier layer 4 ' defines step on grid 2 ' top and sidewall surfaces and Semiconductor substrate 1 ', the thickness being positioned at the self-aligned silicide barrier film at step top is greater than the thickness bottom it, thus causes and cover uneven phenomenon.Particularly when critical size is decreased to below 65nm, gate distance in semiconductor device layer is very little, grid arrangement is intensive, this is by more remarkable for step effect when causing self-aligned silicide barrier film to deposit, the step formed after the self-aligned silicide barrier deposition of such as 55nm product, the top thickness of the stepped area on self-aligned silicide barrier layer is 338A, and the thickness of the bottom of the stepped area on self-aligned silicide barrier layer is 263A, top and bottom thickness difference 100A.
According to the preparation technology of semiconductor device, after self-aligned silicide barrier layer is formed, to etch it thus make it reach presetting thickness, but, if directly carry out conventional etching technics, due to the existence of step effect, after etching, the thickness of step top and bottom still differs greatly, if the thickness of bottom reaches default thickness, then the thickness at top does not also reach, and causes successive process cannot remove this self-aligned silicide barrier layer completely, make this region to form metal silicide, cause component failure; If the thickness at top reaches default thickness, then the thickness of bottom will be less than preset thickness, and cause the source electrode of active area or the damage of drain electrode, make device performance offset design index, this all can badly influence the performance of resulting devices.Therefore, in etching technics after formation self-aligned silicide barrier layer, it is extremely important and necessary for obtaining uniform self-aligned silicide barrier layer, this just has higher requirement to the etching technics on self-aligned silicide barrier layer, how can eliminate step effect, obtaining ideal etching result is one of key issue.
Summary of the invention
For above-mentioned Problems existing, the object of the invention is to the etching technics improving type silicon oxide self-aligned silicide barrier layer, eliminate its step effect, thus obtain the self-aligned silicide barrier layer of uniform fold.
The invention provides a kind of lithographic method improving self-aligned silicide barrier layer step effect in semiconductor device layer, that described semiconductor device layer comprises Semiconductor substrate, the grid formed on the semiconductor substrate and covers grid 2 top and sidewall surfaces and described self-aligned silicide barrier layer in Semiconductor substrate 1, wherein, described self-aligned silicide barrier layer is type silicon oxide, described lithographic method comprises preliminary treatment and main etching two processes
Described preprocessing process comprises:
First, the plasma with isotropic etching ability is formed;
Then, selective etch is carried out at the top of plasma to the stepped area on described self-aligned silicide barrier layer described in utilization with isotropic etching ability;
Described main etching process comprises:
First, the plasma with anisotropic etching ability is formed;
Then, there is described in utilization the top of plasma to the stepped area on described self-aligned silicide barrier layer of anisotropic etching ability, sidewall and bottom and carry out the speed etchings such as synchronous.
Preferably, in described preprocessing process, described selective etch is greater than etch rate to mesa sidewall and bottom, until the difference of the top of described stepped area and bottom thickness is 40A-60A to the etch rate at the top of described stepped area.
Preferably, in described main etching process, the speed such as synchronous etches the top of described stepped area, sidewall and bottom, until the top of described stepped area and the thickness of bottom reach predetermined value.
Preferably, the substrate bias power that described preprocessing process adopts is 0-100W, plasma source power is 500-2000W, uses the total flow of etching gas to be 100-500mTorr for 500-1000sccm and process atmospheric pressures simultaneously, thus obtains and have the plasma of isotropic etching ability.
Preferably, etching gas described in described preprocessing process is CF
4, NF
3or SF
6, or itself and Ar or O
2mist.
Preferably, described main etching process adopts substrate bias power to be 100-1500W, and plasma source power is 200-2000W, and the total flow of the etching gas simultaneously used is 100-500sccm, and process atmospheric pressures is 10-100mTorr, thus obtain the plasma with anisotropic etching ability.
Preferably, etching gas described in described main etching process adopts the fluorine-based or hydrocarbon fluorine base gas of carbon and Ar and O
2mist.
Preferably, the plasma generator that is separated with substrate bias power of described lithographic method using plasma source power.
A kind of lithographic method improving type silicon oxide self-aligned silicide barrier layer step effect in semiconductor device layer of the present invention, adopt preliminary treatment and main etching two processes, due to step effect, self-aligned silicide barrier layer is greater than bottom step in step top thickness, therefore, through preprocessing process, produce the plasma of isotropic etching ability, isotropic plasma is utilized to be greater than the diffusion rate bottom step in the diffusion rate of step top area, thus realize being greater than bottom step to the etch rate at the top of stepped area, and the correction to step, then, through main etching process, produce the plasma with anisotropic etching ability, because the diffusion rate of anisortopicpiston is not by the restriction of space density, basically identical in the diffusion rate at any position of step, therefore can realize, to speed etchings such as the near-synchronous of step top, sidepiece and bottom, avoiding again occurring step effect.By above-mentioned two processes, effectively can remove the step effect on type silicon oxide self-aligned silicide barrier layer, realize the uniform fold on type silicon oxide self-aligned silicide barrier layer.
Accompanying drawing explanation
Fig. 1 is the step effect schematic diagram that the type silicon oxide self-aligned silicide barrier film of chemical vapour deposition (CVD) is formed
Fig. 2 is the process chart of the lithographic method on type silicon oxide self-aligned silicide barrier layer in semiconductor device layer of a preferred embodiment of the present invention
Fig. 3 is the ledge structure schematic diagram covering the type silicon oxide self-aligned silicide barrier layer in semiconductor device layer of above-mentioned preferred embodiment of the present invention
Fig. 4-5 is type silicon oxide self-aligned silicide barrier layer ledge structure schematic cross-sections corresponding to each preparation process of the lithographic method of above-mentioned preferred embodiment of the present invention
Fig. 6 is the process chart of the lithographic method on type silicon oxide self-aligned silicide barrier layer in semiconductor device layer of another preferred embodiment of the present invention
Fig. 7 is the process chart of the lithographic method on type silicon oxide self-aligned silicide barrier layer in semiconductor device layer of another preferred embodiment of the present invention
Embodiment
The embodiment embodying feature & benefits of the present invention describes in detail in the explanation of back segment.Be understood that the present invention can have various changes in different examples, it neither departs from the scope of the present invention, and explanation wherein and being shown in essence when the use explained, and be not used to limit the present invention.
In semiconductor fabrication, be divided into wet method and dry etching, dry etching is that processed substrate is placed in plasma, and under the bombardment be corrosive at band, had certain energetic ion, reaction generates gaseous material, removes the film that is etched.Normal employing has inductively coupled plasma (ICP), transformation coupling plasma (TCP) at present, capacitiveiy coupled plasma (CCP) lithographic technique etc., because it has the advantage that independently can control ion concentration and ion energy, become dry etching technology ideal at present.What the present invention adopted is the plasma generator of the plasma generator that plasma source power is separated with substrate bias power, all uncouplings, all can be applied in the present invention than ICP, TCP, CCP described above etc.
Below in conjunction with accompanying drawing 2-7, by specific embodiment, a kind of lithographic method improving self-aligned silicide barrier layer step effect in semiconductor device layer of the present invention is described in further detail.It should be noted that, accompanying drawing all adopt simplify very much form, use non-ratio accurately, and only in order to object that is convenient, that reach the aid illustration embodiment of the present invention lucidly.
Embodiment 1
As previously mentioned, no matter adopt physical vapour deposition (PVD) or chemical vapor deposition film, semiconductor device layer top bar distribution comparatively dense region inevitably produce step effect problem, namely film causes in the variable thickness of each several part of step, causes plastic film covering uneven.The product that lithographic method of the present invention is applied can be any semiconductor device product, can be applied in any semiconductor device layer, the present embodiment of the present invention is with 55nm high pressure (highvoltage, HV) product, and thickness is the silicon dioxide (SiO deposited with the tetraethoxysilane (PETEOS) that plasma is strengthened of 600A
2) SAB layer is that the lithographic method of example to the SAB of improvement layer step effect of the present invention does detailed explanation and illustrate, but this is not used in and limits the scope of the invention.
The lithographic method improving SAB layer step effect in semiconductor device layer below in conjunction with Fig. 2-5 pairs of the present embodiment is further described, Fig. 3 is the SAB layer ledge structure schematic diagram covered in semiconductor device layer of the present embodiment of the present invention, and Fig. 4-5 is SAB layer ledge structure schematic cross-sections corresponding to each preparation process of the lithographic method of the present embodiment of the present invention.
Refer to Fig. 2, Fig. 2 is the schematic flow sheet improving the lithographic method of SAB layer step effect in semiconductor device layer of the present embodiment of the present invention.The SiO by PETEOS deposition of the semiconductor device layer adopted in the present embodiment of the present invention to be 55HV product and thickness be 600A
2sAB layer, refer to Fig. 3, Fig. 3 is the SAB layer ledge structure schematic diagram covered in semiconductor device layer of a preferred embodiment of the present invention, the grid 2 that this semiconductor device layer comprises Semiconductor substrate 1, formed in this Semiconductor substrate 1 and cover grid 2 top and sidewall surfaces and type silicon oxide SAB layer 3 in Semiconductor substrate 1, the silica here in the present embodiment is SiO
2.As can be seen from Figure 3, the thickness at the top of the stepped area of SAB layer is greater than the thickness bottom stepped area, and in the etching technics of reality, for the 55HV product in the present embodiment, and thickness is the SiO by PETEOS deposition of 600A
2sAB layer, if adopt chemical vapor deposition SiO
2sAB layer, the SiO of deposition
2sAB layer is greater than 150A in the thickness difference of stepped area top and bottom, and the present embodiment, is described lithographic method of the present invention for 150A for this difference, and this is not used in and limits the scope of the invention.
The lithographic method of the present embodiment of the present invention comprises preliminary treatment and main etching two processes.
First carry out preprocessing process, comprising:
Step S11: form the plasma with isotropic etching ability;
Forming the Method and process condition with the plasma of isotropic etching ability has a variety of, can regulate and use different technological parameters, reached the object of the plasma producing isotropic etching ability according to different plasma generators.The etching gas adopted in preprocessing process in the present invention can be CF
4, NF
3or SF
6, or itself and Ar, O
2, N
2deng the mist of assist gas, the plasma generator adopted in the present embodiment is ICP, the substrate bias power adopted is 0-100W, plasma source power is 500-2000W, process atmospheric pressures is 100-500mTorr, the total flow of the etching gas used is 500-1000sccm, and etching gas can be, but not limited to be CF
4and O
2mist, this is not used in and limits the scope of the invention.
Step S12: refer to Fig. 4, utilizes the above-mentioned top of plasma to the stepped area of SAB layer with isotropic etching ability chemically to etch; This is the characteristic that the plasma itself owing to having isotropic etching ability has, it is greater than the diffusion rate bottom intensive step in the diffusion rate of the step top area of spaciousness, thus can realize being greater than mesa sidewall and bottom to the etch rate at the top of stepped area, thus reach the object that step is revised; The thickness at step top is greater than the thickness of mesa sidewall and bottom, step top etching ratio sidewall and bottom all want fast, this will reduce the thickness difference of step top and bottom, in the etching technics of reality, suitable technological parameter and time can be selected according to the thickness difference of step top and bottom, in the present embodiment, the thickness difference of step top and bottom is 150A, the technological parameter in above-mentioned steps S11 is adopted to etch SAB layer, till the thickness difference of step top and bottom is 40-60A, can be 40A especially.Here it should be noted that, due to the top of step, sidewall and bottom etch at the same time, in this step, etch rate due to top is greater than the etch rate of bottom, in etching process, the thickness difference of top and bottom is in continuous reduction, simultaneously, top, the thickness of sidewall and bottom is also in continuous reduction, because etch rate is also subject to the impact of some uncertain factors, cannot precise quantification etch rate, this just cannot make top and bottom thickness difference almost close to while zero, guarantee that the thickness of whole sidewall is also still greater than predetermined thickness, likely cause this thickness difference also not close to zero time, the thickness of top or sidewall or bottom is close to zero, or more serious etches in semiconductor device layer, cause the failure of whole technique, therefore, in actual etching process, according to the process of whole etching technics, in this preprocessing process, thickness difference can not close to zero, the numerical value that thickness difference reaches suitable should be made, this is also guarantee carrying out smoothly of follow-up main etching process.Therefore, etching the top of stepped area and bottom until thickness difference is 40A-60A in the preprocessing process in the present embodiment, can be 40A.
Then, carry out main etching process to comprise:
Step S21: form the plasma with anisotropic etching ability;
Forming the Method and process condition with the plasma of anisotropic etching ability has a variety of, can regulate and use different technological parameters, reached the object of the plasma producing anisotropic etching ability according to different plasma generators.The etching gas that main etching process in the present invention adopts can be the fluorine-based or hydrocarbon fluorine base gas of carbon and Ar and O
2deng the mist of assist gas, the plasma generator adopted in the present embodiment is ICP, adopt substrate bias power to be 100-1500W, plasma source power is 200-2000W, process atmospheric pressures is 10-100mTorr, the total flow of the etching gas used is 100-500sccm, and etching gas can be, but not limited to be CF
4, Ar and O
2mist, this is not used in and limits the scope of the invention.
Step S22: refer to Fig. 5, utilizes the above-mentioned top of plasma to the stepped area of SAB layer, sidewall and the bottom with anisotropic etching ability to carry out the speed etchings such as synchronous, until the top of described stepped area and the thickness of bottom reach predetermined value.Here, predetermined value can set according to actual requirement or object.Due to the impact of the distribution that the diffusion rate with the plasma of anisotropic etching ability is not topped bar by semiconductor device layer, the diffusion rate of its top at step, sidewall and bottom is substantially close, therefore can in step top, sidewall and bottom the speed etching such as simultaneously, guarantee that the difference of the thickness of the SAB layer at each position of step can not increase, again avoiding the generation of step effect, the thickness at each position of last step reaches predetermined value and stops etching.
Embodiment 2
As previously mentioned, no matter adopt physical vapour deposition (PVD) or chemical vapor deposition film, semiconductor device layer top bar distribution comparatively dense region inevitably produce step effect problem, namely film causes in the variable thickness of each several part of step, causes plastic film covering uneven.The product that lithographic method of the present invention is applied can be any semiconductor device product, can be applied in any semiconductor device layer, the present embodiment of the present invention is with 55nm complementary metal oxide semiconductors (CMOS) sensor devices (CMOSimagesensor, CIS) product, and thickness is silicon rich oxide layer (Silicon-richoxide, the SRO) SiO of 400A
2sAB layer is that the lithographic method of example to the SAB of improvement layer step effect of the present invention does detailed explanation and illustrate, but this is not used in and limits the scope of the invention.
The lithographic method improving type silicon oxide SAB layer (SAB) step effect in semiconductor device layer provided in the present embodiment of the present invention, the semiconductor device layer of employing is 55nmCIS product, and thickness is the SROSiO of 400A
2sAB layer.In the etching technics of reality, for the 55nmCIS product in the present embodiment, and thickness is the SROSiO of 400A
2sAB layer, if adopt chemical vapor deposition this SAB layer, this SAB layer of deposition is greater than 80A in the thickness difference of stepped area top and bottom, the present embodiment for this difference for 80A, be described lithographic method of the present invention, this is not used in and limits the scope of the invention.
Below in conjunction with Fig. 6, the lithographic method improving SAB layer step effect in semiconductor device layer of the present embodiment is further described.
Refer to Fig. 6, Fig. 6 is the schematic flow sheet improving the lithographic method of SAB layer step effect in semiconductor device layer of the present embodiment of the present invention, and the lithographic method of the present embodiment of the present invention comprises preliminary treatment and main etching two processes.
First carry out preprocessing process, comprising:
Step S11: form the plasma with isotropic etching ability;
Forming the Method and process condition with the plasma of isotropic etching ability has a variety of, can regulate and use different technological parameters, reached the object of the plasma producing isotropic etching ability according to different plasma generators.The etching gas that preprocessing process in the present invention adopts can be CF
4, NF
3or SF
6, or itself and Ar, O
2, N
2deng the mist of assist gas, the substrate bias power used can be 0-100W, the plasma generator adopted in the present embodiment is TCP, the substrate bias power adopted is 0W, plasma source power is 500-2000W, process atmospheric pressures is 100-500mTorr, and the total flow of the etching gas used is 500-1000sccm, and etching gas can be, but not limited to be SF
6gas or SF
6with O
2mist, this is not used in and limits the scope of the invention.
Step S12: utilize the above-mentioned top of plasma to the stepped area of SAB layer with isotropic etching ability chemically to etch; This is the characteristic that the plasma itself owing to having isotropic etching ability has, it is greater than the diffusion rate bottom intensive step in the diffusion rate of the step top area of spaciousness, thus can realize being greater than mesa sidewall and bottom to the etch rate at the top of stepped area, thus reach the object that step is revised; The thickness at step top is greater than the thickness of mesa sidewall and bottom, step top etching ratio sidewall and bottom all want fast, this will reduce the thickness difference of step top and bottom, in the etching technics of reality, suitable technological parameter and time can be selected according to the thickness difference of step top and bottom, in the present embodiment, the thickness difference of step top and bottom is 80A, the technological parameter in above-mentioned steps S11 is adopted to etch SAB layer, till the thickness difference of step top and bottom is 40A.Here it should be noted that, due to the top of step, sidewall and bottom etch at the same time, in this step, etch rate due to top is greater than the etch rate of bottom, in etching process, the thickness difference of top and bottom is in continuous reduction, simultaneously, top, the thickness of sidewall and bottom is also in continuous reduction, because etch rate is also subject to the impact of some uncertain factors, cannot precise quantification etch rate, this just cannot make top and bottom thickness difference almost close to while zero, guarantee that the thickness of whole sidewall is also still greater than predetermined thickness, likely cause this thickness difference also not close to zero time, the thickness of top or sidewall or bottom is close to zero, or more serious etches in semiconductor device layer, cause the failure of whole technique, therefore, in actual etching process, according to the process of whole etching technics, in this preprocessing process, thickness difference can not close to zero, the numerical value that thickness difference reaches suitable should be made, this is also guarantee carrying out smoothly of follow-up main etching process.Therefore, the top of stepped area and bottom are etched until thickness difference is 40A in the preprocessing process in the present embodiment.
Then, carry out main etching process to comprise:
Step S21: form the plasma with anisotropic etching ability;
Forming the Method and process condition with the plasma of anisotropic etching ability has a variety of, can regulate and use different technological parameters, reached the object of the plasma producing anisotropic etching ability according to different plasma generators.The etching gas that main etching process of the present invention adopts can be the fluorine-based or hydrocarbon fluorine base gas of carbon and Ar and O
2deng the mist of assist gas, the plasma generator adopted in the present embodiment is ICP, the substrate bias power adopted is 100-1500W, plasma source power is 200-2000W, process atmospheric pressures is 10-100mTorr, the total flow of the etching gas used is 100-500sccm, and etching gas can be, but not limited to be CH
2f
2, Ar and O
2mist, this is not used in and limits the scope of the invention.
Step S22: utilize the above-mentioned top of plasma to the stepped area of SAB layer, sidewall and the bottom with anisotropic etching ability to carry out the speed etchings such as synchronous, until the top of described stepped area and the thickness of bottom reach predetermined value.Here, predetermined value can set according to actual requirement or object.Due to the impact of the distribution that the diffusion rate with the plasma of anisotropic etching ability is not topped bar by semiconductor device layer, the diffusion rate of its top at step, sidewall and bottom is substantially close, therefore can in step top, sidewall and bottom the speed etching such as simultaneously, guarantee that the difference of the thickness of the SAB layer at each position of step can not increase, again avoiding the generation of step effect, the thickness at each position of last step reaches predetermined value and stops etching.
Embodiment 3
As previously mentioned, no matter adopt physical vapour deposition (PVD) or chemical vapor deposition film, semiconductor device layer top bar distribution comparatively dense region inevitably produce step effect problem, namely film causes in the variable thickness of each several part of step, causes plastic film covering uneven.The product that lithographic method of the present invention is applied can be any semiconductor device product, can be applied in any semiconductor device layer, the present embodiment of the present invention is with 55nm flash memory (flash) product, and thickness is the SiO deposited with the tetraethoxysilane (PETEOS) that plasma is strengthened of 400A
2to be example do detailed explanation to the lithographic method improving self-aligned silicide barrier layer step effect of the present invention to SAB layer illustrates, but this is not used in and limits the scope of the invention.
The lithographic method improving SAB layer step effect in semiconductor device layer provided in the present embodiment of the present invention, the semiconductor device layer adopted is 55nmflash product, and thickness is the SiO of the PETEOS deposition of 400A
2sAB layer.In the etching technics of reality, for the 55nmflash product in the present embodiment, and thickness is the SiO of the PETEOS deposition of 400A
2sAB layer, if adopt chemical vapor deposition this SAB layer, this SAB layer of deposition is greater than 100A in the thickness difference of stepped area top and bottom, the present embodiment for this difference for 100A, be described lithographic method of the present invention, this is not used in and limits the scope of the invention.
Below in conjunction with Fig. 7, the lithographic method improving type silicon oxide SAB layer step effect in semiconductor device layer of the present embodiment is further described.
Refer to Fig. 7, Fig. 7 is the schematic flow sheet improving the lithographic method of SAB layer step effect in semiconductor device layer of the present embodiment of the present invention, and the lithographic method of the present embodiment of the present invention comprises preliminary treatment and main etching two processes.
First carry out preprocessing process, comprising:
Step S11: form the plasma with isotropic etching ability;
Forming the Method and process condition with the plasma of isotropic etching ability has a variety of, can regulate and use different technological parameters, reached the object of the plasma producing isotropic etching ability according to different plasma generators.The etching gas that in the present invention, preprocessing process adopts can be CF
4, NF
3or SF
6, or itself and Ar, O
2, N
2deng the mist of assist gas, the substrate bias power adopted is 0-100W, the plasma generator adopted in the present embodiment is CCP, the substrate bias power adopted is 0W, plasma source power is 500-2000W, process atmospheric pressures is 100-500mTorr, and the total flow of the etching gas used is 500-1000sccm, and etching gas can be, but not limited to be NF
3gas or NF
3with O
2mist, this is not used in and limits the scope of the invention.
Step S12: utilize the above-mentioned top of plasma to the stepped area of SAB layer with isotropic etching ability chemically to etch; This is the characteristic that the plasma itself owing to having isotropic etching ability has, it is greater than the diffusion rate bottom intensive step in the diffusion rate of the step top area of spaciousness, thus can realize being greater than mesa sidewall and bottom to the etch rate at the top of stepped area, thus reach the object that step is revised; The thickness at step top is greater than the thickness of mesa sidewall and bottom, step top etching ratio sidewall and bottom all want fast, this will reduce the thickness difference of step top and bottom, in the etching technics of reality, suitable technological parameter and time can be selected according to the thickness difference of step top and bottom, in the present embodiment, the thickness difference of step top and bottom is 100A, the technological parameter in above-mentioned steps S11 is adopted to etch SAB layer, till the thickness difference of step top and bottom is 40-60A, can be 40A especially.Here it should be noted that, due to the top of step, sidewall and bottom etch at the same time, in this step, etch rate due to top is greater than the etch rate of bottom, in etching process, the thickness difference of top and bottom is in continuous reduction, simultaneously, top, the thickness of sidewall and bottom is also in continuous reduction, because etch rate is also subject to the impact of some uncertain factors, cannot precise quantification etch rate, this just cannot make top and bottom thickness difference almost close to while zero, guarantee that the thickness of whole sidewall is also still greater than predetermined thickness, likely cause this thickness difference also not close to zero time, the thickness of top or sidewall or bottom is close to zero, or more serious etches in semiconductor device layer, cause the failure of whole technique, therefore, in actual etching process, according to the process of whole etching technics, in this preprocessing process, thickness difference can not close to zero, the numerical value that thickness difference reaches suitable should be made, this is also guarantee carrying out smoothly of follow-up main etching process.Therefore, the top of stepped area and bottom are etched until thickness difference is 40A-60A in the preprocessing process in the present embodiment.
Then, carry out main etching process to comprise:
Step S21: form the plasma with anisotropic etching ability;
Forming the Method and process condition with the plasma of anisotropic etching ability has a variety of, can regulate and use different technological parameters, reached the object of the plasma producing anisotropic etching ability according to different plasma generators.The etching gas that this main etching process in the present invention adopts can be the fluorine-based or hydrocarbon fluorine base gas of carbon and Ar and O
2deng the mist of assist gas, the plasma generator adopted in the present embodiment is ICP, the substrate bias power adopted is 100-1500W, plasma source power is 0-2000W, process atmospheric pressures is 0-100mTorr, the total flow of the etching gas used is 0-500sccm, and etching gas can be, but not limited to be CHF
3, Ar and O
2mist, this is not used in and limits the scope of the invention.
Step S22: utilize the above-mentioned top of plasma to the stepped area of SAB layer, sidewall and the bottom with anisotropic etching ability to carry out the speed etchings such as synchronous, until the top of described stepped area and the thickness of bottom reach predetermined value.Here, predetermined value can set according to actual requirement or object.Due to the impact of the distribution that the diffusion rate with the plasma of anisotropic etching ability is not topped bar by semiconductor device layer, the diffusion rate of its top at step, sidewall and bottom is substantially close, therefore can in step top, sidewall and bottom the speed etching such as simultaneously, guarantee that the difference of the thickness of the SAB layer at each position of step can not increase, again avoiding the generation of step effect, the thickness at each position of last step reaches predetermined value and stops etching.
The lithographic method improving type silicon oxide SAB layer step effect in semiconductor device layer of the present invention, adopt preliminary treatment and main etching two processes, due to step effect, self-aligned silicide barrier layer is greater than bottom step in step top thickness, therefore, through preprocessing process, produce the plasma of isotropic etching ability, isotropic plasma is utilized to be greater than the diffusion rate bottom step in the diffusion rate of step top area, thus realize being greater than bottom step the etch rate at the top of stepped area, and the correction to step; Then, through main etching process, produce the plasma with anisotropic etching ability, because the diffusion rate of anisortopicpiston is not by the restriction of space density, basically identical in the diffusion rate at any position of step, therefore can realize, to the speed etching such as synchronous of step top, sidepiece and bottom, avoiding again occurring step effect.By above-mentioned two processes, effectively can remove the step effect on self-aligned silicide barrier layer, realize the uniform fold on self-aligned silicide barrier layer.
Above-describedly be only embodiments of the invention; described embodiment is also not used to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (8)
1. one kind is improved the lithographic method of self-aligned silicide barrier layer step effect in semiconductor device layer, that described semiconductor device layer comprises Semiconductor substrate, the grid formed on the semiconductor substrate and covers described top portions of gates and sidewall surfaces and described self-aligned silicide barrier layer in described Semiconductor substrate, it is characterized in that, described self-aligned silicide barrier layer is type silicon oxide, described lithographic method comprises preliminary treatment and main etching two processes
Described preprocessing process comprises:
First, the plasma with isotropic etching ability is formed;
Then, the top of plasma to the stepped area on described self-aligned silicide barrier layer described in utilization with isotropic etching ability chemically etches;
Described main etching process comprises:
First, the plasma with anisotropic etching ability is formed;
Then, there is described in utilization the top of plasma to the stepped area on described self-aligned silicide barrier layer of anisotropic etching ability, sidewall and bottom and carry out the speed etchings such as synchronous.
2. lithographic method according to claim 1, it is characterized in that, in described preprocessing process, describedly chemically to etch, that etch rate to mesa sidewall and bottom is greater than, until the difference of the top of described stepped area and bottom thickness is 40A-60A to the etch rate at the top of described stepped area.
3. lithographic method according to claim 1, it is characterized in that, in described main etching process, the described etching of the speed such as synchronously, that the top to described stepped area, sidewall are identical with the etch rate of bottom, until the top of described stepped area and the thickness of bottom reach target thickness.
4. the lithographic method according to claim 1,2 or 3, it is characterized in that, the substrate bias power that described preprocessing process adopts is 0-100W, plasma source power is 500-2000W, use the total flow of etching gas to be 100-500mTorr for 500-1000sccm and process atmospheric pressures simultaneously, thus obtain there is the plasma of isotropic etching ability.
5. the lithographic method according to claim 1,2 or 3, is characterized in that, the etching gas adopted in described preprocessing process is CF
4, NF
3or SF
6, or itself and Ar or O
2mist.
6. the lithographic method according to claim 1,2 or 3, it is characterized in that, described main etching process adopts substrate bias power to be 100-1500W, plasma source power is 200-2000W, the total flow of the etching gas simultaneously used is 100-500sccm, and process atmospheric pressures is 10-100mTorr, thus obtain the plasma with anisotropic etching ability.
7. the lithographic method according to claim 1,2 or 3, is characterized in that, the etching gas adopted in described main etching process adopts the fluorine-based or hydrocarbon fluorine base gas of carbon and Ar and O
2mist.
8. according to the lithographic method described in claim 7, it is characterized in that, the plasma generator that described lithographic method using plasma source power is separated with substrate bias power.
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|---|---|---|---|---|
| US6153483A (en) * | 1998-11-16 | 2000-11-28 | United Microelectronics Corp. | Method for manufacturing MOS device |
| US6350696B1 (en) * | 2000-09-28 | 2002-02-26 | Advanced Micro Devices, Inc. | Spacer etch method for semiconductor device |
| CN102110644A (en) * | 2009-12-23 | 2011-06-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing silicide alignment block (SAB) film of p-type metal-oxide semiconductor (PMOS) device |
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| US7015089B2 (en) * | 2002-11-07 | 2006-03-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to improve etching of resist protective oxide (RPO) to prevent photo-resist peeling |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153483A (en) * | 1998-11-16 | 2000-11-28 | United Microelectronics Corp. | Method for manufacturing MOS device |
| US6350696B1 (en) * | 2000-09-28 | 2002-02-26 | Advanced Micro Devices, Inc. | Spacer etch method for semiconductor device |
| CN102110644A (en) * | 2009-12-23 | 2011-06-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing silicide alignment block (SAB) film of p-type metal-oxide semiconductor (PMOS) device |
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