CN103268278B - Support the SRAM controller of polycaryon processor and follow the tracks of information processing method - Google Patents
Support the SRAM controller of polycaryon processor and follow the tracks of information processing method Download PDFInfo
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Abstract
The invention discloses a kind of SRAM controller supporting polycaryon processor and follow the tracks of information processing method, described SRAM is connected with some processors by the first data path and the second data path respectively, SRAM controller is connected with SRAM memory also by the first data path, and described SRAM controller includes: the filtering module, mixing module, SRAM Read-write Catrol module and the some control depositors being connected with filtering module, mixing module and SRAM Read-write Catrol module respectively that are sequentially connected and some status registers.The present invention is filtered by the tracking information sending multiprocessor and is mixed, effectively reduce the tracking information data amount needing storage, and improve memory element utilization rate when information followed the tracks of by SRAM memory storage multiprocessor, to reach the purpose of the multiprocessor tracking information as far as possible many with SRAM memory cell storage in limited chip.
Description
Technical field
The application relates to SRAM controller and technical field of data processing thereof, particularly relates to a kind of polycaryon processor of supporting
SRAM controller and tracking information processing method thereof.
Background technology
Middle and high end processor can export encoded track record information when normal execution application program mostly.This
A little track record information are after being saved, through decoding and the process of the debugging acid supporting with processor, and can be by processor
Internal instruction execution flow is truly reduced, thus reaches to be tracked processor running status the effect of record.With
The preservation of track record information and extraction, the early stage for application program debugs exploitation, and real-time when reality is applied of program
Monitoring, suffers from important meaning.
For preserving the encoded track record information that processor sends, integrated the depositing of chip internal both can be used
Storage module, it would however also be possible to employ the independent storage devices that chip exterior is supporting.The storage device using chip exterior independence stores
Track record information, its advantage is that memory capacity is big.Its shortcoming is to need to increase the defeated of a set of track record information on chip
Outgoing interface, and the speed of service that the transmission speed of this socket is required to processor matches, with reach to export in real time
Purpose.Using chip internal integrated memory modular to store track record information, its advantage is that storage speed is fast, and saves corresponding
Chip output interface.Its shortcoming is the memory module finite capacity being internally integrated, it is impossible to recording processor work time whole
Track record information.
Along with improving constantly of middle and high end processor speed, and increase chip pin and the chip manufacturing that causes and encapsulation
Continuing to increase of cost, the method using chip exterior storage device to preserve track record information becomes further to be difficult to.Adopt
Keep in processor track record information by the memory module that chip internal is integrated, be increasingly becoming the first-selection side of high speed processor
Case.In recent years, at a multiple processor of core Embedded, i.e. multi core chip, a new trend of processor development is become.
The processor that multi-core processor chip makes needs preserve keeps track of the data volume of information and is doubled and redoubled, and chip internal is integrated in addition
Memory module, capacity is by chip area and the physical constraints of power consumption, it is impossible to that does is the biggest so that how with less storage mould
The track record information that block storage is the most, one that becomes processor chips design has one of problem to be solved.
The processor of different families, such as series processors, the series processors of American I ntel company of ARM company of Britain
Deng, the track record information of its output is different.Every company all can be carried out not for the track record information of its processor
With the compression of degree, formed a set of for exporting and the data stream of storage.Have been disclosed for some in the prior art to tracking
The patent that record is compressed, such as, United States Patent (USP) US7058859 " Trace Reporting Method and System
(track record method and system) ", United States Patent (USP) US6918065 " Method for Compressing and
Decompressing Trace Information (method compressed and decompress tracking information) ", United States Patent (USP)
US7209058 " Trace Receiver Data Compression (track receiver data compression) " etc..Above-mentioned technical side
Case is all the compression method towards track record data stream, thus reaches the effect making the track record data volume of output as far as possible reduce
Really.
As a example by C*Core series processors, the track record inter-area traffic interarea of output, every fixing processor clock
In the cycle, by a set of parallel data bus line of fixing bit wide, by one group of track record information packet, deliver to chip internal integrated
In SRAM.This packet comprises two kinds of track record information: effectively keep track of information and invalid tracking information.It is responsible for depositing
The SRAM of storage tracking information, with same fixing processor clock cycle interval, is stored in storage by each packet received
In unit, no matter whether this packet comprises valid data.When processor normally works, containing effectively keeping track of information
Packet output entire packet in proportion be less, say, that the most invalid tracking information is deposited
Enter in SRAM.In multi core chip, this phenomenon just becomes apparent from.Due to the finite capacity of the integrated SRAM of chip internal, in a large number
The preservation of invalid tracking information not only wastes the SRAM memory cell of preciousness, too increases power consumption unnecessary for SRAM and opens
Pin.
The memorizer of original storage tracking information, another problem existed is: under multiprocessor memory module, whole
Individual memory space will be divided into some regions.The number in region needs the individual of the processor of preservation tracking information in being equal to chip
Number.The track record information of each processor, can only leave in the memory area of oneself correspondence.When chip normally works,
The memory area of oneself correspondence is stained with by the track record information that there will be certain processor, causes recording message part and loses
Lose, and memory area corresponding to another processor also has the most vacant situation to occur.This multiprocessor mean allocation is deposited
The method in storage space so that the valuable utilization rate step-down following the tracks of information storage space.Need in chip to preserve track record letter
The processor of breath is the most, and this situation is more susceptible to, and the utilization rate of SRAM is the lowest.
In sum, it is necessary to a kind of SRAM controller supporting polycaryon processor is provided and follows the tracks of information processing method
To solve the problems referred to above.
Summary of the invention
In view of this, the invention provides a kind of SRAM controller supporting polycaryon processor and follow the tracks of information processing side
Method.
To achieve these goals, the technical scheme that the embodiment of the present application provides is as follows:
A kind of SRAM controller supporting polycaryon processor, described SRAM is respectively by the first data path and the second data
Path is connected with some processors, and SRAM controller is connected with SRAM memory also by the first data path, and described SRAM is controlled
Device processed includes:
Filtering module, follows the tracks of information the need of preserving and following the tracks of for detecting in the packet that each processor sends
Information is the most effective, if the information of tracking is invalid without preservation or the information of tracking, then abandons this packet；
Mixing module, described mixing module is connected with filtering module, and the packet for being exported by filtering module is pressed parallel
The packet of multichannel is mixed by the sequencing arrived, and is converted into the effective data packets of single channel, and sends this valid data
Bag；
SRAM Read-write Catrol module, described SRAM Read-write Catrol module is connected with mixing module, is used for receiving mixing module
In effective data packets, and by mixed effective data packets write SRAM memory, be additionally operable to from SRAM memory read
The most stored effective data packets；
Some control depositors, described control depositor respectively with filtering module, mixing module and SRAM Read-write Catrol mould
Block is connected, and controls depositor and includes following the tracks of for configuring needs storage storage dispensing unit and the control of message handler
The startup of SRAM controller and the switch control unit of time-out；
Some status registers, described status register respectively with filtering module, mixing module and SRAM Read-write Catrol mould
Block is connected, and status register includes for indicating packet the number state storing to SRAM memory effective data packets number
Control unit.
As a further improvement on the present invention, described control depositor also includes information indicating unit, for each place
Reason device indicates containing the packet that there is a need to preservation and effective trace information.
As a further improvement on the present invention, described mixing module includes some data buffers and with one with whole
The data buffer read-out control circuit that data buffer is connected, described data buffer is used for storing effective data packets and storage
Buffered data packet number information, described data buffer read-out control circuit is for providing control information to data buffer.
As a further improvement on the present invention, the number of described data buffer is identical with the number of integrated processor.
As a further improvement on the present invention, described status register also includes for whether indicating each data buffer
It is filled with the data buffer status control unit of spilling situation.
Correspondingly, the tracking information processing method of a kind of SRAM controller supporting polycaryon processor, described method includes
Following steps:
S1, processor send the packet comprising tracking information；
S2, follow the tracks of information filtration, filtering module detect in each packet follow the tracks of information the need of preserve and with
Track information is the most effective, if the information of tracking is invalid without preservation or the information of tracking, then abandons this packet, if the information of tracking needs
Preserve and the information of tracking is effective, then send this packet, perform step S3；
S3, the mixing of tracking information, the packet that filtering module is exported by mixing module is by the parallel sequencing arrived
The packet of multichannel is mixed, is converted into the effective data packets of single channel, and sends this effective data packets；
S4, the effective data packets received in mixing module, and mixed effective data packets is write SRAM memory.
As a further improvement on the present invention, described step S2 also includes:
Indicate containing the packet that there is a need to preservation and effective trace information in each processor.
As a further improvement on the present invention, described step S3 also includes:
Data buffer read-out control circuit provides control information to data buffer；
Obtain data buffer storage effective data packets and store buffered data packet number information；
The data buffer that buffered data packet number is most is selected to be read out.
As a further improvement on the present invention, described step S3 also includes:
Indicate the number storing to SRAM memory effective data packets；
Indicate whether each data buffer is filled with the situation of spilling.
The method have the advantages that
The present invention supports the SRAM controller of polycaryon processor and follows the tracks of information processing method by sending out multiprocessor
The tracking information gone out filters and mixes, and effectively reduces the tracking information data amount needing storage, and improves SRAM and deposit
Memory element utilization rate during information followed the tracks of by reservoir storage multiprocessor, to reach to deposit by SRAM memory cell in limited chip
The purpose of the multiprocessor tracking information that storage is the most.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present application or technical scheme of the prior art, below will be to embodiment or existing
In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this
Some embodiments described in application, for those of ordinary skill in the art, on the premise of not paying creative work,
Other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the module diagram of the present invention one preferred implementation chips；
Fig. 2 is the module diagram of SRAM controller in the present invention one preferred implementation；
Fig. 3 is the workflow diagram of filtering module in the present invention one preferred implementation；
Fig. 4 is the module diagram of mixing module in the present invention one preferred implementation；
Fig. 5 is the particular flow sheet that in the present invention one preferred implementation, SRAM controller follows the tracks of information processing method.
Detailed description of the invention
For the technical scheme making those skilled in the art be more fully understood that in the application, real below in conjunction with the application
Execute the accompanying drawing in example, the technical scheme in the embodiment of the present application is clearly and completely described, it is clear that described enforcement
Example is only some embodiments of the present application rather than whole embodiments.Based on the embodiment in the application, this area is common
The every other embodiment that technical staff is obtained under not making creative work premise, all should belong to the application protection
Scope.
The invention discloses a kind of SRAM controller supporting polycaryon processor, SRAM respectively by the first data path and
Second data path is connected with some processors, and SRAM controller is connected with SRAM memory also by the first data path,
SRAM controller includes:
Filtering module, follows the tracks of information the need of preserving and following the tracks of for detecting in the packet that each processor sends
Information is the most effective, if the information of tracking is invalid without preservation or the information of tracking, then abandons this packet；
Mixing module, mixing module is connected with filtering module, arrives by parallel for the packet exported by filtering module
Sequencing the packet of multichannel is mixed, be converted into the effective data packets of single channel, and send this effective data packets；
SRAM Read-write Catrol module, SRAM Read-write Catrol module is connected with mixing module, for receiving in mixing module
Effective data packets, and mixed effective data packets is write SRAM memory, it is additionally operable to read from SRAM memory
The effective data packets of storage；
Some control depositors, control depositor respectively with filtering module, mixing module and SRAM Read-write Catrol module phase
Even, control depositor and include following the tracks of for configuring needs storage storage dispensing unit and the control SRAM control of message handler
The startup of device processed and the switch control unit of time-out；
Some status registers, status register respectively with filtering module, mixing module and SRAM Read-write Catrol module phase
Even, status register includes for indicating packet the number state control storing to SRAM memory effective data packets number
Unit.
Correspondingly, the invention also discloses the tracking information processing side of a kind of SRAM controller supporting polycaryon processor
Method, comprises the following steps:
S1, processor send the packet comprising tracking information；
S2, follow the tracks of information filtration, filtering module detect in each packet follow the tracks of information the need of preserve and with
Track information is the most effective, if the information of tracking is invalid without preservation or the information of tracking, then abandons this packet, if the information of tracking needs
Preserve and the information of tracking is effective, then send this packet, perform step S3；
S3, the mixing of tracking information, the packet that filtering module is exported by mixing module is by the parallel sequencing arrived
The packet of multichannel is mixed, is converted into the effective data packets of single channel, and sends this effective data packets；
S4, the effective data packets received in mixing module, and mixed effective data packets is write SRAM memory.
Ginseng Fig. 1 show the module diagram of the present invention one preferred implementation chips, and this chip has support multinuclear
The SRAM controller of processor.
The integrated some processor of chip internal 10 (processor 1, processor 2 ... processor n), one be used for storing tracking letter
The SRAM memory 20 of breath and a corresponding SRAM controller 30.Each processor 10 has parallel data to lead to
Road (the first path) is connected to SRAM controller, and the first path is responsible for transmitting the tracking information of each processor 10 to SRAM control
Device 30.Multiple processors 10 are shared a parallel bus data path (alternate path) and are connected to SRAM controller 30.SRAM
The tracking information of each processor that controller is responsible for coming the first tunnel carries out filtering and mixed processing, then writes
In SRAM memory.The read data request that SRAM controller response to be responsible for alternate path transmits, and store from SRAM
Device appropriate address obtains data and returns to send the processor of read request.SRAM controller should also contain some control depositors and
Status register, each processor can be read and write these by alternate path and control depositor and status register.
In the present invention, SRAM controller should include at least following functional circuit: information filtering module, many followed the tracks of by multiprocessor
Processor effective trace information mixing module, SRAM Read-write Catrol module, control and status register management module.
Specifically, ginseng Fig. 2 shown in, in present embodiment, SRAM controller 30 includes: filtering module 31, mixing module 32,
SRAM Read-write Catrol module 33, some control depositors 34 and some status registers 35.Wherein:
Filtering module 31 for detect the packet that each processor 10 sends is followed the tracks of information the need of preserving and
Tracking information is the most effective, if the information of tracking is invalid without preservation or the information of tracking, then abandons this packet.
Shown in ginseng Fig. 3, if needing to store the tracking information of certain processor, and this tracking information comprises valid data,
Then this tracking information packet can be spliced a processor beacon information, and is sent to follow-up mixing module；If certain
The tracking information that individual processor sends need not preserve, or the information of tracking is without valid data, and this packet will be lost
Abandon.
Judge that the tracking information of certain processor, the need of preservation, is by the specific control bit specifically controlling depositor
Determine.How to judge whether tracking information contains effective information, information packet format description part will be followed the tracks of below and make
Explain in detail.
The optimization that the SRAM controller that original chip internal is integrated is carried out by the present invention, adds effectively following the tracks of note
The filtering function of record information.Invalid information, after by SRAM controller identification, will no longer be stored into SRAM memory cell, thus save
Save substantial amounts of SRAM memory space.
Mixing module 32, mixing module is connected with filtering module, and the packet being used for exporting filtering module is by arriving parallel
The packet of multichannel is mixed by the sequencing come, and is converted into the effective data packets of single channel, and sends this effective data packets.
Shown in ginseng Fig. 4, in present embodiment, mixing module 32 includes some data buffers 321 and with one with whole
The data buffer read-out control circuit 322 that data buffer is connected, data buffer 321 is used for storing effective data packets and depositing
Storing up buffered data packet number information, data buffer read-out control circuit 322 is for providing control information to data buffer.
Wherein, the number of data buffer is identical with the number of integrated processor.
Mixing module is responsible for the tracking information packet with processor beacon information exported by filtering module, by arriving
Sequencing, the multichannel data bag arrived parallel is converted into single-pass data bag, is then forwarded to SRAM Read-write Catrol module.By
In the parallel multichannel effective data packets arrived, little time big during its data volume, and it is sent to the single channel number of SRAM Read-write Catrol module
According to bag, its bandwidth is fixing.
As a example by 4 core systems, the valid data path access mixing module that 4 tunnels are parallel, the effective data packets of every road input,
Can regard as random from the time.Under worst case, 4 tunnel effective data packets are input simultaneously to mixing module, and export and arrive
The packet of SRAM Read-write Catrol module, per clock cycle at most one.
In order to solve in this local time, input traffic is more than the problem of output stream, and this module should comprise some
Enough FIFO data buffers of the degree of depth, the number of data buffer is identical with the number of processor.One clock cycle
In, each data buffer can be stored in an effective data packets, can read an effective data packets simultaneously.Each data are delayed
Rush device and should comprise the information of a packet number currently buffered, inquire about for data buffer read-out control circuit.Number
According to buffer read-out control circuit each clock cycle from all data buffers, select a data buffer, read one
Individual effective data packets is sent to SRAM Read-write Catrol module.Its screening rule is, selects the number that buffered data packet number is most
It is read out according to buffer.
The present invention does not use partitioned storage mode, and uses mixing storage mode, be there is a need to preserve the place of tracking information
Whole SRAM memory cell shared by reason device, and the sequencing sent by effective trace information packet is sequentially stored in SRAM, from
And realize the maximized purpose of SRAM space utilisation.
SRAM Read-write Catrol module 33, SRAM Read-write Catrol module is connected with mixing module, is used for receiving in mixing module
Effective data packets, and by mixed effective data packets write SRAM memory, be additionally operable to read from SRAM memory
Stored effective data packets.
Control depositor 34, control depositor respectively with filtering module 31, mixing module 32 and SRAM Read-write Catrol module
33 are connected.
Control depositor 34 to specifically include:
For configuring the storage dispensing unit needing storage to follow the tracks of message handler；
Control startup and the switch control unit of time-out of SRAM controller；
To the information indicating list indicated containing the packet that there is a need to preservation and effective trace information in each processor
Unit.
Status register 35, status register respectively with filtering module 31, mixing module 32 and SRAM Read-write Catrol module
33 are connected.
Status register 35 specifically includes:
For indicating the packet number status unit storing to SRAM memory effective data packets number；
The data buffer status control unit of spilling situation whether it is filled with for indicating each data buffer.
SRAM controller in present embodiment can receive the tracking that at most 8 C*Core series processors send simultaneously
Information, automatic fitration hash, only store useful data, and store with the mixing storage mode of not subregion, reach
The maximized purpose of memory space utilization rate.
Different processor families, the tracking information packet that its processor sends is different.In order to improve storage sky
Between utilization rate, some processor can carry out compression in various degree and process the tracking information sent, the tracking information being saved,
Both can be the data stream through overcompression, it is also possible to be the data stream without compression, and the present invention had used filtration and mixes
The processing mode closed.
Ginseng Fig. 5 show in present embodiment the tracking information processing method of the SRAM controller supporting polycaryon processor
Particular flow sheet, comprises the following steps:
S1, processor send the packet comprising tracking information；
S2, follow the tracks of information filtration, filtering module detect in each packet follow the tracks of information the need of preserve and with
Track information is the most effective, if the information of tracking is invalid without preservation or the information of tracking, then abandons this packet, if the information of tracking needs
Preserve and the information of tracking is effective, then send this packet, perform step S3.This step also includes contain in each processor
The packet needing preservation and effective trace information indicates；
S3, the mixing of tracking information, the packet that filtering module is exported by mixing module is by the parallel sequencing arrived
The packet of multichannel is mixed, is converted into the effective data packets of single channel, and sends this effective data packets；
S4, the effective data packets received in mixing module, and mixed effective data packets is write SRAM memory.
Wherein, step S3 also includes:
Data buffer read-out control circuit provides control information to data buffer；
Obtain data buffer storage effective data packets and store buffered data packet number information；
The data buffer that buffered data packet number is most is selected to be read out.
In present embodiment, information packet followed the tracks of by the processor of indication, refer in particular to the series processors of C*Core company per time
The Parallel Tracking information data that the clock cycle is sent.So-called effective data packets, refers in particular to non-zero tracking information packet.Certainly exist
Can also follow the tracks of information data for other in other embodiments, effective data packets can also carry out difference according to the difference of data
Setting.
By technique scheme it can be seen that the present invention supports SRAM controller and the information of tracking thereof of polycaryon processor
Reason method is filtered by the tracking information sending multiprocessor and is mixed, and effectively reduces the tracking information needing storage
Data volume, and improve SRAM memory storage multiprocessor follow the tracks of information time memory element utilization rate, to reach with limited
Chip in the as far as possible many multiprocessor of SRAM memory cell storage follow the tracks of the purpose of information.
Device embodiments described above is only schematically, the wherein said unit illustrated as separating component
Can be or may not be physically separate, the parts shown as unit can be or may not be physics list
Unit, i.e. may be located at a place, or can also be distributed on multiple NE.Can be selected it according to the actual needs
In some or all of module realize the purpose of present embodiment scheme.Those of ordinary skill in the art are not paying creation
Property work in the case of, be i.e. appreciated that and real the application can be used for numerous general or special purpose computing system environment or configuration
In.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie
In the case of the spirit or essential attributes of the present invention, it is possible to realize the present invention in other specific forms.Therefore, no matter
From the point of view of which point, all should regard embodiment as exemplary, and be nonrestrictive, the scope of the present invention is by appended power
Profit requires rather than described above limits, it is intended that all by fall in the implication of equivalency and scope of claim
Change is included in the present invention.Should not be considered as limiting involved claim by any reference in claim.
Although moreover, it will be appreciated that this specification is been described by according to embodiment, but the most each embodiment only wraps
Containing an independent technical scheme, this narrating mode of description is only that for clarity sake those skilled in the art should
Description can also be formed those skilled in the art through appropriately combined as an entirety, the technical scheme in each embodiment
May be appreciated other embodiments.
Claims (4)
1. supporting a SRAM controller for polycaryon processor, described SRAM controller is respectively by the first data path and second
Data path is connected with some processors, and SRAM controller is connected with SRAM memory also by the first data path, its feature
Being, described SRAM controller includes:
Filtering module, follows the tracks of information the need of preserving and tracking information for detecting in the packet that each processor sends
The most effective, if the information of tracking is invalid without preservation or the information of tracking, then abandon this packet；
Mixing module, described mixing module is connected with filtering module, arrives by parallel for the packet exported by filtering module
Sequencing the packet of multichannel is mixed, be converted into the effective data packets of single channel, and send this effective data packets, its
In, described mixing module includes that some data buffers and the data buffer being connected with total data buffer with are read
Going out control circuit, described data buffer is used for storing effective data packets and storing buffered data packet number information, described number
According to buffer read-out control circuit for providing control information to data buffer, the number of described data buffer is with integrated
The number of processor is identical；
SRAM Read-write Catrol module, described SRAM Read-write Catrol module is connected with mixing module, for receiving in mixing module
Effective data packets, and mixed effective data packets is write SRAM memory, it is additionally operable to read from SRAM memory
The effective data packets of storage；
Some control depositors, described control depositor respectively with filtering module, mixing module and SRAM Read-write Catrol module phase
Even, control depositor and include following the tracks of for configuring needs storage storage dispensing unit and the control SRAM control of message handler
The startup of device processed and the switch control unit of time-out；
Some status registers, described status register respectively with filtering module, mixing module and SRAM Read-write Catrol module phase
Even, status register includes for indicating packet the number state control storing to SRAM memory effective data packets number
Unit, described status register also includes the data buffering whether being filled with spilling situation for indicating each data buffer
Device status unit.
SRAM controller the most according to claim 1, it is characterised in that described control depositor also includes information indicating list
Unit, for indicating containing the packet that there is a need to preservation and effective trace information in each processor.
3. a tracking information processing method for the SRAM controller of support polycaryon processor as claimed in claim 1, it is special
Levy and be, said method comprising the steps of:
S1, processor send the packet comprising tracking information；
S2, the filtration of tracking information, filtering module detects follows the tracks of information the need of preserving and following the tracks of letter in each packet
Breath is the most effective, if the information of tracking is invalid without preservation or the information of tracking, then abandons this packet, if tracking information needs to preserve
And the information of tracking is effective, then send this packet, perform step S3；
S3, the mixing of tracking information, the packet that filtering module is exported by mixing module will be many by the parallel sequencing arrived
The packet on road mixes, and is converted into the effective data packets of single channel, and sends this effective data packets,
This step also includes: data buffer read-out control circuit provides control information to data buffer, obtains data buffering
Device stores effective data packets and stores buffered data packet number information, selects the data buffering that buffered data packet number is most
Device is read out；
Indicate the number storing to SRAM memory effective data packets, indicate whether each data buffer is filled with spilling
Situation；
S4, the effective data packets received in mixing module, and mixed effective data packets is write SRAM memory.
Processing method the most according to claim 3, it is characterised in that described step S2 also includes:
Indicate containing the packet that there is a need to preservation and effective trace information in each processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310236387.6A CN103268278B (en) | 2013-06-14 | 2013-06-14 | Support the SRAM controller of polycaryon processor and follow the tracks of information processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310236387.6A CN103268278B (en) | 2013-06-14 | 2013-06-14 | Support the SRAM controller of polycaryon processor and follow the tracks of information processing method |
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| Publication Number | Publication Date |
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