CN103235717B - There is the processor of polymorphic instruction set architecture - Google Patents

Abstract

The present invention proposes a processor with polymorphic instruction set architecture, which includes a scalar processing unit (101), at least one polymorphic instruction processing unit (100), at least one multi-granularity parallel memory (102) and a DMA control device (103); polymorphic instruction processing unit (100) includes at least one functional unit (202); polymorphic instruction processing unit (100) is used for explaining and executing polymorphic instruction, and its functional unit (202) is used for carrying out specific Data manipulation tasks; the scalar processing unit (101) is used to call polymorphic instructions and query the execution status of polymorphic instructions; the DMA controller (103) is used to transmit configuration information of polymorphic instructions and to the multi-granularity The memory (102) transfers data required by the polymorphic instruction. After the processor of the present invention is tape-out, the programmer can still redefine the instruction set of the processor according to the characteristics of the application algorithm.

Description

Processor with Polymorphic Instruction Set Architecture

technical field

The present invention mainly relates to the processor instruction set architecture, which is closely related to the definition of the processor instruction set, the design of the processor architecture and the implementation method of the micro-architecture, especially a polymorphic instruction that can be dynamically reconfigured after tape-out processor set architecture.

Background technique

In recent years, the Internet, cloud computing, and the Internet of Things have developed rapidly. Ubiquitous mobile devices, RFID, and wireless sensors are generating information every second, and hundreds of millions of users of Internet services have generated a huge amount of information interaction; at the same time, users have put forward high requirements for the real-time and effectiveness of information processing , such as an online video-on-demand system, users not only require high-definition images, but also require decoding and display speeds of at least 30 frames per second. We need to study how to efficiently and quickly process massive amounts of information from the analysis of algorithm characteristics.

Generally speaking, massive information processing presents the following features: The first feature is the huge amount of data. The amount of data generated by high-definition video, broadband communications, and high-precision sensors is increasing at a rate of 5 to 10 times per year. The second feature is the huge amount of calculation. The computational complexity of information processing is usually the Kth power of the data volume n (that is, O(n ^K )). For example, the computational complexity of the bubble sorting algorithm is O(n ² ), FFT The complexity of the algorithm is O(nlogn). As the amount of data increases, the amount of calculation required for information processing increases sharply. The third feature is that the algorithms for massive information processing are relatively regular. Core algorithms such as one-dimensional and two-dimensional filtering, FFT transformation, and adaptive filtering can all be expressed in simple mathematical formulas without complicated logical judgments. The fourth characteristic of massive information processing is that it has strong data locality: there is no correlation between local data blocks, but there is strong correlation between local data itself. For example, the calculation results in the filtering algorithm are only related to the data in the filtering template range, and the data in the template range needs to be calculated many times to get the final result; in the video coding algorithm, the data of one or adjacent macroblocks needs to be complicated. The final result is obtained by the operation, and there is no data correlation between the macroblocks that are far away. The fifth characteristic of massive information processing is that the processing algorithm mode basically remains unchanged, but the details of the algorithm continue to evolve. For example, the video coding standard evolves from H.263 to H.264, and the communication protocol evolves from 2G to 3G, and then to LTE.

Massive information processing has its own unique performance requirements and application characteristics. Due to the huge amount of data and calculation in the process of mass information processing, and most of them require real-time calculation, the computing power of traditional scalar and superscalar processors is far lower than this requirement; at the same time, due to the limitations of power consumption and volume, our It is also impossible to realize a massive information processing system only by stacking scalar processors. However, due to the high design and development costs and long cycle of ASIC chips for massive information processing, their update speed is far lower than the evolution speed of massive information processing algorithms, and cannot adapt to the development speed of massive information processing systems. Therefore, it is the current development trend of massive information processing chips to transform traditional scalar and superscalar processors according to the characteristics of massive information processing, or even design brand new domain processors.

An "instruction" is a symbol defined by the designer and understood by the processor. By sending different sequences of instructions to the processor, the programmer specifies what the processor should do at different times. The set of all instructions that a processor can understand is the instruction set for that processor. Programmers use the instructions in the instruction set to implement various algorithms.

Generally, the processor instruction set is determined, and the instruction behavior corresponds to the processor implementation one-to-one. For example, the calculation instruction "ADDR0, R1, R2" included in the ARMv4T instruction set means to add the values in registers R1 and R2, and then Write to R0.

After the processor instruction set is determined, the programmer cannot add instructions to the instruction set, or redefine the behavior of the instructions. Therefore, the instructions in the general processor instruction set are more general to ensure programming flexibility. However, it is difficult for general-purpose processor instruction sets to efficiently implement some special applications. For example, in video coding, it is often necessary to perform 8-bit data calculations. If such algorithms are implemented with 32-bit addition instructions "ADDR0, R1, R2" similar to ARM processors, the efficiency is very low. Therefore, all kinds of processors usually have extended instruction sets for special applications, such as the MMX instruction in the X86 instruction set for video image processing, and the NEON instruction in the ARM instruction set.

Such extended instructions are characterized by high execution efficiency for a certain type of application, but very low execution efficiency for other applications. Therefore, after the design of the processor is completed, the application field it is suitable for has been determined, and it is difficult to adapt to other application fields. Programmers also cannot fine-tune and optimize the processor based on the algorithm characteristics of other application fields.

There are already some patents discussing how to implement reconfigurable computing. For example, US2005/0027970A1 (ReconfigurableInstructionSetComputing) and US2005/0169550A1 (VideoProcessingSystemWithReconfigurableInstructions) adopt the structure of CPU+FPGA, and the user uses a unified high-level language to develop, and the compiler divides the program into the part running on CPU and the part running on FPGA. The feature of this method is that the flexibility of FPGA can be used to accelerate program efficiency, but the too flexible configuration of FPGA leads to low chip performance/cost ratio. U.S. Patent US2004/0019765A1 (PipelinedReconfigurableDynamicInstructionSetProcessor) discusses a processor structure of a RISC processor + a configurable array processor unit, in which multiple array processing units are logically divided into multiple pipeline stages, and the behavior of each pipeline stage Dynamic configuration via RISC processors. US Patent US2006/0211387A1 (MultistandardSDRAarchitectureUsingContext-BasedOperationReconfigurableInstructionSetProcessor) defines a configuration unit + coprocessor processor structure, where each coprocessor is composed of a state control unit and a data path, and is responsible for some similar processing tasks.

Contents of the invention

(1) Technical problems to be solved

The technical problem to be solved by the invention is to propose a processor with polymorphic instruction set architecture to solve the problem that the processor cannot redefine the processor instruction set after tape-out.

(2) Technical solution

In order to solve the above-mentioned technical problems, the present invention proposes a processor with polymorphic instruction set architecture, including a scalar processing unit, at least one polymorphic instruction processing unit, at least one multi-granularity parallel memory and a DMA controller; The polymorphic instruction processing unit includes at least one functional unit; the polymorphic instruction processing unit is used to interpret and execute polymorphic instructions, and its functional unit is used to perform specific data manipulation tasks, wherein the polymorphic instruction refers to multiple sequentially executed The sequence of microcode records, the microcode records represent the actions that each functional unit needs to perform in a certain clock cycle; the scalar processing unit is used to call polymorphic instructions and query the execution status of polymorphic instructions; the DMA controller is used for The configuration information of the polymorphic instruction is transmitted, and the data required by the polymorphic instruction is transmitted to the multi-granularity memory.

According to a specific implementation manner of the present invention, the polymorphic instruction processing unit passively receives the polymorphic instruction from the DMA controller, and is called by the scalar processing unit.

According to a specific implementation manner of the present invention, the scalar processing unit controls the polymorphic instruction processing unit through a first control path, and the scalar processing unit controls the DMA controller through a second control path.

According to a specific embodiment of the present invention, the polymorphic instruction processing unit also includes a microcode memory) and a microcode control unit; the microcode memory is used to store polymorphic instructions; the microcode control unit is used to pass The first control path receives a control request from the scalar processing unit and executes corresponding actions.

According to a specific embodiment of the present invention, the microcode control unit includes a configuration register, which is used to store parameters and running states required by the multi-state instruction processor unit during operation.

According to a specific implementation manner of the present invention, the control request of the scalar processing unit includes starting or querying the polymorphic instruction processing unit, reading and writing configuration registers of the polymorphic instruction processing unit.

According to a specific embodiment of the present invention, the polystate instruction processing unit further includes a transmission control unit, the functional unit has multiple data input/output ports, and exchanges data through the transmission control unit.

According to a specific embodiment of the present invention, the functional unit is used to perform data load/store operations, and read and write data from the multi-granularity parallel memory through a first internal bus; at the same time, the microcode memory acts as a slave A device is connected to the first internal bus and passively receives microcode records from the outside.

According to a specific implementation manner of the present invention, the microcode control unit sequentially reads and executes the microcode records of the polymorphic instructions.

According to a specific embodiment of the present invention, each row in the microcode memory stores a microcode record, and when the scalar processing unit calls a polymorphic instruction, only the initial microcode record corresponding to the polymorphic instruction is specified The line number in this microcode memory.

(3) Beneficial effects

After the processor with the polymorphic instruction set architecture of the present invention is tape-out, the programmer can still redefine the processor instruction set according to the characteristics of the application algorithm. Redefining the instruction set architecture of the post-processor is more in line with the characteristics of the application algorithm, so that the processing performance of the processor in this type of application can be improved. The redefinition process does not modify the processor hardware and the corresponding assembler, linker and other software tool chains, but for different instruction definitions, the instruction set architecture presents different forms.

Description of drawings

Fig. 1 schematically shows the main components and interconnection relationship of the processor with polymorphic instruction set architecture of the present invention;

Fig. 2 briefly shows the main components and interconnection relationship of the polymorphic instruction execution unit of the present invention;

Fig. 3 schematically shows the main components of the microcode record of the present invention;

Fig. 4 briefly shows how to define the behavior of the polymorphic instruction and how the microcode memory preserves the definition of the polymorphic instruction;

FIG. 5 exemplarily shows a process of defining and calling polymorphic instructions in the present invention;

Fig. 6 schematically shows a functional unit in a processor with a polymorphic instruction set architecture of the present invention;

Fig. 7 exemplarily shows the interface definition and internal structure of the calculation unit adopted by the processor of the present invention;

Fig. 8 exemplarily shows the interface definition and internal structure of the bus interface unit adopted by the processor of the present invention;

Fig. 9 exemplarily shows the interface definition of the register file heap adopted by the processor of the present invention;

Fig. 10 exemplarily shows the definition of data transfer paths between functional components in the processor of the present invention;

Fig. 11 exemplarily shows the implementation structure of the internal data transmission unit of the computing unit in the processor of the present invention;

Fig. 12 exemplarily shows the implementation structure of the data transmission unit between functional components in the processor of the present invention

Fig. 13 exemplarily shows the coding of functional components in the processor of the present invention;

Fig. 14 exemplarily shows the logical behavior of the multiplexer in the processor of the present invention in the processor of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The invention proposes a processor capable of dynamically reconfiguring a polymorphic instruction set architecture after tapeout (trial production).

The structure of the processor of the present invention is shown in FIG. 1 , and mainly includes the following components: a scalar processing unit 101 , at least one polymorphic instruction processing unit 100 , at least one multi-granularity parallel memory 102 and a DMA controller 103 . The polymorphic instruction processing unit 100 includes at least one functional unit.

The polymorphic instruction refers to a sequence of multiple consecutively executed microcode records. The polymorphic instruction set is a collection of polymorphic instructions, and the microcode records represent the actions that each functional unit needs to perform in a certain clock cycle, such as performing an addition operation, or performing a data loading operation, or doing nothing.

Wherein, the polymorphic instruction processing unit 100 interprets and executes the polymorphic instruction, and the functional units included in it are used to perform specific data manipulation tasks; the scalar processing unit 101 invokes the polymorphic instruction and queries the execution status of the polymorphic instruction, The DMA controller 103 transmits the configuration information of the polymorphic instruction and transmits the data required by the polymorphic instruction to the multi-granularity memory 102 .

The scalar processing unit 101 controls the polymorphic instruction processing unit 100 through a first control path 104, the scalar processing unit 101 controls the DMA controller 103 through a second control path 105, and the DMA controller 103 controls the DMA controller 103 through a first internal bus 106 transmits configuration information to the polystate processing unit 100, the DMA controller 103 transmits data to the multi-granularity parallel memory 102 through the second internal bus 107, and the DMA controller 103 reads and writes data from the outside through the bus 108, and the polystate instruction processing unit 100 reads and writes data from the multi-granularity parallel memory 102 through the second internal bus 107 .

Described scalar processing unit 101 can be a RISC or DSP, but must have first control path 104, and this control path 104 must possess following function:

1. Start the polymorphic instruction processing unit 100;

2. Query the execution state of the polymorphic instruction processing unit 100;

3. Read and write configuration registers of the polymorphic instruction processing unit 100 (to be described below).

The multi-granularity parallel memory 102 adopts the multi-granularity parallel memory in the Chinese patent publication whose application number is 201110460585.1 (named "multi-granularity parallel storage system and memory"), and the memory can simultaneously support matrix rows and columns of different data types in parallel. read and write.

The master device of the second internal bus 107 is the polymorphic instruction processing unit 100 , and the slave device is the multi-granularity parallel memory 102 . The DMA controller 103 and the multi-state instruction processing unit 100 can read and write data from the multi-granularity parallel memory 102 through the second internal bus 107,

The master device of the first internal bus 106 is a DMA controller 103, and the slave device is a polymorphic instruction processing unit 100, and the DMA controller 103 can write polymorphic instructions to the polymorphic instruction processing unit 100 through the first internal bus 106 . Polymorphic instructions are stored in external memory connected to bus 108 .

polymorphic instruction processing unit

The polymorphic instruction processing unit 100 passively receives polymorphic instructions from the DMA controller 103 and is invoked by the scalar processing unit 101 . FIG. 2 shows an internal structure diagram of the polymorphic instruction processing unit 100 .

The polymorphic instruction processing unit 100 includes a microcode memory 200 , a microcode control unit 201 , at least one function unit 202 and a transmission control unit 203 . The microcode memory 200 is responsible for storing polymorphic instructions, and the microcode control unit 201 receives various control requests from the scalar processing unit 101 through the first control path 104 and executes corresponding actions. Described microcode control unit 201 comprises configuration register 207, and this configuration register 207 is used for storing polymorphic instruction processor unit 100 required parameters and running state when running, as specifying the functional unit 202 that carries out current polymorphic instruction, specifying required The starting address of the data, the total length of the data, and indicating whether the current polymorphic instruction processor unit 100 is idle or not.

These requests include:

1. Start the polymorphic instruction processing unit 100: At this time, the microcode control unit 201 reads the microcode record 300 from the microcode memory 200, generates corresponding control information, and sends it to the function unit 202 and the transmission control unit 203.

2. Query the polymorphic instruction processing unit 100: at this time, the microcode control unit 201 returns the execution status of the current polymorphic instruction: completed or idle.

3. Read and write the configuration register 207 of the polymorphic instruction processing unit 100: at this time, the microcode control unit 201 will write the specified data into the specified configuration register 207, or return the data of the specified configuration register 207.

The polymorphic instruction processing unit 100 can design at least one different functional unit 202 according to application requirements. The functional unit 202 is responsible for performing specific data operation tasks, such as performing addition operations, or data load/store operations. The functional unit 202 generally has a plurality of data input/output ports, and exchanges data through the transmission control unit 203. After the addition operation is completed, the addition unit passes the addition result to the transmission control unit 203, and the transmission control unit 203 sends the addition result to the transmission control unit 203. into the multiplication unit for multiplication.

The transmission control unit 203 is connected to the data input/output ports of all functional units 202, receives the source and destination information of the data at each time from the microcode control unit 201 through the interface 206, and sends the source data to the destination.

The bus 107 is the first internal bus 107 in FIG. 1 . Certain types of functional units 202 need to perform data load/store operations, and need to read and write data from the multi-granularity parallel memory 102 through the first internal bus 107 . At the same time, the microcode memory 200 is connected to the first internal bus 107 as a slave device, passively receiving the microcode record 300 from the outside.

Definition and call of polymorphic instruction

FIG. 3 shows a structure diagram of a microcode record 300 . The microcode record 300 is divided into multiple domains, and each functional unit has a corresponding domain in the microcode record 300, for example, the functional unit domain 301 corresponds to the second functional unit. At the same time, there is a special microcode control field 302 in the microcode record 300, which indicates which line of the microcode record 300 the microcode control unit 201 needs to read at the next clock.

As mentioned above, the polymorphic instruction of the present invention is a sequence of microcode records 300 that are executed consecutively and have specific functions. As shown in Figure 4. The polymorphic instructions, that is, the sequence of microcode records 300 are stored in the microcode memory 200, and are sequentially read and executed by the microcode control unit 201. Each row in the microcode memory 200 stores a microcode record 300 . When the scalar processing unit 101 invokes a polymorphic instruction, it only needs to specify the row number corresponding to the polymorphic instruction that starts to be recorded in the microcode memory 200 .

The programmer can flexibly define the behavior of the polymorphic instruction and the starting line number of the polymorphic instruction in the microcode memory by using the microcode record 300 according to the algorithm requirement. Fig. 5 exemplarily shows a flow of defining and calling polymorphic instructions. First, the programmer defines the behavior of one or more polymorphic instructions according to the application requirements, and converts the behavior of the instruction into a microcode record 300 sequence, which is generally expressed in text, such as "ALU.T0=T1+T2 (U)||Repeat(10)", indicating that the ALU performs 10 addition operations. At the same time, write scalar code, which calls the polymorphic instruction defined by the programmer. At this time, the starting line number of the polymorphic instruction has not been determined, and it is replaced by a label, such as Instr1. After compiling and linking, the polymorphic instruction record represented by text becomes a binary file that the microcode control unit 201 can understand, and at the same time, in the process of compiling and linking, determine the starting address of each polymorphic instruction, such as Instr1 The value of has been determined to be 10. After the scalar code is compiled and linked, it needs to be cross-linked with the polymorphic instruction binary file to replace the symbolic starting address of the polymorphic instruction in the original scalar code with the actual value to generate a scalar binary file. Before calling the polymorphic instruction, the scalar code uses the DMA controller 103 to load the content of the binary file of the polymorphic instruction into the microcode memory, and then calls the polymorphic instruction.

Embodiments of Processors with Polymorphic Instruction Set Architectures

An exemplary embodiment of the polymorphic instruction set architecture is given below, which is only an implementation manner of the present invention, and the content of the present invention is not limited to this example.

This embodiment is a processor with polymorphic instruction set architecture for data-intensive applications. Figure 6 shows the functional units in this processor. As shown in Figure 6, the data bit width of all functional units is 512 bits. When performing data operations, 512 bits can be regarded as 64 pieces of 8bit or 32 pieces of 16bit or 16 pieces of 32bit data. IALU in the functional unit is used for fixed-point logic calculations, FALU is used for floating-point logic calculations, IMAC is used for fixed-point multiply-accumulate calculations, FMAC is used for floating-point multiply-accumulate operations, and SHU0 and SHU1 are used for data interleaving operations, namely Exchange the positions of any two 8bit data within the 512bit data. M is a 512-bit wide register file stack, BIU0 , BIU1 , and BIU2 are bus interface units, responsible for loading/storing data from the multi-granularity parallel memory 102 .

IALU, FALU, IMAC, FMAC, SHU0, SHU1 have similar interfaces, they are collectively referred to as computing unit 500 in this embodiment, the interface of this computing unit 500 is shown in Figure 7, and it comprises four data input ports 604, and corresponding 600 of the four temporary registers. The operation logic 601 reads data from the temporary register to perform calculation, writes the calculation result into the temporary register 602 , and then transmits the calculation result to the transmission control unit 203 through the output port 603 .

BIU0 , BIU1 , and BIU2 are collectively referred to as a bus interface unit 501 , and its internal structure is shown in FIG. 8 . It has a data input port 702, which obtains data from the transmission control unit 203, and writes the obtained data into the temporary register 700; a data output port 703, through which the data in the temporary register 701 is transmitted to the transmission control unit 203 ; an internal bus interface 107 through which data in the multi-granularity parallel memory 102 is read and written; an address calculation logic 704 is responsible for calculating an address sent to the second internal bus 107 .

M is a 512-bit wide register file (Registerfile), which has 4 write ports 800 , 4 read ports 802 , and corresponding memory banks 801 . Figure 9 illustrates the interface to the register file file.

In the polymorphic instruction set architecture, the calculation results of each functional unit can be directly transmitted to other functional units to realize cascaded operations. In this embodiment, it is not necessary to design direct data transmission paths between all functional units. For example, FMAC mainly performs floating-point multiply-accumulate operations, and its operation results do not need to be directly transmitted to fixed-point calculation units IALU or IMAC. The advantage of reducing the data transmission path is that the connection between functional units can be reduced, thereby reducing the chip area and chip cost. The data transmission path between the functional units in this embodiment is shown in Figure 10. The beginning of each column in the table indicates the data destination, the beginning of each row indicates the data source, and the cells with ticks in the middle indicate the existence of transmission paths. In addition, in order to further reduce the transmission path, some functional units can share the transmission path according to the application needs. Sharing the transmission path between the functional units can reduce power chip connections, but these functional units cannot transmit data at the same time. up. If SHU0 to BIU0 and SHU1 to BIU1 share one transmission path, when SHU0 transmits data to BIU0, data cannot be transmitted between SHU1 and BIU1. Shading in Fig. 10 indicates a part of the common transmission path.

The transmission control unit 203 corresponding to FIG. 10 is composed of 29 multiplexers. For the convenience of expression, we decompose the transmission control unit 203 into two levels. The first level is composed of IALU, IMAC, FALU, and FMAC, temporarily called This level is ACU, as shown in Figure 11. This layer transmits data with other functional units through three input ports ACU.I0, ACU.I1, ACU.I2 and one output port ACU.O. The ACU includes a total of 16 multiplexers, namely M13-M28 in Figure 11, and the data input of each multiplexer refers to the marks in the figure.

The second level consists of ACU, M, SHU0, SHU1, and BIU0~BIU2, as shown in Figure 12, including a total of 13 multiplexers, namely M0~M12 in Figure 12, the data input of each multiplexer See markings in figure.

In order to generate the control signals for the 29 multiplexers in the transmission control unit 203, we first group and encode the functional units that can be used, as shown in Figure 13, where "x" means don't care, "0" or "1 "It will be all right. Each functional unit control field 301 in the microcode record 300 needs to specify the destination of the operation result in addition to specifying the operation to be performed by the functional unit. The destination is specified by the code in FIG. The text expression is "IALU.T0=FALU.T1+T2", where "FALU.T1+T2" on the right of "=" indicates that FALU will perform an addition operation, and "IALU" on the left of "=" refers to the destination of the data operation result , the code for this destination is "1100".

The microcode control unit 201 sends the destination information of all functional units in the microcode record 300 to the transmission control unit 203, and the transmission control unit 203 generates control signals of 29 multiplexers according to the destination information. FIG. 14 describes the logical behavior of the multiplexer M0, where GroupID represents the group number of the destination in the control field 301 of the corresponding functional unit.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.

Claims (8)

1. A processor with polymorphic instruction set architecture, characterized in that: comprise a scalar processing unit (101), at least one polymorphic instruction processing unit (100), at least one multi-granularity parallel memory (102) and a DMA controller (103); the polymorphic instruction processing unit (100) includes at least one functional unit (202); The polymorphic instruction processing unit (100) is used to interpret and execute polymorphic instructions, and its functional unit (202) is used to perform specific data manipulation tasks, wherein the polymorphic instruction refers to a plurality of continuously executed microcode records ( 300), the microcode records represent the actions that each functional unit (202) needs to perform in a certain clock cycle; The scalar processing unit (101) is used to call the polymorphic instruction and query the execution state of the polymorphic instruction; The DMA controller (103) is used to transmit the configuration information of the polymorphic instruction and transmit the data required by the polymorphic instruction to the multi-granularity parallel memory (102); The polymorphic instruction processing unit (100) passively receives polymorphic instructions from the DMA controller (103), and is called by the scalar processing unit (101); The scalar processing unit (101) controls the polymorphic instruction processing unit (100) through a first control path (104), and the scalar processing unit (101) controls the DMA controller (103). 2. the processor with polymorphic instruction set architecture as claimed in claim 1, is characterized in that: described polymorphic instruction processing unit (100) also comprises microcode memory (200) and microcode control unit (201) ; The microcode memory (200) is used to store polymorphic instructions; The microcode control unit (201) is configured to receive a control request from the scalar processing unit (101) through the first control path (104) and execute corresponding actions. 3. the processor with polymorphic instruction set architecture as claimed in claim 2, is characterized in that: described microcode control unit (201) comprises configuration register (207), and this configuration register (207) is used for storing multiple The required parameters and the running state of the state instruction processing unit (100) during operation. 4. The processor with polymorphic instruction set architecture as claimed in claim 3, characterized in that: the control request of the scalar processing unit (101) comprises starting or inquiring about the polymorphic instruction processing unit (100), Reading and writing configuration registers (207) of the polymorphic instruction processing unit (100). 5. The processor with polymorphic instruction set architecture as claimed in claim 3, characterized in that: the polymorphic instruction processing unit (100) also includes a transmission control unit (203), and the functional unit (202) It has a plurality of data input/output ports, and exchanges data through the transmission control unit (203). 6. The processor with polymorphic instruction set architecture as claimed in claim 3, characterized in that: said functional unit (202) is used to perform data loading/storage operations, and through a first internal bus (107) Reading and writing data from the multi-granularity parallel memory (102); at the same time, the microcode memory (200) is connected to the first internal bus (107) as a slave device, and passively receives microcode records (300) from the outside. 7. The processor with polymorphic instruction set architecture according to claim 2, characterized in that: the microcode control unit (201) sequentially reads and executes the microcode records (300) of polymorphic instructions. 8. the processor with polymorphic instruction set architecture as claimed in claim 7, is characterized in that: each line deposits a microcode record (300) in the described microcode memory (200), when described scalar processing When the unit (101) calls the polymorphic instruction, it only specifies the line number of the starting microcode corresponding to the called polymorphic instruction recorded in the microcode memory (200).