CN103098019B - Method, apparatus and system for preserving processor state for efficient transition between processor power states - Google Patents

Abstract

The present invention discloses a technique for providing processor states for implementing power state transitions of a processor. In one embodiment, an operating system executing on a processor detects an opportunity to transition the processor to an idle processor power state. In a specific embodiment, the operating system initiates the transition by invoking a task switch, wherein information describing the processor state is saved to a task switch segment.

Description

Method, apparatus and system for preserving processor state for efficient transition between processor power states system

Background technique

1. Technical field

Embodiments generally relate to techniques for power management in computer platforms. More specifically, certain embodiments provide methods for saving or restoring processor state to support computer platforms transitioning between processor power states.

2. Background technology

Improvements in integrated circuit (IC) fabrication and other aspects of computer equipment fabrication have allowed for smaller and/or denser integrated platform architectures. Circuitry in such platforms generally tends to be increasingly sensitive to inefficient use of power, and/or to inefficient use of die space. Thus, incremental improvements in power efficiency, die size, and/or die utilization provide increasing performance gains in these platforms. This is especially true in the case of small form factor platforms such as platforms for handheld devices (eg, smartphones, tablets, etc.).

Existing computer platforms variously include one or more features for managing power allocation to or power usage by processors of those platforms. For example, these features may implement processor idle states differently, eg, in response to a user-initiated platform suspend or hibernate request. In order to support processor idle power states such as the C6 power state, the platform must ensure that the processor's state information is not lost while the processor is in this processor idle power state. In the prior art, processors have variously included dedicated hardware for offloading processor state to differentially powered regions on the chip or for continuous Keep processor state.

Reliance on these techniques for implementing processor idle power states has imposed the requirement that various implementing circuits, such as one or more of registers, power distribution traces, control logic, etc. be included on the processor's IC die. These requirements have heretofore imposed certain constraints on efforts to reduce processor die space and/or improve processor die space utilization.

Brief description of the drawings

Various embodiments of the invention are shown, by way of example and not limitation, in the several figures of the accompanying drawings, in which:

Figure 1 shows a block diagram of selected elements of a system for providing access to processor state information, according to an embodiment.

2 shows a block diagram of selected elements of an executing operating system and hardware of a system for providing access to processor state information, according to an embodiment.

Figure 3 shows a block diagram of selected elements of a task state segment for storing processor state information, according to an embodiment.

4 shows a flow diagram of selected elements of an algorithm for providing access to processor state information, according to an embodiment.

detailed description

Embodiments provide access to processor state in different ways for the purpose of transitioning the processor between processor power states. Various embodiments may be implemented on a computer platform that, for example, utilizes the platform's processor and memory to execute an operating system (OS). The processor of this platform may lack the ability to independently maintain some or all of the processor state for later restoration and/or use (for example, when the processor returns from processor idle to a higher power running processor state) dedicated circuit. However, various embodiments are not limited thereto.

"Processor state information" or simply "processor state" refers to information that describes the data, current (or next ) instructions, the state of the stack, information that determines the status of parameters for exception handling, error handling, etc., or otherwise determines how the processor is and/or will perform processing at a particular point in time. Providing access to the processor state may include, for example, providing the processor state for storage external to the processor, eg, in case the processor transitions to a processor idle state. Alternatively or additionally, providing access to the processor state may include making the processor state available for loading into the processor, eg, in preparation for transitioning from a processor idle state to a higher power run processor state.

In some embodiments, the OS may initiate a transition to (or from) a processor idle power state. By way of illustration and not limitation, in response to detecting an opportunity to cause the processor to transition between processor power states, an OS executing on the processor may trigger the processor to perform a task switch. In some embodiments, the task switch may save some or all of the state of the processor to a task switch repository—eg, a data structure in memory that is available to the OS's general purpose task switches during uptime execution of the OS. While certain embodiments are not limited thereto, the location of the task-switching repository in memory, the arrangement of data in the task-switching repository, and/or references to the task-switching repository by other platform data may be compared to the Santa Clara, CA Compatible with the use of Intel Corporation's x86 architecture.

For example, a task switch repository may include a task state segment (TSS). By way of illustration and not limitation, a task switch may save one or more of segment register state, control register state, EFLAG register state, EIP register state, and segment selector state to the TSS. While features of certain embodiments are described herein in terms of accessing the TSS, it should be understood that these features can be extended for other embodiments to access any of a variety of additional or alternative task switch repositories.

In an embodiment, task switching may include switching the processor to stop executing tasks of applications running on the OS. In these cases, for example, a task switch may be performed without the application receiving any indication that operations need to cease power state transitions.

Alternatively or additionally, for example, an OS initiating a task switch for a processor power state transition may include switching the processor from executing a task in an OS context to executing a power management task in another context. For example, a processor may switch to a task in a context different from the OS context. By way of illustration and not limitation, a task switch may include switching a processor to execute a single thread context or other context for performing power management tasks of any task other than the OS. For example, such power management tasks may include basic input/output system (BIOS) or other firmware tasks.

FIG. 1 illustrates selected elements of a system 100 in accordance with certain exemplary embodiments. System 100 may include platform 105 having a power supply 150 for powering other components of platform 105 in various manners. Although the scope of the various embodiments is not limited thereto, the platform 105 may include a personal computer (PC), a personal digital assistant (PDA), an Internet appliance, a cellular phone, a laptop computer, a tablet device, a mobile unit, a wireless communication device, and/or One or more of any other computing devices.

According to some embodiments, platform 105 may include processing unit 110 coupled directly or indirectly to one or more other components such as memory 125 and system interconnect 135 . Additionally or alternatively, processing unit 110 may have access to basic input/output system (BIOS) instructions, such as those stored in memory 125 or a separate storage device (120). For example, processing unit 110 may be variously coupled to components of platform 105 via one or more address and/or data buses. It should be understood that interconnects other than or in addition to such buses may be used to connect processing units 110 . For example, one or more dedicated lines, crossover lines, etc. may be used to connect processing unit 110 to memory 125.

As described below, processor 110 may include one or more cores 115 (not shown) to execute an operating system (OS). In various embodiments, the executing OS may implement one or more features—for example, Advanced Configuration and Power Interface (ACPI) and/or Operating System Power Management (OSPM) code—to provide power distribution and/or or consumption management.

Additionally, processing unit 110 may include cache memory (not shown), such as, for example, static random access memory (SRAM), or any of various types of internally integrated memory. The memory 125 may include dynamic random access memory (DRAM), non-volatile memory, and the like. In one example, memory 125 may store software programs executable by processing unit 110 .

Interconnect 135 may interconnect various components of platform 105 for various exchanges of data and/or control messages. By way of illustration and not limitation, interconnect 135 may include one or more of an Ethernet interface, a universal serial bus (USB) interface, a peripheral component interconnect interface, and the like. Additionally or alternatively, interconnect 135 may include circuitry for controlling various components interconnected by interconnect 135 . For example, interconnect 135 may include one or more controller hubs such as an I/O controller hub, a platform controller hub, a memory controller hub, and the like.

To illustrate various features of certain embodiments, interconnect 135 is shown coupling processing unit 110 to input device 130 for receiving communications at platform 105, output device 140 for sending communications from platform 140, and for A store 145 in which data is stored in the platform 105 . By way of illustration and not limitation, one or both of input devices 130 and output devices 140 may include one or more of a keyboard, keypad, mouse, touch screen, display, biometric device, and the like. Storage devices 145 may include hard disk drives (HDD), solid-state drives (SSD), compact disk (CD) drives, digital versatile disk drives (DVD), and/or other computer media input/output (I/O) devices one or more of . In an embodiment, one or more of input devices 130 , output devices 140 , and storage devices 145 may be external and coupled to platform 105 —eg, as various devices that are peripheral to platform 105 .

It should be understood that any of various additional or alternative devices, circuit blocks, etc. of platform 105 may be coupled to processing unit 110 according to various embodiments. It should also be understood that the particular architecture of platform 105—eg, the relative configuration of devices, circuit blocks, etc. of platform 105 relative to processing unit 110—is not limited to certain embodiments.

According to some embodiments, system 100 may exchange data with other devices via a connection to network 155—for example, using platform 105's network interface card, wireless network interface, or antenna (not shown). The network connection may include any type of network connection, such as an Ethernet connection, Digital Subscriber Line (DSL), telephone line, coaxial cable, and the like. Network 155 may be any type of network, such as the Internet, a telephone network, a cable network, a wireless network (such as, for example, in accordance with IEEE Std 802.11 (1999), one or more IEEE 802.11 related standards, IEEE 802. 16 standard or something), and so on.

According to one embodiment, processing unit 110—eg, a particular processing core of one or more cores 115—may operate differently in two or more processor power states. As used herein, a power state refers to one or more characteristics of power delivered to or used by a device or combination of devices in that power state—for example, voltage level, current level, clock frequency, etc. Platform 105 may provide hardware and/or execute software to support, initiate, or otherwise effectuate transitions of processor cores between these power states.

FIG. 2 illustrates selected elements of a platform 200 for providing access to processor state information, according to an embodiment. For example, platform 200 may include some or all of the features of platform 105 .

By way of illustration and not limitation, platform 200 may include a processor core 205 for executing an operating system (OS) 250 . To illustrate certain features of one embodiment, processor core 210 is shown as residing in system on chip (SoC) 205 of platform 200 . It should be understood that in alternative embodiments, processor core 210 may reside external to one or any SoC of the platform—for example, in an isolated single-core or multi-core CPU IC chip.

Processor core 210 may be coupled to one or more other components of platform 200 in various ways—eg, including components that reside on SoC 205 or are external to SoC 205 . By way of illustration and not limitation, SoC 205 may include graphics module 215 having circuitry or other logic to perform rendering calculations or other processing of graphics data. Alternatively or additionally, SoC 205 may include a display module 220 having interfaces, drivers, or other circuitry/logic for providing video information to a display. Alternatively or additionally, SoC 205 may include a memory controller 225 including circuitry or other logic for managing access to the data storage components of platform 200 . Alternatively or in addition, SoC 205 may include a power management unit (PMU) 230 to variously detect, determine, or otherwise provide data and/or control messages related to power management of one or more components of platform 200 .

In various embodiments, some or all components of platform 200 coupled to processor core 210 may (in various alternative embodiments) be separate from one or any SoC of platform 200 . Likewise, it should be understood that combinations and/or configurations of these other coupling components of platform 200 are illustrative only, and that platform 200 may include one or more additional or alternative components coupled to processor core 210 according to various embodiments. Any of a variety of combinations of components.

OS 250 may exhibit baseline runtime execution during one or more running (ie, non-idle) processor power states of processor core 210 . During such standard runtime execution, OS 250 may perform various tasks. When processor core 210 is executing instructions of OS 250 , for example, by performing tasks on behalf of OS 250 , processor core 210 is said to be running within the context of OS 250 . Tasks executed in the context of the OS 250 may include, but are not limited to, tasks for performing operations of applications running on the OS 250, tasks for the OS 250 to implement interrupt handling, tasks for the OS 250 to implement exception handling, etc.

During such runtime execution, OS 250 may switch between these tasks in different ways while maintaining the running processor power state. For example, OS 250 may request a task switching call to save information in processor core 210 that describes the execution state of the currently executing task, OS 250 will also describe the next task to be switched to (e.g., start or restart Other information about the execution state of the executed task) is loaded into the processor core 210. By way of illustration and not limitation, OS 250 may signal one or more task switches, causing processor core 210 to switch on a different task state segment (TSS) 240a, . . . way to save and/or load task state for individual tasks.

In one embodiment, OS 250 may include processor manager 255—for example, functionality from a set of executable instructions for evaluating or otherwise detecting one or more processor idles of processor core 210. situation. In one embodiment, processor manager 255 may include the CPUIDLE manager routine of LinuxOS. Alternatively or in addition, processor manager 255 may include one or more processor idle/load detection functions available using OS Power Management (OSPM) agents, such as those described in the Advanced Configuration and Power Interface (ACPI) open standard such as Functionality available in ACPI Amendment 4.0a, released April 5, 2010). Although described herein in terms of processor manager 255, it should be understood that OS 250 may include or otherwise provide any of a variety of additional or alternative detection logic for detecting processor idle conditions in accordance with various embodiments of the present invention. A sort of.

By way of illustration and not limitation, processor manager 255 can be executed to determine, receive information about current processor idle, current rate of change in processor idle, expected future processor idle, expected future rate of change in processor idle, etc. An indication of the level or type, or otherwise detect the level or type of current processor idling, current rate of change in processor idling, expected future processor idling, expected future rate of change in processor idling, etc. It should be understood that detecting the idle state of the processor core 210 may include detecting a corresponding load state of the processor core 210 .

For example, OS 250 may include or otherwise have access to a scheduler (not shown) responsible for scheduling the next operation, thread, etc. of OS 250 . Processor manager 255 may detect that the scheduler of OS 250 has determined that there are no or are not expected to be ready operations or threads scheduled for execution by OS 250 .

Based on detection of current or anticipated future processor idle conditions, processor manager 255 may determine that an idle condition represents an opportunity to transition processor core 210 to a processor idle state—e.g., a C6 (or lower) power state . In response to identification of such an opportunity, processor manager 255 may initiate such a power state transition. In an embodiment, initiating a power state transition may include processor manager 255 executing a call to task switch logic 260 of OS 250 . Furthermore, the task switching logic 260 may provide low-level signals to the hardware of the processor core 210 to perform task switching. In one embodiment, while OS 250 remains in one or more operating power states, task switching saves the state of processor core 210 to a TSS—such as TSS 240a, . . . , 240n of memory 235 available for task switching. One.

For example, processor core 210 may switch to a task for a different context than OS 250 context. By way of illustration and not limitation, a task switch may include switching a processor to execute a single-threaded context or other context for performing power management tasks other than any task of the OS 250 . Such power management tasks may include, for example, tasks of power management firmware 245 - such as basic input/output system (BIOS) tasks.

FIG. 3 illustrates selection elements of a processor state 300 provided to (or from) a TSS 305 , where the provisioning is a task switch to support processor power state transitions, according to an embodiment. For example, TSS 305 may include some or all of the features of TSS 240a.

In one embodiment, TSS 305 may also be used for another provision of processor state (such as store or offload), where the other provision is for a task switch, wherein throughout the task switch, the aforementioned processor remains at Same running processor power state.

For example, the availability of a TSS 305 for one or both types of task switching (i.e., for processor power state transitions or for an unchanged running processor power state) can be determined by the location of the TSS 305 in memory and/or generated by the arrangement of processor state information within the TSS305. Alternatively or in addition, the availability of TSS 305 for both types of task switching may arise from registers, tables, pointers, or other platform data elements (not shown) external to TSS 305 and referencing TSS 305, such as indicating the TSS 305 is a processor state repository that is accessible during uptime execution of the OS to enable generic task switching.

By way of illustration and not limitation, the location, arrangement, and/or reference to TSS 305 in the platform may be compatible with the use of TSS 305 with x86 architecture from Intel Corporation, Santa Clara, CA. More specifically, the TSS 305 may include a CS register 310 for storing the selector for the encoding segment 315, a DS register 320 for storing the selector for the data segment 325, and an SS register 330 for storing the selector for the stack segment 335. one or more of .

Selectors CS register 310, DS register 320, and SS register 330 can be easily loaded into or unloaded from a processor with task switching, e.g., for restoring or saving task execution, respectively, when a task switch is about to be performed current state of .

For example, TSS 305 may include various alternative or additional structures compatible with task switching implemented by x86 architecture processors. By way of illustration and not limitation, the TSS 305 may include one or more additional data segment registers - illustratively ES registers 340, FS registers of respective selectors that may store additional data segments 345, 355, 365 350 and GS register 360. Alternatively or in addition, TSS 305 may store EFLAG register 370 to store individual flags indicating the mode of processor operation (e.g., single-level mode, interrupt handling mode, task chaining mode, etc.) used to execute tasks associated with TSS 305 . sign. Alternatively or in addition, TSS 305 may store EIP register 375 to store a pointer to the current instruction for executing the task. Techniques for storing and/or restoring processor state by accessing the TSS with x86 architecture processors are well documented and are not limited to various embodiments, which extend these and other such techniques to support processing Task switching for power state transitions of the controller.

It should be understood that the structure shown in TSS 305 is merely illustrative, and that TSS 305 may include any number of additional or alternative structures and/or information to store processor state. Additionally, such structures and/or information may indicate the availability of the TSS 305 to the processor for processor access to effectuate task switches associated with power state transitions of the processor (e.g., transitioning to an idle processor power state or from an idle processor power state transition) and task switching when the processor will remain in a single run power state.

FIG. 4 illustrates selected elements of a method 400 for providing processor status, according to an embodiment. For example, method 400 may be performed by hardware of platform 105 executing an OS. In an embodiment, at 410, method 400 may include the OS detecting an opportunity for a processor executing the OS to transition to the first power state. For example, the OS may determine that a processor idle condition indicates that power savings are available by placing the processor into an idle processor power state.

In response to detecting the opportunity, at 420, the OS can initiate a power state transition. In an embodiment, the OS initiated transition may include the OS triggering a task switch by the processor. The triggered task switch may save at least a portion of the processor state of the processor to at least a portion of the platform's task switch repository. In an embodiment, one or more characteristics of the data in the platform—for example, the arrangement of the data in the task-switching repository, the location of the task-switching repository in the platform, external to the task-switching repository and references Data for a task switch repository—may indicate that a task switch repository is accessible to effectuate a task switch associated with a processor's power state transition (e.g., transitioning to or from an idle processor power state) and task switching for when the processor will remain in a single operating power state.

This document describes techniques and architectures for providing access to processor state. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of certain embodiments. It will be apparent, however, to one skilled in the art that certain embodiments may be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the description.

Reference in this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in this specification are not necessarily all referring to the same embodiment.

Some portions of the detailed description herein are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the computing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm here is generally considered to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, as will be apparent from the following discussion, it should be understood that discussions throughout the specification using terms such as "process," "calculate," "operate," "determine," "display," etc. refer to computer systems or similar electronic computing device acts and processes that manipulate and/or transform data represented as physical (e.g., electronic) quantities within computer system registers and memory into computer system memory, registers, or other such information storage , transmit or display other data similarly expressed as physical quantities within a device.

Certain embodiments are also directed to means for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored on a computer readable storage medium such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), disks such as dynamic RAM (DRAM) random access memory (RAM), erasable programmable read-only memory (EPROM), electrical EPROM (EEPROM), magnetic or optical cards, or any type of memory card suitable for storing electronic instructions and each coupled to a computer system bus medium.

The algorithms and displays presented herein are not inherently tied to any particular computer or other device. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description below. Furthermore, certain embodiments are not described with reference to any specific programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the embodiments as described herein.

In addition to what is described herein, various modifications may be made to the disclosed embodiments and implementations of the invention without departing from their scope. Accordingly, the descriptions and examples herein are to be interpreted in an illustrative rather than a restrictive sense. The scope of the invention should be measured only with reference to the appended claims.

Claims (30)

1. the method being used for the power management of processor, including:

By the detection of operating system OS for the processor performing described operating system OS is changed to first The chance of power rating；And

In response to the detection of described chance, described operating system OS starts conversion, including described operating system OS triggers the task switching of described processor, and the switching of described task is by the processor state of described processor At least some of preservation switches at least some of of storage vault to task, and wherein said task switching storage vault is also Can accessed another task for constant operation processor power rating switch.

2. the method for claim 1, it is characterised in that described first power rating includes processor Idle condition.

3. the method for claim 1, it is characterised in that the switching of described task includes described process The power management that device switches to perform in another context from performing operating system O/S context of task is appointed Business.

4. method as claimed in claim 3, it is characterised in that another context described be single-threaded up and down Literary composition.

5. method as claimed in claim 3, it is characterised in that perform described power management tasks and include holding Row firmware.

6. method as claimed in claim 5, it is characterised in that perform described power management tasks and include holding Row basic input/output bios code.

7. the method for claim 1, it is characterised in that the switching of described task includes described process Device is from the task switching performing the application of operation on described operating system OS, wherein not to described application Instruction needs to stop performing the switching of described task in the case of the operation of described conversion.

8. the method for claim 1, it is characterised in that by the processor state of described processor At least some of task switching preserved includes posting segment register state, control buffer status, EFLAG One or more preservations in storage state, EIP register state and segment selector state to described task is cut Change the task switching of storage vault.

9. it is used for a device for the power management of processor, including:

Memorizer, has task switching storage vault, and described task switching storage vault includes one or more task State section；And

Coupleding to the processor of described memorizer, described processor execution operating system OS is used for detection will The chance to the first power rating changed by described processor, and described to start in response to detecting described chance Conversion, triggers the task switching of described processor including described operating system OS, and described task switches institute State at least some of at least preserved to described task switching storage vault of the processor state of processor Point, wherein said task switching storage vault can also be accessed for constant operation processor power rating Another task switches.

10. device as claimed in claim 9, it is characterised in that the process of described operating system OS Device manager is used for the chance of described conversion for detection.

11. devices as claimed in claim 9, it is characterised in that described first power rating includes place Reason device idle condition.

12. devices as claimed in claim 9, it is characterised in that the switching of described task includes described behaviour Make system OS to switch to perform another from performing operating system O/S context of task by described processor Power management tasks in context.

13. devices as claimed in claim 12, it is characterised in that another context described is single line Journey context.

14. devices as claimed in claim 12, it is characterised in that perform described power management tasks Including performing firmware.

15. devices as claimed in claim 9, it is characterised in that the switching of described task includes described behaviour Make system OS by described processor from the task switching performing the application of operation on described operating system OS, Wherein do not needing to stop in the case of the operation of described conversion, perform described appointing to described application instruction Business switching.

16. devices as claimed in claim 9, it is characterised in that by the processor shape of described processor At least some of task switching preserved of state include by segment register state, control buffer status, One or more preservations in EFLAG buffer status, EIP register state and segment selector state are to institute State the task switching of task switching storage vault.

17. 1 kinds of equipment for the power management of processor, including:

For by the detection of operating system OS for the processor conversion by performing described operating system OS extremely The device of the chance of the first power rating；And

For the detection in response to described chance, described operating system OS starts conversion, including described operation System OS triggers the device of the task switching of described processor, and the switching of described task is by the place of described processor At least some of preservation of reason device state switches at least some of of storage vault to task, and wherein said task is cut Change storage vault and can also be accessed another task switching for constant operation processor power rating.

18. equipment as claimed in claim 17, it is characterised in that described first power rating includes Processor idle states.

19. equipment as claimed in claim 17, it is characterised in that the switching of described task includes institute State processor to switch to perform the power in another context from performing operating system O/S context of task Management role.

20. equipment as claimed in claim 19, it is characterised in that another context described is single line Journey context.

21. equipment as claimed in claim 19, it is characterised in that perform described power management tasks Including performing firmware.

22. equipment as claimed in claim 21, it is characterised in that perform described power management tasks Including performing basic input/output bios code.

23. equipment as claimed in claim 17, it is characterised in that the switching of described task includes institute State processor and switch, wherein not to institute from performing the task of the application of operation on described operating system OS State application instruction to need to stop in the case of the operation of described conversion, perform the switching of described task.

24. equipment as claimed in claim 17, it is characterised in that by the processor of described processor At least some of task switching preserved of state include by segment register state, control buffer status, One or more preservations in EFLAG buffer status, EIP register state and segment selector state are to institute State the task switching of task switching storage vault.

25. 1 kinds of computer systems, including:

Memorizer；

Coupleding to the processor of described memorizer, described processor execution operating system OS is used for detection will The chance to the first power rating changed by described processor, and described to start in response to detecting described chance Conversion, triggers the task switching of described processor including described operating system OS, and described task switches institute At least some of preservation of the processor state stating processor switches at least some of of storage vault to task, its Described in task switching storage vault can also be accessed for another of constant operation processor power rating Task switches；And

Coupleding to the antenna of described processor, described antenna is by described computer system and wireless network phase coupling Close.

26. computer systems as claimed in claim 25, it is characterised in that described operating system OS Processor management device for detection for the chance of described conversion.

27. computer systems as claimed in claim 25, it is characterised in that described first power shape State includes processor idle states.

28. computer systems as claimed in claim 25, it is characterised in that the switching of described task will Described processor switches to perform the merit in another context from performing operating system O/S context of task Rate management role.

29. computer systems as claimed in claim 28, it is characterised in that perform described power tube Reason task includes performing firmware.

30. computer systems as claimed in claim 25, it is characterised in that by described processor At least some of task switching preserved of processor state includes segment register state, controls depositor shape One or more preservations in state, EFLAG buffer status, EIP register state and segment selector state Task switching to described task switching storage vault.