CN1030834A - Bus transmitter with controlled trapezoidal slew rate - Google Patents
Bus transmitter with controlled trapezoidal slew rate Download PDFInfo
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- CN1030834A CN1030834A CN88102666A CN88102666A CN1030834A CN 1030834 A CN1030834 A CN 1030834A CN 88102666 A CN88102666 A CN 88102666A CN 88102666 A CN88102666 A CN 88102666A CN 1030834 A CN1030834 A CN 1030834A
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- transistor
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- 230000000630 rising effect Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000011514 reflex Effects 0.000 description 2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
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Abstract
The present invention relates to a kind of transmitter circuit by the transmission of the bus in digital data system digital data signal, sort circuit comprises a MOSFET bus driver transistor, transistorized grid-drain capacitance C
GDCompare dominant with other electric capacity of grid end.The bus driver transistor is led the buffer circuits that flows through with the pull-down transistor electric current and is encouraged on having, this electric current is controlled by two assorted stream sources.The gate terminal of driver transistor be connected to lead and pull-down transistor between node on and be subjected to the control of this node.The drain electrode end connection of driver transistor and a lead of control bus.
Description
Relate generally to electronic circuit field of the present invention relates more specifically in digital data system to send by bus the circuit of signal.
A digital data system comprises many functional units, comprise: one or more processors, internal memory and such as the such input-output apparatus of mass storage, video display terminal, printer and communication facilities, by one or multiple bus with above-mentioned these device interconnectings.The signal and the various control signal of these buses transmission representative information between each unit that constitutes this system, these control signals are used in particular for the transmission of each information signal.
Usually, bus is one group of lead that some functional units can be connected in parallel thereon.When a unit sent signal by a lead in the bus, the end that this signal arrives this bus just may be reflected.Reflected signal may disturb the signal that sends by this bus subsequently, and this situation can cause the signaling error on the bus.The subject matter of signal reflex is that reflected signal makes the signal degradation that sends subsequently.Therefore, in order the interference from the signal reflection to be reduced to minimum, system designer is had to before carrying out another time transmission, provides enough time delay after then last the transmission.
On the other hand, perhaps system designer can make reflection reduce to minimum by design bus or by the signal that bus sends, and for example, each end of some lead has the resistor network that helps to reduce reflection.The power supply of bus also can provide by these bus termination absorbing load networks.
In addition, can the conditioning signal waveform, make reflection and reduce to minimum in the cross-talk between the signal on the different bus.Particularly, signal waveform can be reasonable rectangle, makes that the voltage amplitude steeper ground between height and low level on the bus conductor changes.A kind of like this signal waveform allows to send apace signal, but yet may cause signal reflex and cross-talk.
On the other hand, if signal is " trapezoidal ", promptly the signal voltage amplitude of this waveform with more not precipitous but still be very fast rate variation, just can reduce to contingent reflection minimum between height and low level.The transmitter that produces such signal should be able to be " rate of change " (Slew rate) at the voltage changing rate on the selected limit inner control lead.This problem is complicated, because in most systems, bus should be able to handle be attached thereto, the very wide unit of number of variations scope, like this, then the situation that causes capacity load in wide range, to change, thereby may change the rate of change of the signal that sends by bus conductor.
At present, the transmitter that can produce trapezoidal signal waveform can be made by discrete resistors and other element that high-precision is controlled in conjunction with the electric parameter value with bipolar transistor.Most of circuit that constitutes the functional unit of digital data system is made with MOSFET device (MOSFET), bipolar transmitter circuit then is separate with other element that constitutes these unit and make separately, occupies sizable space on the printed circuit board (PCB) of the circuit component that these unit of formation are housed.In addition, because these bipolar transmitters are discretes, ambipolar and separate with other device,, cause to send the extra delay of signal so they need very big electric power.
The invention provides a kind of improved transmitter circuit that make with the MOSFET device, new, in order to produce by bus signal that send, that have trapezoidal waveform.
Put it briefly, this new bus transmitter circuit comprises a MOSFET bus driver transistor, and the buffer circuits that this transistor leads on having by, the pull-down transistor electric current passes through is encouraged, and this electric current is controlled by constant current source.Capacitor C between the grid-leakage of driver transistor
GDBasically greater than other electric capacity at gate terminal place.The driver transistor gate end is connected to the node that leads between the drop-down two transistor, and is controlled by this node.The drain electrode end of driver transistor is connected to bus line, and it is controlled.In order on bus line, to establish a signal, on lead transistor and be switched on, according to a speed electric current is sent into node by current source control, this makes the magnitude of voltage of node increase.When the node voltage value reached the threshold value of driver transistor, driver transistor began conducting, and the magnitude of voltage of bus line is descended.Simultaneously, electric current is by the grid-drain capacitance of driver transistor, begins to flow into node from bus line, thereby limited the node voltage value, and limited the electric current of the driver transistor of flowing through thus.Thereby, electric current in the mode that is subjected to the control of magnitude of voltage rate of change on the bus line to a certain extent from the bus line driver transistor of flowing through, thereby realize the trapezoidal variation of signal on bus line.On bus line signal is become in the process of anti-(negale), working condition is similar, and electric current flows out node by electric capacity between the grid-leakage of pull-down transistor and driver transistor.
With reference to description, can understand the above-mentioned and further advantage of the present invention preferably below in conjunction with accompanying drawing.In these accompanying drawings:
Fig. 1 is by the deliver letters circuit sketch plan of device of the digital data bus that the present invention constitutes;
Fig. 2 is 2 signal waveforms of locating in circuit shown in Fig. 1, and it helps to understand the transmitter shown in Fig. 1.
With reference to Fig. 1, the transmitter 10 that constitutes according to the present invention comprises a bus driver transistor 11, and the gate terminal of transistor 11 receives the impact damper output digital data signal BUT OUT from the buffer circuits 12 that is connected into the phase inverter form.In response to (being high level) impact damper output signal BUF OUT from the establishment of buffer circuits 12, the bus driver transistor turns sends out a BUS OUT(L by bus line 14) bus output (low level of establishment) digital data signal.Bus driver transistor 11 has the drain electrode end of always receiving bus line 14 in succession and one to be connected in fact to be in earthy power supply V
SSSource terminal.Bus driver transistor 11 is n-type metal oxide semiconductor field effect transistors (MOSFET).
Buffer circuits 12 comprises and leads transistor 16 and a n-type pull-down transistor 17 on the p-type that is connected between constant current source 20 and 21.Constant current source 20 is connected to power supply V
DD, and the electric current that leads transistor 16 drain electrode ends is coupled in control.On lead the source terminal link node 22 of transistor 16, node 22 is connected to the drain electrode end of pull-down transistor 17.The source terminal of pull-down transistor 17 is connected to current source 21, and current source 21 controls flow to power supply V by it from node 22
SSElectric current.The BUF OUT phase inverter output signal that is coupled to bus driver transistor 11 gate terminal by on node 22 places of leading between the drain electrode end of the source terminal of transistor 16 and pull-down transistor 17 provide.See transistor 11 back, with at node 22 places other electric capacity compare, transistor 11 it gate terminal and drain electrode end between exist a big electric capacity (in Figure 11 with C
GDRepresent), so grid-drain capacitance C
GDAmong each electric capacity at node 22 places, play significant feature in fact.
On lead transistor 16 and pull-down transistor 17 gate terminal by (being asserted high level) output signal SIG OUT(H from phase inverter 13) with cascade system control, phase inverter 13 will be from signal output (being asserted low level) signal SIG OUT(L of other circuit (not shown)) carry out paraphase.This signal output (being asserted low level) signal SIG OUT(L) also control a p-transistor npn npn 15, the drain electrode end of transistor 15 is connected to node 22, and its source terminal is connected to power supply V
SS
Originally, signal output (being asserted high level) signal SIG OUT(H) in (opposite) low-voltage state.As a result, transistor 15 conductings.Phase inverter 13 is with this signal output (being asserted high level) signal SIG OUT(H) paraphase, so that signal output (being asserted low level) signal SIG OUT(L of (opposite) high-voltage value to be provided), it transfers again transistor 17 to be maintained at conducting state, and transistor 16 is maintained at cut-off state.At this moment, transfer to power supply V by current source 21 from the electric charge of node 22
SS(promptly) is so impact damper output signal BUF OUT is in low voltage value.In addition, because driver transistor 11 ends, so bus output (being asserted low level) signal BUS OUT(L) be to be in high-voltage value (thereby a signal with opposite logic levels is provided), as (Fig. 2) shown in the time A.
As signal output (being asserted high level) signal SIG OUT(H) during from (high voltage) state that opposite (low-voltage) state exchange becomes to determine, transistor 15 ends.In addition, phase inverter 13 is with signal output (being asserted high level) signal SIG OUT(H) paraphase, export (being asserted low level) signal SIG OUT(L to form a signal that is in low-voltage (establishments) state).As a result, transistor 17 ends, and cuts off from node 22 and passes through current source 21 to power supply V
SSCurrent path.In addition, signal output (being asserted low level) signal SIG OUT(L) make transistor 16 conductings, thus set up one from power supply V
DDBy the path of current source 20 to node 22.
Because transistor 16 conductings, thus impact damper output signal BUF OUT(as among Fig. 2 since time A to shown in the time B) rise.At time B(Fig. 2), the magnitude of voltage of impact damper output signal BUF OUT has risen to threshold voltage, so the 11 beginning conductings of bus driver transistor.This then make electric current flow through bus driver transistor 11 again from the line 14 of bus, cause bus output (being asserted low level) signal BUS OUT(L) magnitude of voltage descend, as among Fig. 2 and then behind the time B shown in.Yet, because the grid of bus driver transistor 11 a drain capacitance C
GDOccupy the sizable ratio of total capacitance on the node 22, so electric current also passes through grid one drain capacitance C from the line 14 of bus
GDInject node 22.Therefore, grid one drain capacitance C
GDProvide a feedback network, so that bus output (being asserted low level) signal BUS OUT(L) influence the magnitude of voltage of node 22.
Because this moment two sources, promptly current source 20(by on lead transistor 16) and the line 14(of bus pass through the grid one drain capacitance C of bus driver transistor 11
GD), force electric current to enter node 22 the other way around, so node 22 (is power supply V with respect to ground
SSMagnitude of voltage) magnitude of voltage, promptly the magnitude of voltage of node 22 is constant, as among Fig. 2 between time B and the C shown in.Therefore, the magnitude of voltage on bus driver transistor 11 gate terminal approximately maintains on the threshold value, thereby transistor 11 is kept conducting, and its conducting degree is such: promptly the magnitude of voltage of the line 14 of bus is at this moment to fall under the speed that is controlled.That is exactly (being asserted low level) bus-out signal BUS OUT(L) in a time interval, change to low value, the grid one drain capacitance C of it and bus driver transistor 11 from the high value
GDWith provide by current source 20 current related.
Bus output (being asserted low level) signal BUS OUT(L on the line 14 in bus) when finishing downward transition change, electric current passes through grid one drain capacitance C from the line 14 of bus
GDThe speed of injecting node 22 also descends.As a result, from current source 20, by on lead the electric current that transistor 16 injects nodes 22 and play a major role at node 22 places, and the magnitude of voltage of node 22 begins to increase once more, shown in time C to D among Fig. 2.This rate of growth depends on and comprises grid one drain capacitance C
GDAt the electric capacity of interior node 22 and by the electric current of current source 20 for supply.At time D (Fig. 2), node 22 is charged to maximum voltage value.At this moment, bus driver transistor 11 complete conductings, and node 22 is charged fully, as among Fig. 2 shown in the high impact damper output signal BUF OUT in time D place.In addition, during to time D, bus output (being asserted low level) signal BUS OUT(L) be determined fully, promptly it is at minimum voltage value.
Impact damper output signal BUF OUT remains on high-voltage value, and bus output (being asserted low level) signal BUS OUT(L) remain on low voltage value, till time E.At time E, signal output (being asserted high level) signal SIG OUT(H) be opposite, promptly it is energized to a low voltage value.As a result, phase inverter 13 is with the signal of this low value output (being asserted high level) signal SIG OUT(H) paraphase, so that signal output (being asserted low level) signal SIG OUT(L of a high value to be provided).Signal output (being asserted low level) signal SIG OUT(L of this high value) again then lead transistor 16 on going to end, thereby, cut-out is 22 path from current source 20 to node, and conducting pull-down transistor 17, thus provide one from node 22 to current source 21 current path.
In addition, the signal of high value is exported (being asserted high level) signal SIG OUT(H) make transistor 15 conductings, this directly is provided with one at node 22 with by source electrode power supply V
SSCurrent path between the ground that is provided.This current path by transistor 15 allows node 22 between time E and F (Fig. 2) to be discharged to the threshold voltage of transistor 15 apace.At transistor 15 is in the certain embodiments of n one transistor npn npn, and the magnitude of voltage that transistor 15 allows nodes 22 falls from 5 volts of states of complete charged state reduces to about 2.5 volts.During this period, also also have electric current to flow out node 22, but main current path is a transistor 15 by pull-down transistor 17 and current source 21.Flowed out enough big electric current at node 22, after making the magnitude of voltage of node 22 reach the threshold value of bus driver transistor 11, bus driver transistor 11 begins to end, make bus output (being asserted low level) signal BUS OUT(L) magnitude of voltage rise, thereby make bus output (being asserted low level) signal BUS OUT(L) become anti-.
In the front and back of time F, when the drain electrode end of transistor 15 dropped into the threshold value of transistor 15 to the potential difference (PD) between the gate terminal, transistor 15 ended basically.Yet electric current still tends to continue flow out node 22 by pull-down transistor 17 and current source 21.Simultaneously, electric current continues in the other direction (promptly to pass through the grid one drain capacitance C of driver transistor 11
GD) outflow node 22.Because electric current is to flow out from node 22 in the other direction, so it is constant that the magnitude of voltage of the node 22 of impact damper output signal BUF OUT is provided, shown in the G, the size of the magnitude of voltage that this is constant enough makes transistor 11 keep conducting under controlled level as time F among Fig. 2.This permission bus output (being asserted low level) signal BUS OUT(L) magnitude of voltage increased with a kind of speed of stable control in this time interval, as shown in Figure 2.
At time G, grid one drain capacitance C
GDStop to draw electric charge from node 22, thus electric charge just the transistor 17 by still conducting, flow out from node 22 with the speed of being controlled by current source 21.Therefore the magnitude of voltage of node 22 drops into the V of source electrode supply
SSValue, the i.e. earth potential of transmitter circuit 10.Therefore, impact damper output (being asserted low level) signal BUF OUT(L) (Fig. 2) falls with an in check speed between time G-H, as shown in Figure 2.
Will recognize that the effect that transistor 15 is set is in order to shorten E to the F time period, be during this period of time for the magnitude of voltage that makes node 22 drop to driver transistor 11 begin by the time magnitude of voltage required.Under the situation that does not have transistor 15, electric current changes from pull-down transistor 17 and current source 21 and flows through, but because current source 21 has limited the circulation of electric current, so need the long time to make the voltage of node 22 finally reach the value that driver transistor 11 begins to end.
In addition, will recognize big grid one drain capacitance C
GDA feedback network is provided in fact, has made bus output (being asserted low level) signal BUS OUT(L) control the magnitude of voltage of node 22 to a certain extent, this is again then controlled the rising and the decline of signal.This just causes bus output (being asserted low level) signal BUS OUT(L) have suitable rising, the forward position of fall time (B to C is between the moment in Fig. 2) and back along (F-G is between the moment in Fig. 2), thus " trapezoidal " signal is provided.The sort signal shape, make in having very short rising, the signal of fall time (being rectangular signal) intrinsic ringing and other noises reduce greatly.The sort signal shape is by means of big grid one drain capacitance C
GDRealize capacitor C
GDConcerning the total capacitance at driver transistor gate end place, occupy main status in fact, make electric current at bus output (being asserted low level) signal BUS OUT(L) transition change during, as described above like that, easily by grid one drain capacitance C
GD
The description of front is limited to a certain embodiments of the present invention.But clearly, might do various changes and modification and have the part or all of advantage that the present invention reaches the present invention.So, claim of the present invention need cover all with the real spirit and scope of the present invention in relevant various changes and modification.
Claims (6)
1, a kind of bus transmitter circuit, it comprises:
A. drive assembly, it comprises an output terminal and a control end, has sizable electric capacity between described output terminal and described control end, thereby provides a feedback network between described output terminal and described control end; And
B. controller buffer device, it has stipulated a control node, described control node removes to control the described control end of described drive assembly in response to the state of input signal, described controller buffer device comprises current-source arrangement, described current-source arrangement Control current flows into and flows out described control node, go conducting and end described drive assembly according to a kind of controlled way, described feedback network is the described drive assembly conducting of control and the speed of ending further, thereby be controlled at the magnitude of voltage of described output end signal.
2, a kind of bus transmitter circuit described in claim 1, wherein, described drive assembly comprises the mosfet driver transistor unit, comprise a drain electrode end that is connected to bus line at output terminal described in the described mosfet driver transistor unit, and described control end comprises a gate terminal, described mosfet driver transistor unit further comprises the source terminal device that is connected to the source electrode power supply, described mosfet driver transistor unit has the electric capacity between described gate terminal and described drain electrode end, and described electric capacity is compared with other electric capacity of described gate terminal place and occupied ascendancy in fact.
3, a kind of described bus transmitter circuit as claimed in claim 1, wherein, described controller buffer device comprise by on lead the mosfet transistor device and on lead that current-source arrangement forms on the pull device that leads device and form by drop-down mosfet transistor device and pull-down current source apparatus, lead the mosfet transistor device on described and described drop-down mosfet transistor device links together at described control node place, and do the control of connection level by described input signal, be subjected to the control of described current source separately by leading mosfet transistor device and described drop-down mosfet transistor device on described to the electric current of described control node.
4, a kind of bus transmitter circuit described in claim 1, it further comprises the pull-down transistor device of the described control end that is connected to described drive assembly, when described input signal switching levels, described pull-down transistor device is subjected to the control of the complementary signal of described input signal, described control node is set on the level of selecting, ends apace to impel described drive assembly.
5, a kind of bus transmitter circuit, it comprises:
A. bus driver apparatus, it comprises a mosfet transistor device with gate terminal, described gate terminal is controlled at flowing of electric current between source terminal and the drain electrode end, described drain electrode end is connected on the single line of bus, described mosfet transistor device has big grid one drain capacitance, so that a feedback network between described source electrode and described gate terminal to be provided;
B. buffer device, it comprises:
ⅰ. on lead device, it has:
A. lead transistor on the MOSFET that has conducting state and a cut-off state; With
B. lead current source on one, when it leads transistor and is in conducting state on described MOSFET, go control to flow through and lead transistorized electric current on described;
ⅱ. pull device, it has:
A. MOSFET pull-down transistor with conducting state and cut-off state; With
B. the electric current that flows through described pull-down transistor when it is in conducting state at described MOSFET pull-down transistor, is removed to draw in a pull-down current source; Lead transistor and described MOSFET pull-down transistor on the described MOSFET and be subjected to the control of the connection level of an input signal, under situation in response to the alternating state of described input signal, a transistor that leads on the described MOSFET in transistor or the described MOSFET pull-down transistor is switched on, lead device and described pull device on described and be joined together to form a control node, the gate terminal of described bus driver apparatus is connected to described this control node.
6, a kind of bus transmitter circuit described in claim 5, it further comprises the pull-down transistor device of the described gate terminal that is connected to described bus driver device, when described input signal switching levels, described pull-down transistor device is subjected to the control of the complementary signal of described input signal, described control node is set on the level of selecting, ends apace to impel described bus driver apparatus.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US6794587A | 1987-06-29 | 1987-06-29 | |
| US067,945 | 1987-06-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1030834A true CN1030834A (en) | 1989-02-01 |
| CN1012409B CN1012409B (en) | 1991-04-17 |
Family
ID=22079462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN88102666A Expired CN1012409B (en) | 1987-06-29 | 1988-05-06 | Bus transmitter having controlled trapezoidal slew rate |
Country Status (4)
| Country | Link |
|---|---|
| KR (1) | KR920007097B1 (en) |
| CN (1) | CN1012409B (en) |
| AT (1) | ATE100256T1 (en) |
| BR (1) | BR8802752A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184128A (en) * | 2011-05-26 | 2011-09-14 | 成都易我科技开发有限责任公司 | Fast disc incremental backup method |
| CN102253868A (en) * | 2010-05-21 | 2011-11-23 | 联发科技股份有限公司 | Method for data recovery and device for data recovery |
| CN102290982A (en) * | 2010-05-31 | 2011-12-21 | 罗姆股份有限公司 | Transmitter, interface device, and car mounted communication system |
| CN101686043B (en) * | 2008-09-28 | 2012-12-05 | 四川虹欧显示器件有限公司 | Circuit structure for protecting driving tube |
| CN102104372B (en) * | 2009-12-21 | 2013-06-12 | 台达电子工业股份有限公司 | Cycle switch control circuit and its control method |
| CN103259519A (en) * | 2013-05-27 | 2013-08-21 | 苏州贝克微电子有限公司 | Active upward-pulling circuit of drain electrode open circuit signal |
| CN102246148B (en) * | 2008-12-11 | 2014-02-12 | 微软公司 | Participating with and accessing connectivity exchange |
| CN111913518A (en) * | 2019-05-08 | 2020-11-10 | 世界先进积体电路股份有限公司 | Voltage regulation circuit |
-
1988
- 1988-04-08 AT AT88400859T patent/ATE100256T1/en not_active IP Right Cessation
- 1988-05-06 CN CN88102666A patent/CN1012409B/en not_active Expired
- 1988-06-02 BR BR8802752A patent/BR8802752A/en not_active Application Discontinuation
- 1988-06-28 KR KR1019880007838A patent/KR920007097B1/en not_active Expired
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101686043B (en) * | 2008-09-28 | 2012-12-05 | 四川虹欧显示器件有限公司 | Circuit structure for protecting driving tube |
| CN102246148B (en) * | 2008-12-11 | 2014-02-12 | 微软公司 | Participating with and accessing connectivity exchange |
| CN102104372B (en) * | 2009-12-21 | 2013-06-12 | 台达电子工业股份有限公司 | Cycle switch control circuit and its control method |
| CN102253868A (en) * | 2010-05-21 | 2011-11-23 | 联发科技股份有限公司 | Method for data recovery and device for data recovery |
| CN102253868B (en) * | 2010-05-21 | 2013-07-10 | 联发科技股份有限公司 | Method for data recovery and device for data recovery |
| CN102290982A (en) * | 2010-05-31 | 2011-12-21 | 罗姆股份有限公司 | Transmitter, interface device, and car mounted communication system |
| CN102290982B (en) * | 2010-05-31 | 2015-07-08 | 罗姆股份有限公司 | Transmitter, interface device, and car mounted communication system |
| CN102184128A (en) * | 2011-05-26 | 2011-09-14 | 成都易我科技开发有限责任公司 | Fast disc incremental backup method |
| CN102184128B (en) * | 2011-05-26 | 2013-04-10 | 成都易我科技开发有限责任公司 | Fast disc incremental backup method |
| CN103259519A (en) * | 2013-05-27 | 2013-08-21 | 苏州贝克微电子有限公司 | Active upward-pulling circuit of drain electrode open circuit signal |
| CN111913518A (en) * | 2019-05-08 | 2020-11-10 | 世界先进积体电路股份有限公司 | Voltage regulation circuit |
| CN111913518B (en) * | 2019-05-08 | 2022-03-25 | 世界先进积体电路股份有限公司 | Voltage adjustment circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1012409B (en) | 1991-04-17 |
| ATE100256T1 (en) | 1994-01-15 |
| KR890001325A (en) | 1989-03-20 |
| KR920007097B1 (en) | 1992-08-24 |
| BR8802752A (en) | 1988-12-27 |
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