CN103064503B

CN103064503B - SOC (system on a chip) and buffer thereof

Info

Publication number: CN103064503B
Application number: CN201210567839.4A
Authority: CN
Inventors: 景蔚亮
Original assignee: Shanghai Xinchu Integrated Circuit Co Ltd
Current assignee: Shanghai Xinchu Integrated Circuit Co Ltd
Priority date: 2012-12-24
Filing date: 2012-12-24
Publication date: 2016-03-09
Anticipated expiration: 2032-12-24
Also published as: CN103064503A

Abstract

The invention relates to SOC (system on a chip) and buffer thereof.SOC (system on a chip) comprises microcontroller; And store the buffer of instruction and the data read for described microcontroller.Described buffer comprises Nonvolatile static random access storage device.Before described buffer enters power-down mode, described Nonvolatile static random access storage device can preserve the live content of described SOC (system on a chip).Compared to prior art, the present invention has the advantage of low-power consumption and quick Self-disconnecting pattern recovery normal mode of operation.

Description

System on chip and register thereof

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a system on chip and a register thereof in the field of integrated circuits.

Background

In a System-on-Chip (soc) architecture, when a microcontroller reads instructions and data stored in an off-Chip hard disk, the soc generally sequentially reads the instructions or data stored in the off-Chip hard disk into an off-Chip memory, then introduces the instructions or data in the off-Chip memory into a buffer of the soc, and finally the microcontroller reads the instructions and data from the buffer to execute operations. The on-chip registers are generally implemented by Static Random Access Memories (SRAMs). When the microcontroller unit reads instructions and data in the buffer, if an interrupt or exception occurs in the system, the system stores all the field contents including an interrupt stack, a user stack, a global variable, a local variable, and the like in the buffer. After the interrupt or exception handling is completed, the microcontroller will restore all the field content stored in the buffer and continue to execute the interrupted instruction or data. During the period of executing an interrupt or handling an exception, the buffer needs to be kept powered on all the time to ensure that the data stored in the buffer is not lost. This tends to result in static leakage power, and as process sizes are made smaller, the buffer occupies a larger proportion and larger area in the entire system-on-chip. This problem is particularly acute, for example, in deep sub-micron process nodes (DSMs), where static leakage power consumption may even be greater than dynamic power consumption.

In addition, when the instruction or data is imported into the buffer and executed by the microcontroller, if the buffer of the system on chip is powered off; because the buffer of the conventional system on chip adopts the SRAM, the instruction and data of the buffer of the system on chip need to be imported again after the system on chip is powered on again based on the characteristic that the SRAM loses the stored content when the SRAM is powered off. This means that instructions and data are read from the off-chip hard disk into the off-chip memory and then are loaded into the registers of the system-on-chip, and the microcontroller needs to execute the program from the beginning. Not only much power consumption is wasted, but also the speed of the microcontroller changing from the low power consumption mode (buffer power down) to the normal working mode is greatly reduced.

In summary, with the trend of miniaturization and low power consumption of electronic products, the registers used in the conventional system on chip will not meet the market demand, and improvement is needed.

Disclosure of Invention

The invention overcomes the defects of overlarge static leakage power consumption, low speed of normal work recovery and the like in the prior art, and provides an on-chip system and a buffer thereof.

The invention proposes a system on chip comprising:

a microcontroller; and

the buffer is used for storing the instructions and data read by the microcontroller; wherein the buffer comprises a non-volatile static random access memory; the non-volatile static random access memory may store the on-site contents of the system-on-chip before the cache enters a power-down mode.

When the buffer is powered on again, the system on chip recovers the field content from the nonvolatile static random access memory, and introduces instructions and data from the outside of the chip into the buffer according to a program pointer in the field content to continue executing the program.

The capacity size ratio of the nonvolatile static random access memory in the whole buffer is increased, and the nonvolatile static random access memory can also store part or all of instructions and/or data to be processed by the microcontroller before the buffer enters a power-down mode.

And when the buffer is powered on again, the on-chip system recovers the field content from the nonvolatile static random access memory and continues to execute part or all of the instructions and/or data which are stored in the nonvolatile static random access memory and are to be processed by the microcontroller before power failure.

Wherein, furthermore, the buffer is completely composed of a nonvolatile static random access memory.

And after the buffer is powered on again, the system on chip continues to execute the interrupted instruction and data stored in the buffer before power failure.

The invention also provides a buffer which is applied to the system on chip and used for storing the instruction and the data read by the microcontroller of the system on chip; wherein the buffer comprises: a non-volatile static random access memory; the non-volatile static random access memory may store the on-site contents of the system-on-chip before the cache enters a power-down mode.

The capacity size proportion of the nonvolatile static random access memory in the whole buffer is increased, and the nonvolatile static random access memory can store part or all of instructions and/or data to be processed by the microcontroller in the buffer before the buffer enters a power-down mode.

The system on chip and the buffer thereof according to the embodiment of the invention not only overcome the problem of large static leakage power consumption, but also can quickly recover the field and continuously execute instructions or data after the ultra-low power consumption mode (buffer power failure) is finished.

Drawings

FIG. 1 is a flow diagram of a system-on-a-chip importing a program (instructions and/or data) from off-chip;

FIG. 2 is a diagram illustrating the structure of registers and the process of executing the program according to an embodiment of the present invention;

FIG. 3 is a flowchart of a program execution of a system-on-chip that employs the registers shown in FIG. 2;

FIG. 4 is a diagram illustrating the structure of registers and the process of executing the program according to another embodiment of the present invention;

FIG. 5 is a diagram illustrating the architecture and program introduction of a von Neumann based register according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating the structure and program import of a cache based on the Harvard architecture according to an embodiment of the present invention;

FIG. 7 is a flowchart of a program execution for a system-on-chip that employs the registers shown in FIGS. 5 and 6;

FIG. 8 is a flowchart illustrating a procedure for implementing registers of a system on chip according to a third embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the following specific examples and the accompanying drawings. The procedures, conditions, experimental methods and the like for carrying out the present invention are general knowledge and common general knowledge in the art except for the contents specifically mentioned below, and the present invention is not particularly limited.

FIG. 1 is a flow diagram of a system-on-a-chip 100 importing programs (instructions and/or data) from off-chip. As shown in FIG. 1, the system on chip 100 includes a microcontroller 2 and a register 3 for storing instructions and data to be read by the microcontroller 2. The soc 100 needs to sequentially read the instructions or data stored in the off-chip hard disk 5 into the off-chip memory 4, and then import the instructions or data from the off-chip memory 4 into the buffer 3, and the microcontroller 2 reads the instructions and data from the buffer 3 to execute the program operation.

For the cache 3 of the system on chip adopting the SRAM structure, it needs to keep the power-on state all the time when the system on chip 100 processes an interrupt or an exception to ensure that the data or the instruction therein is not lost. That is, when the system-on-chip 100 is in interrupt or exception handling, the buffer 3 cannot be powered down, which inevitably causes a large static leakage power consumption. Furthermore, once the cache 3 of the system-on-chip is powered down; after the power is turned on again, the program (instructions and data) needs to be read from the off-chip hard disk 5 to the off-chip memory 4 again, and then the program is imported to the buffer 3 of the system on chip until the microcontroller 2 is all restored, so that the program can be executed again from the beginning. On one hand, unnecessary large power consumption is caused, and on the other hand, the speed of the microcontroller for recovering the normal working mode is also greatly influenced.

The system-on-chip 100 and the register 3 thereof according to the embodiment of the present invention can solve the above technical problem well, and the register 3 uses a Non-volatile static random access memory (NVSRAM) to partially or completely replace the SRAM. Wherein the NVSRAM is composed of a basic SRAM memory cell and two nonvolatile memory cells based on phase change material or Magnetic Random Access Memory (MRAM) material, and data is always kept unchanged even after power is turned off. Because the NVSRAM has the characteristic that data is not lost after power failure, the system on chip can put all global variables, local variables, interrupt stacks and user stacks in the NVSRAM. During the process of processing interrupt, exception or normal execution of instructions and data, before the system on chip enters an ultra-low power mode (buffer power down), the microcontroller, such as a kernel thereof, can transfer local variables, global variables, user stack data, interrupt stack data and a current PC pointer into the NVSRAM. Therefore, during the interruption or abnormal period, the microcontroller 2 can power down the whole buffer 3, and the problem of static leakage power consumption caused by the SRAM is solved. In addition, after the buffer 3 is powered on again, the microcontroller 2 can quickly restore the field of the buffer 3 before power failure and continue to execute programs without re-importing all instructions and data from the beginning. With the development of the process, the occupied proportion and the occupied area of the buffer 3 in the whole system on chip 100 are larger and larger; the advantages of the present invention will also be increasingly highlighted.

Since the area of each NVSRAM is larger than that of the corresponding SRAM, for example, in an embodiment, the area of each NVSRAM is larger than that of the original 6T-SRAM 1/3, so that the buffer 3 of the system on chip of the present invention can make various different adjustments to the adopted ratio of NVSRAMs and SRAMs according to the application requirements of different systems on chip 100, mainly considering the area of the buffer 3.

According to an embodiment of the present invention, if the on-chip system 100 has strict requirements on the area of the registers, the area ratio of the NVSRAM to the entire registers can be set to the minimum, such as reducing the capacity to only store global variables, local variables, interrupt stacks, user stacks, and other system field data. This is readily understood by those skilled in the art and the present invention will not be described in detail.

Fig. 2 is a schematic diagram illustrating the structure and program execution process of the register 10 of the system on chip 100 according to the first embodiment of the present invention, wherein the NVSRAM capacity of the register 10 of the system on chip 100 is set to be minimum, that is, only the system field contents, such as global variables, local variables, interrupt stack, user stack, etc., can be stored. The system-on-chip buffer 10 is an instruction data buffer based on von neumann (von neumann) architecture, and includes two parts, an instruction data buffer 12 using NVSRAM and an instruction data buffer 14 using SRAM. As shown in fig. 2, where s3 indicates the time when the system program 16 executed s3 before the system 100 entered the ultra low power mode (buffer 10 powered down), i.e., b, the program I (including instructions and data) 17 was executed, and the program that has not yet been executed is program II 18.

FIG. 3 is a flowchart illustrating a program executed by the system-on-chip 100 employing the register 10 shown in FIG. 2. At step 50, it is determined whether the buffer 10 is to enter a power down mode (ultra low power mode). If the cache 10 is to be powered down, then at step 51 live content (e.g., global and local variables, live data, PC pointers, etc.) is imported into the instruction data cache 12 using NVSRAM before powering down the cache 10 at step 52. In view of the nonvolatile nature of NVSRAM, the instruction data in the instruction data buffer 12 of NVSRAM is also not lost and changed in the event of a power failure. After the buffer 10 is woken up, entering step 53, the microcontroller 2 of the system-on-chip 100 can quickly resume the scene at step 54. In step 55, the system-on-chip 100 only needs to re-import the unexecuted program II18 from the off-chip hard disk 5 to the register 10 via the off-chip memory according to the PC pointer, which saves the time s 3. Thus, the system on chip according to an embodiment of the present invention can quickly continue the program execution, i.e., proceed to step 56.

Fig. 4 is a schematic diagram illustrating the structure and the program execution process of the registers 20 of the system on chip 100 according to a second embodiment of the present invention, wherein the NVSRAM capacity of the registers 20 of the system on chip 100 is also set to be minimum, i.e. only the system site contents can be stored. The system-on-chip buffer 20 is based on a Harvard (Harvard) architecture, i.e., comprising a separate instruction buffer 30 and data buffer 40, wherein the instruction buffer 30 comprises two parts, an instruction buffer 32 using NVSRAM and an instruction buffer 34 using SRAM, and the data buffer 40 comprises two parts, a data buffer 42 using NVSRAM and a data buffer 44 using SRAM. As shown in fig. 4, s4 represents the time when the instruction 36 and data 46 are executed s4, i.e. the instruction I37 and data I47 have been executed, and the instructions and data that have not yet been executed are instruction II38 and data II48 before the system 100 enters the ultra-low power mode (buffer power down), i.e. c.

Similarly, when the system 100 is going to enter the ultra-low power mode (buffer power down), the field content is only imported into the corresponding NVSRAM instruction buffer 32 and NVSRAM data buffer 42. After the power-up of the buffer memory 20 is resumed, the microcontroller 2 of the soc 100 can resume the site quickly, and only the unexecuted command II38 and data II48 need to be imported into the buffer memory 20 from the off-chip hard disk 5 via the off-chip memory 4 again, which saves time s 4.

According to another embodiment of the present invention, if the system-on-chip 100 allows a certain redundancy of the area of the buffer 3, the occupied capacity of the NVSRAM area can be increased correspondingly compared to the minimum limit. When the system on chip 100 is going to enter the ultra-low power mode (the buffer 3 is powered down), if the microcontroller 2 happens to execute a certain program, and especially the mode switching time of the system 100 for the certain program is very high, the programmer may request the operating system to store the field content in the NVSRAM area, and at the same time, to introduce a section of instructions or data (part or all) to be processed in the buffer 3 into the NVSRAM area.

FIG. 5 illustrates the structure and program introduction of a von Neumann-based register 10 according to an embodiment of the present invention. As shown in fig. 5, point b represents the point in time when the system 100 enters the ultra-low power mode (buffer power down), and s6 is the time when the program 16 was executed before the system 100 entered the ultra-low power mode (buffer 10 power down). At this time, the unexecuted program II18 includes two parts: program III60 is a program partition within the buffer 10 that the system 100 is going to process, and program IV62 is the remaining program that is not executing on the off-chip memory 4 or off-chip hard disk 5. t1 is the time required for program III60 to be imported from an arbitrary position on the buffer 10 into the buffer 12 using NVSRAM, and t2 is the time required for program IV62 to be imported from the off-chip hard disk 5 or the off-chip memory 4 into the buffer 10. FIG. 6 is a diagram illustrating the structure and program introduction of a register 20 based on the Harvard architecture according to an embodiment of the present invention. As shown in fig. 6, point c represents a time point when the system 100 enters the ultra low power mode (buffer power down), and s7 is a time when the program 16 is executed before the system 100 enters the ultra low power mode. The unexecuted instruction II38 and data II48 include two parts: the command III64 and data III65 are the command area and data area located within the registers 20 that the system 100 will process, and the command IV66 and data IV67 are the unexecuted commands and data that remain located on the off-chip memory 4 or off-chip hard disk 5. t3 is the time taken for instruction III64 to be imported from any location on cache 20 into the NVSRAM instruction area on cache 20 (i.e., NVSRAM instruction cache 32), t4 is the time taken for instruction IV66 to be imported from off-chip memory or off-chip hard disk 5 into cache 20, t5 is the time taken for data III65 to be imported from any location on cache 20 into the NVSRAM data area on cache 20 (i.e., NVSRAM data cache 42), and t6 is the time taken for data IV67 to be imported from off-chip memory 4 or off-chip hard disk 5 into cache 20.

FIG. 7 is a flowchart illustrating program execution by the system-on-chip 100 employing the registers 10, 20 shown in FIGS. 5 and 6. At step 70, a determination is made as to whether the buffers 10, 20 are to enter a power down mode (or ultra low power mode). If the cache 10, 20 is to be powered down, then the field content (e.g., global and local variables, field data, PC pointers, etc.) is imported into the NVSRAM region, such as the instruction cache 32 using NVSRAM, at step 71, before powering down the cache 10, 20 at step 73. Program III60 waiting to be executed (based on von neumann architecture) located in the cache 10 or instruction III64 and data III65 waiting to be executed (based on harvard architecture) in the cache 20 are saved to NVSRAM at step 72. After the buffers 10, 20 are woken up, i.e. the buffers 10, 20 are powered up in step 74, the microcontroller 2 of the system on chip 100 can quickly resume the field in step 75. Then, at step 76, the program saved in NVSRAM is executed continuously, such as program III60 (based on von neumann architecture) or instruction III64 and data III65 (based on harvard architecture). After the instructions and/or data stored in the NVSRAM are executed, the program IV62 (based on von neumann architecture) or the instruction IV66 and the data IV67 (based on harvard architecture) before power-off needs to be imported again from the off-chip.

In the third embodiment of the present invention, the entire buffer is implemented by using NVSRAM, the buffer can not only implement all functions of the conventional buffer, but also the program can be saved after being imported into the buffer, and the buffer can be completely powered down, thereby overcoming the problem of large static leakage power consumption of the buffer. After the power outage is resumed, the program stored in the buffer may cause the microcontroller unit to execute the program following the pre-power outage without re-booting. Therefore, the ultra-fast recovery field can be achieved, extra time is not needed, and the problem of redundant dynamic leakage power consumption when the program is led in for the second time is solved. Fig. 8 is a flowchart illustrating program execution of a buffer of a system on chip according to a third embodiment of the present invention, where the system enters an ultra-low power consumption mode (the buffer is powered down) when the program is executed, the buffer immediately enters a power down mode to wait for being awakened, and after the buffer is powered up, the microcontroller continues to read data in the NVSRAM, and then executes the program before powering down.

Compared with the existing buffer of the system on chip completely using the SRAM, the buffer of the invention partially or completely replaces the SRAM by the NVSRAM, thereby greatly reducing the power consumption (including static and dynamic leakage power consumption) and being capable of recovering from a power-off mode more quickly. Therefore, the method is more suitable for the development requirements of electronic products, such as low power consumption, quick response and the like. The comparison of the advantages and disadvantages of the three embodiments of the present invention compared to the existing register is shown in table 1 below.

In response to a request for entering an ultra-low power mode (buffer power-down), for the existing buffer and the third embodiment of the present invention, the buffer power-down mode is directly entered without doing anything when the request occurs, for the buffer of the first embodiment of the present invention, only field data, a PC pointer, a global variable, a local variable, etc. need to be saved, and the request is responded very quickly, but for the buffer of the second embodiment, in addition to saving the field data, the PC pointer, the global variable, and the local variable, an instruction region and a data region in the buffer to be currently executed need to be saved in the NVSRAM, so the speed in responding the request is slow.

When the site is restored after the ultra-low power mode (buffer power failure) is finished, the existing buffer needs to re-import instructions and data when the site is restored, and the instructions and the data are executed from the beginning, so that the restoration of the site is slow. While the first embodiment of the present invention requires that the program be continuously executed from the off-chip according to the PC pointer, the second and third embodiments of the present invention solve the problem of static leakage power consumption because the data before the power failure of the buffer is saved in the NVSRAM, the data is immediately recovered when the field is recovered, and the buffer can be in the power failure mode when the interrupt or abnormal execution occurs.

If the total area of the existing buffer is A, the storage unit NVSRAM of each buffer is 1/3 larger than the area of the SRAM, for designing the buffer of the first embodiment, if the data stored in the field needs the capacity of 10% of the SRAM, the area of the buffer after the 10% of the SRAM is replaced by the NVSRAM is 1.03A, for designing the buffer of the second embodiment, because the area proportion occupied by the NVSRAM in the buffer of the first embodiment is properly enlarged when the buffer of the second embodiment is designed, the area size of the buffer of the second embodiment ranges from 1.03A to 1.3A. In the third embodiment, all the SRAMs in the buffer are replaced by NVSRAM, so that the area of the buffer in the third embodiment is 1.3A.

In the aspect of power consumption, the SRAM, which is a storage unit in the existing buffer, must be kept in a power-on state all the time to ensure that data is not lost, so that the generated power consumption P4 is the maximum. The buffer of the first embodiment is designed in the invention, some field-recovered data are stored in the NVSRAM, and based on the characteristics of the NVSRAM, the buffer can be powered down when the interruption or abnormal execution occurs, so that the static leakage power consumption is reduced, and therefore, the power consumption P1 generated by designing the buffer of the first embodiment is smaller than P4. However, after the buffer is powered up again, because the proportion of the NVSRAM in the buffer is only a small part and the stored data is limited, a part of instructions and data still needs to be imported again. The buffer of the second embodiment is designed to properly enlarge the area ratio occupied by the NVSRAM in the buffer of the first embodiment, and when the buffer of the second embodiment is stored in the field, more data is stored in the NVSRAM in the second embodiment than in the NVSRAM in the first embodiment, so that the data does not need to be re-imported from the outside of the chip, and the power consumption P2 generated by the second embodiment is designed to be smaller than the power consumption P1 generated by the first embodiment. The third embodiment is designed to replace all the SRAMs with NVSRAMs, which not only can power down the buffer when the execution is interrupted, but also does not need to re-import the program after the buffer power down is recovered, so that the power consumption P3 generated by designing the buffer of the third embodiment is the lowest. In summary, the power consumption of the registers in the 4 manners sequentially includes: p4 > P1 > P2 > P3.

TABLE 1 comparison of the advantages and disadvantages of the present invention with the prior art

The protection of the present invention is not limited to the above embodiments. Variations and advantages that may occur to those skilled in the art may be incorporated into the invention without departing from the spirit and scope of the inventive concept, and the scope of the appended claims is intended to be protected.

Claims

1. A system on a chip, comprising:

a microcontroller; and

the buffer is used for storing the instructions and data read by the microcontroller; wherein the buffer comprises a non-volatile static random access memory; before the cache enters a power down mode, the nonvolatile static random access memory can store the field content of the system on chip;

wherein,

the nonvolatile static random access memory consists of a basic SRAM memory cell and two nonvolatile memory cells based on phase change materials or magnetic memory materials, and data can be kept unchanged all the time even after power failure;

before the buffer enters a power-down mode, the nonvolatile static random access memory can also store part or all of instructions and/or data to be processed by the microcontroller;

and after the buffer is powered up again, the on-chip system recovers the field content from the nonvolatile static random access memory and continues to execute part or all of instructions and/or data which are stored in the nonvolatile static random access memory and are to be processed by the microcontroller before power failure.

2. The system-on-chip as recited in claim 1, wherein the system-on-chip restores the live content from the non-volatile static random access memory when the cache is powered back up, and imports instructions and data from off-chip into the cache to continue execution of the program based on the program pointer in the live content.

3. The system on a chip of claim 1, further wherein the cache is comprised entirely of non-volatile static random access memory.

4. The system-on-chip of claim 3, wherein after the buffer is powered back up, the system-on-chip continues to execute interrupted instructions and data stored in the buffer prior to a power loss.

5. The buffer is applied to a system on chip and used for storing instructions and data read by a microcontroller of the system on chip; wherein the buffer comprises: a non-volatile static random access memory; before the cache enters a power down mode, the nonvolatile static random access memory can store the field content of the system on chip;

wherein,

the nonvolatile static random access memory consists of a basic SRAM memory cell and two nonvolatile memory cells based on phase change materials or magnetic memory materials, and data can be kept unchanged even after power failure.

6. The buffer of claim 5, wherein a size ratio of a capacity of the non-volatile static random access memory in the entire buffer is increased, wherein the non-volatile static random access memory is further capable of storing some or all of instructions and/or data to be processed by the microcontroller in the buffer before the buffer enters the power-down mode.

7. The cache of claim 5, further wherein the cache is comprised entirely of non-volatile static random access memory.