CN103036817A - Server single-board, server single-board realization method and host processor - Google Patents

Abstract

Embodiments of the present invention provide a server single board and an implementation method thereof, which relate to the communication field. The server single board can reduce the delay inside the server and improve the quality of network service. Including: a PCIe switch, a main processor and multiple slave processors. The PCIe switch includes an uplink port and multiple downlink ports; the main processor is connected to the uplink port of the PCIe switch, and multiple slave processors are connected to the PCIe switch respectively. connected to the downstream port of the device; the main processor is used to receive the first Ethernet data packet sent by other boards through the network port, convert the first Ethernet data packet into the first PCIe data packet, and convert the first PCIe data packet through the PCIe switch The packet is forwarded to one or more slave processors; it is also used to receive the second PCIe data packet sent by one or more slave processors, convert the second PCIe data packet into a second Ethernet data packet, and send it to other The single board forwards the second Ethernet data packet.

Description

A server single board, server single board implementation method and main processor

technical field

The invention relates to the communication field, in particular to a server single board, a method for realizing the server single board and a main processor.

Background technique

With the continuous development of communication technology, the number of telecommunication equipment that provides functions such as core computing, information resource management, and information resource services to users is also increasing. Excessive energy consumption not only affects the operating costs of operators, but also causes serious waste of energy. Therefore, the energy saving of telecommunication equipment has gradually become the focus of the industry.

A telecommunications room is generally composed of a large number of servers, switching equipment, access equipment, storage equipment, and network equipment. Among them, servers in various forms (such as rack type, blade type, plug-in card type) are often the components with the highest energy consumption in the telecommunications room. Among many server energy-saving measures, using low-power processor chips to build low-power servers is a very effective measure.

The existing technology includes a server composed of multiple low-power processor chips. In this system, in order to enable data to be reasonably configured and scheduled among different processor chips, the processor chips can be connected through high-speed Ethernet Network interface for interconnection. Due to the limited number of Ethernet interfaces of each processor chip, the processor chips are usually interconnected in a tree structure. When the number of processor chips is large, the depth of the tree structure needs to be large to realize each processing. But in this way, for the processor chips at the leaf nodes, if the processors of the two leaf nodes want to realize data interaction, they must go through multi-level Ethernet switching, which will The delay is increased, which seriously affects the quality of network services.

Contents of the invention

Embodiments of the present invention provide a server single board, a method for implementing the server single board, and a main processor, which are used to solve the problem in the prior art that the internal delay of the server is large, thereby seriously affecting the quality of network service.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

In the first aspect, the first implementation of the embodiment of the present invention provides a server single board, which is applied to a server system, and the server system further includes at least one other single board connected to the server single board, and the server single board Board includes:

A PCIe switch, a main processor and a plurality of slave processors, the PCIe switch includes an uplink port and a plurality of downlink ports;

The main processor is connected to the uplink port of the PCIe switch, and the multiple slave processors are respectively connected to the downlink port of the PCIe switch;

The main processor is used to receive the first Ethernet data packet sent by the other single board through the network port, convert the first Ethernet data packet into the first PCIe data packet, and pass through the PCIe switch. The uplink port forwards the first PCIe data packet to the PCIe switch, so that the PCIe switch forwards the first PCIe data packet to the slave processor connected to the downlink port;

The main processor is also used to receive the second PCIe packet sent by the slave processor through the PCIe switch, convert the second PCIe packet into a second Ethernet packet, and pass through the network port Forwarding the second Ethernet data packet to the other single board.

With reference to the first possible implementation of the first aspect, in the second possible implementation, the master processor is further configured to receive, through the PCIe switch, the third PCIe data packet sent by one of the slave processors , and forward the third PCIe data packet to another slave processor through the PCIe switch.

In combination with the first or second possible implementation of the first aspect, in a third possible implementation, the main processor is used to convert the second PCIe data packet into a second Ethernet data packet, specifically:

If the payload of the second PCIe data packet includes a complete Ethernet data packet, the main processor is used to directly extract the Ethernet data packet to obtain the second Ethernet data packet; or,

If the payload of the second PCIe data packet includes the payload of the Ethernet data packet, the main processor is configured to extract the payload of the Ethernet data packet for encapsulation to obtain the second Ethernet data packet.

With reference to any of the first to third possible implementations of the first aspect, in a fourth possible implementation, the master processor is further configured to generate a path configuration table, where the path configuration table includes a slave processor identifier and routing information corresponding to the slave processor identifier;

The main processor is used to convert the first Ethernet data packet into a first PCIe data packet, and forward the first PCIe data packet to the PCIe switch through the uplink port of the PCIe switch, Making the PCIe switch forward the first PCIe packet to the slave processor connected to the downlink port is specifically:

The main processor is used to:

Encapsulate the first Ethernet data packet as a whole into the payload of the first PCIe data packet or the main processor is used to extract the payload in the first Ethernet data packet, and the first Ethernet data The payload in the packet is encapsulated into the payload of the first PCIe data packet; according to the path configuration table and the slave processor identification of the slave processor, the first routing information corresponding to the slave processor is obtained, and the The first routing information is added to the header of the first PCIe data packet; the first PCIe data packet is forwarded to the PCIe switch through the uplink port of the PCIe switch, so that the PCIe switch according to The first routing information in the header of the first PCIe data packet forwards the first PCIe data packet to the slave processor connected to the downlink port.

With reference to any one of the first to fourth possible implementations of the first aspect, in a fifth possible implementation, the main processor is further configured to:

receiving the loading request from the processor through the PCIe switch;

Read operating system and application image files according to the loading request;

and sending the read operating system image file to the slave server through the PCIe switch, so that the slave processor starts an operating system according to the operating system image file.

In combination with any of the first to fifth possible implementations of the first aspect, in the sixth possible implementation,

The main processor is also used to:

Send an online detection message to the slave processor through the PCIe switch, to detect whether the slave processor is connected normally;

When it is determined that a slave processor fails to connect, the data packet sent to the one slave processor is sent to another slave processor through the PCIe switch according to a preset sending strategy.

In combination with the sixth implementation manner of the first aspect, in a seventh possible implementation manner, when it is determined that the one slave processor resumes the connection, the data packet sent to the other slave processor is passed through the PCIe The switch forwards to the one slave processor.

In the second aspect, in the first possible implementation manner, this embodiment discloses a method for implementing a server board, the server board is applied to a server system, and the server system further includes a server board connected to the server board. at least one other board, including:

The main processor receives the first Ethernet data packet sent by the other single board through the network port;

The main processor converts the first Ethernet data packet into the first PCIe data packet;

The main processor forwards the first PCIe data packet to the PCIe switch through the uplink port of the PCIe switch, so that the PCIe switch forwards the first PCIe data packet to the The slave processor connected to the downlink port;

The main processor receives the second PCIe data packet sent from the processor through the PCIe switch;

The main processor converts the second PCIe data packet into a second Ethernet data packet;

The main processor forwards the second Ethernet data packet to the other boards through the network port.

With reference to the first possible implementation of the second aspect, in the second possible implementation, the method further includes:

The main processor receives the third PCIe packet sent by one of the slave processors through the PCIe switch, and forwards the third PCIe packet to another slave processor through the PCIe switch device.

In combination with any of the first to second possible implementations of the second aspect, in a third possible implementation, converting the second PCIe data packet into a second Ethernet data packet by the main processor includes:

If the payload of the second PCIe data packet includes a complete Ethernet data packet, the main processor directly extracts the Ethernet data packet to obtain the second Ethernet data packet; or,

If the payload of the second PCIe data packet includes the payload of the Ethernet data packet, the main processor extracts the payload of the Ethernet data packet and encapsulates it to obtain the second Ethernet data packet.

In combination with any of the first to third possible implementation manners of the second aspect, in a fourth possible implementation manner, the method further includes:

generating a path configuration table, the path configuration table including a slave processor identifier and routing information corresponding to the slave processor identifier;

The host processor converting the first Ethernet packet into the first PCIe packet includes:

Encapsulate the first Ethernet data packet as a whole into the payload of the first PCIe data packet or the main processor extracts the payload in the first Ethernet data packet, and encapsulate the first Ethernet data packet The payload in the packet is encapsulated into the payload of the first PCIe packet; according to the path configuration table and the slave processor identification of the slave processor, the first routing information corresponding to the slave processor is obtained, and the The first routing information is added to the header of the first PCIe data packet;

The main processor forwards the first PCIe data packet to the PCIe switch through the uplink port of the PCIe switch, so that the PCIe switch forwards the first PCIe data packet to the The slave processor connected to the downstream port includes:

The first PCIe data packet is forwarded to the PCIe switch through the uplink port of the PCIe switch, so that the PCIe switch forwards the first PCIe data packet according to the first routing information in the header of the first PCIe data packet The first PCIe data packet is forwarded to the slave processor connected to the downlink port.

In combination with any of the first to fourth possible implementation manners of the second aspect, in a fifth possible implementation manner, the method further includes:

The main processor receives the loading request sent from the processor through the PCIe switch;

Read operating system and application image files according to the loading request;

and sending the read operating system image file to the slave server through the PCIe switch, so that the slave processor starts an operating system according to the operating system image file.

With reference to any of the first to fifth possible implementations of the second aspect, in a sixth possible implementation, the master processor sends an online detection message to the slave processor through the PCIe switch to detect Whether the slave processor is connected normally;

When it is determined that a slave processor fails to connect, the master processor sends the data packet sent to the one slave processor to another slave processor through the PCIe switch according to a preset sending policy.

With reference to the sixth possible implementation of the second aspect, in the seventh possible implementation, when it is determined that the one slave processor resumes the connection, pass the data packet sent to the other slave processor through the The PCIe switch forwards to the one slave processor.

In the third aspect, in the first possible manner, this embodiment discloses a processor, which is applied to a server board, and the main processor includes:

The first receiving module is configured to receive the first Ethernet data packet sent by other boards through the network port;

A first converting module, configured to convert the first Ethernet data packet received by the first receiving module into a first PCIe data packet;

The first sending module is used to forward the first PCIe data packet converted by the first conversion module to the slave processor connected to the PCIe switch through the PCIe switch;

A second receiving module, configured to receive the second PCIe data packet sent from the processor through the PCIe switch;

A second converting module, configured to convert the second PCIe data packet received by the second receiving module into a second Ethernet data packet;

The second sending module is configured to forward the second Ethernet data packet converted by the second conversion module to the other boards through the network port.

With reference to the first possible implementation of the third aspect, in the second possible implementation, the first sending module is specifically configured to send the first PCIe data packet via the PCIe switch through the uplink port of the PCIe switch To the slave processor connected to the downstream port of the PCIe switch;

The second receiving module is specifically configured to receive from the uplink port of the PCIe switch the information sent by the slave processor from the downlink port of the PCIe switch and arrive at the PCIe switch via the PCIe switch The second PCIe data packet of the uplink port.

With reference to any of the first to second possible implementations of the third aspect, in a third possible implementation, the second receiving module is further configured to receive one of the slave processors through the PCIe switch. The third PCIe packet;

The first sending module is further configured to forward the third PCIe data packet received by the second receiving module to another slave processor through the PCIe switch.

With reference to any of the first to third possible implementation manners of the third aspect, in a fourth possible implementation manner, the main processor further includes:

A configuration table generating module, configured to generate a path configuration table, the path configuration table including a slave processor identifier and routing information corresponding to the slave processor identifier;

The first conversion module includes:

Payload processing module, for encapsulating the first Ethernet data packet as a whole into the payload of the first PCIe data packet or for extracting the payload in the first Ethernet data packet, the first The payload in the Ethernet packet is encapsulated into the payload of the first PCIe packet;

A header processing module, configured to obtain first routing information corresponding to the slave processor according to the path configuration table and the slave processor identifier of the slave processor, and add the first routing information to the second A header of a PCIe data packet, so that after the PCIe switch receives the first PCIe data packet sent by the first sending module, according to the first route in the first PCIe data packet header information to forward the first PCIe packet to the slave processor.

With reference to any of the first to fourth possible implementations of the third aspect, in a fifth possible implementation, the third receiving module is configured to receive the loading request sent by the slave processor through the PCIe switch, Read operating system and application image files according to the loading request;

The third sending module is configured to send the read operating system image file to the slave processor through the PCIe switch, so that the slave processor starts an operating system according to the operating system image file.

With reference to any one of the first to fifth possible implementation manners of the second aspect, in a sixth possible implementation manner, the main processor further includes:

A detection module, configured to send an online detection message to the slave processor through the PCIe switch, to detect whether the slave processor is connected normally;

When the detection module determines that a slave processor connection fails, the first sending module is also used for:

According to the preset sending strategy, the data packet sent to the slave processor is sent to another slave processor through the PCIe switch; when it is determined that the connection is restored from the processor, it will be sent to the other The data packet of the slave processor is forwarded to the one slave processor through the PCIe switch.

The embodiment of the present invention provides a server board, a method for implementing the server board, and a main processor. The server board is applied to a server system, and the server system further includes at least one other board connected to the server board. The server board is The board specifically includes a PCIe switch, a main processor and multiple slave processors, wherein the PCIe switch includes an uplink port and a plurality of downlink ports; the main processor is connected to the uplink port of the PCIe, and the multiple slave processors are respectively connected to The downlink port of the PCIe switch is connected. Using such a structure of the server board, the main processor can send and receive data with other boards through the network port, and the main processor is connected to each slave processor through the PCIe switch. Therefore, the slave processor data Both sending and receiving and data exchange between slave processors can be completed by the main processor. In this way, the interconnection between all processors can be realized without using a multi-level tree structure, thereby avoiding data forwarding between multi-level processors, reducing the delay of the server single board, and improving network service efficiency. quality.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of a server board provided by an embodiment of the present invention;

FIG. 2a is a schematic structural diagram of a main processor provided by an embodiment of the present invention;

FIG. 2b is a schematic structural diagram of another main processor provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of a connection structure of a server board provided by an embodiment of the present invention;

FIG. 4 is a schematic flowchart of a method for implementing a server single board provided by an embodiment of the present invention;

FIG. 5 is a schematic flowchart of another method for implementing a server single board provided by an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The server single board 1 provided by the embodiment of the present invention can be applied to a server system, and the server system can also include at least one other single board 2 connected to the server single board 1. As shown in FIG. 1, the server single board 1 can include:

A PCIe switch 11, a master processor 12 and multiple slave processors 13, the PCIe switch 11 may include one uplink port and multiple downlink ports.

The master processor 12 is connected to an uplink port of the PCIe switch 11 , and multiple slave processors 13 are connected to downlink ports of the PCIe switch 11 respectively.

The main processor 12 is used to receive the first Ethernet data packet sent by other single boards 2 through the network port 14, convert the first Ethernet data packet into the first PCIe data packet, and convert the first Ethernet data packet into the first PCIe data packet through the uplink port of the PCIe switch 11. The first PCIe data packet is forwarded to the PCIe switch 11, so that the PCIe switch 11 forwards the first PCIe data packet to the slave processor 13 connected to the downlink port.

For example, the process in which the main processor 12 converts the first Ethernet data packet into the first PCIe data packet may specifically include: the main processor 12 encapsulates the first Ethernet data packet as a whole into the payload of the first PCIe data packet , the conversion of the data packet format can be realized efficiently and quickly by adopting such an overall encapsulation method; or, the main processor 12 can also extract the payload in the first Ethernet data packet, and convert the first Ethernet data packet The payload in the package is encapsulated into the payload of the first PCIe data packet, so that the encapsulated PCIe data packet does not contain non-critical data including the packet header of the Ethernet data packet, which greatly reduces the PCIe data packet capacity, improving the encapsulation efficiency of PCIe data packets.

The main processor 12 is also used to receive the second PCIe data packet sent from the processor 13 through the PCIe switch 11, convert the second PCIe data packet into a second Ethernet data packet, and transmit the data to other single boards through the network port 14. 2. Forward the second Ethernet data packet.

Correspondingly, the process in which the main processor 12 converts the second PCIe data packet into the second Ethernet data packet may specifically include: if the payload of the second PCIe data packet includes a complete Ethernet data packet, the main processor 12 may Directly extract the Ethernet data packet to obtain the second Ethernet data packet; or, if the payload of the second PCIe data packet includes the payload of the Ethernet data packet, the main processor 12 can extract the net of the Ethernet data packet The payload is encapsulated to obtain the second Ethernet data packet.

In this embodiment of the present invention, the processor may include an x86 processor or an ARM processor. Wherein, the x86 processor specifically refers to an x86-based low-power processor. In practical applications, due to the low cost and low power consumption of processors based on the ARM architecture, a server with higher performance can be obtained by clustering multiple lower-performance ARM processors, while ensuring server performance. The production cost is greatly reduced, and the power consumption of the server is reduced.

The server single board provided by the embodiment of the present invention is applied to a server system, and the server system further includes at least one other single board connected to the server single board, and the server single board specifically includes a PCIe switch, a main processor, and a plurality of slave A processor, wherein the PCIe switch includes an uplink port and multiple downlink ports; the main processor is connected to the uplink port of the PCIe, and multiple slave processors are respectively connected to the downlink ports of the PCIe switch. Using such a structure of the server board, the main processor can send and receive data with other boards through the network port, and the main processor is connected to each slave processor through the PCIe switch. Therefore, the slave processor data Both sending and receiving and data exchange between slave processors can be completed by the main processor. In this way, the interconnection between all processors can be realized without using a multi-level tree structure, thereby avoiding data forwarding between multi-level processors, reducing the delay of the server single board, and improving network service efficiency. quality.

Further, the main processor 12 can also be used to receive the third PCIe data packet sent by one of the slave processors 13 through the PCIe switch 11, and forward the third PCIe data packet to another slave through the PCIe switch 11. Processor 13.

In this way, multiple slave processors 13 can control the PCIe switch 11 for data exchange through the main processor 12, thereby avoiding data forwarding between multi-level processors, reducing the delay of the server single board, and improving quality of network service.

Further, the main processor 12 can also be used for:

The PCIe switch 11 is initialized, and the registers of the PCIe switch 11 are configured so that the PCIe switch 11 can work normally.

Wherein, the initialization of the PCIe switch 11 by the main processor 12 may specifically include: allocating routing information for each slave processor 13 connected to the PCIe switch 11 .

It should be noted that, in the embodiment of the present invention, the routing information may specifically include BDF (collectively referred to as Bus (bus), Device (device), and Function (function) numbers) information or BAR (Base Address Register, base address register) space address.

The main processor 12 can also be used to generate a path configuration table, the path configuration table includes the identifier of the slave processor 13 and routing information corresponding to the identifier of the slave processor 13, wherein the routing information corresponding to the identifier of the slave processor 13 The information is the same as the routing information assigned for the slave processor 13 indicated by the processor identification.

Further, the main processor 12 converts the first Ethernet data packet into the first PCIe data packet, and forwards the first PCIe data packet to the PCIe switch 11 through the uplink port of the PCIe switch 11, so that the PCIe switch 11 converts the first PCIe data packet into the first PCIe data packet. A PCIe packet is forwarded to the specific process from the processor 13 connected to the downlink port and can be as follows:

First, the main processor 12 can encapsulate the first Ethernet data packet as a whole into the payload of the first PCIe data packet or the main processor 12 can extract the payload in the first Ethernet data packet, and the first Ethernet The payload in the data packet is encapsulated into the payload of the first PCIe data packet.

After completing the encapsulation of the first PCIe packet, the master processor can obtain the first routing information corresponding to the slave processor 13 according to the path configuration table and the slave processor identification of the slave processor 13, and add the first routing information to the head of the first PCIe packet; the first PCIe packet is forwarded to the PCIe switch 11 by the uplink port of the PCIe switch 11, so that the PCIe switch 11 can be based on the first PCIe packet in the first PCIe packet header. The routing information forwards the first PCIe data packet to the slave processor 13 connected to the downlink port.

For example, the identity information of each slave processor is recorded in the path configuration table, and the identity information can be the bus ID where the processor resides or the MAC (Medium Access Control, medium access control layer) address of the slave processor, The identity information of each slave processor corresponds to a preset routing information. Before the master processor 12 forwards the first PCIe data packet through the PCIe switch 11, the slave processor identification of the slave processor 13 according to the path configuration table Obtain the routing information corresponding to the slave processor 13, add the routing information to the header of the first PCIe packet, and the PCIe switch 11 can search the path configuration table by the routing information recorded in the header of the first PCIe packet, according to the The path configuration table obtains routing information of one or more slave processors 13 , so as to forward the first PCIe data packet to one or more slave processors 13 .

Of course, multiple slave processors 13 can also exchange data according to the path configuration table. For example, after the main processor 12 completes the initialization of the PCIe switch 11 and the scanning of the slave processor 13, the path configuration table is generated, and the path configuration table is sent to each slave processor 13. When the first slave processor needs to send When the second slave processor forwards data, the data packet can be sent to the PCIe switch 11, the identity information of the second slave processor is added in the forwarded data packet, and the PCIe switch 11 can query the path configuration table, thereby The routing information of the second slave processor is determined according to the identity information of the second slave processor so as to complete the data forwarding.

After the master processor 12 initializes the PCIe switch 11, the slave processor 13 can also be used for:

A loading request is sent to the main processor 12 through the PCIe switch 11 to request loading of necessary operating systems and application programs.

Correspondingly, after receiving the loading request, the main processor 12 can also be used to: read the operating system and the application program image file according to the loading request; send the read operating system image file through the PCIe switch 11 to The slave server 13 enables the slave processor 13 to start the operating system according to the operating system image file.

In this way, the image file of the operating system and the application program can be placed in the storage medium of the main processor 12 in advance, and when the slave processor 13 needs to be loaded, only the image file needs to be loaded from the storage medium of the main processor 12. Just take out and send to the slave processor 13, so that each slave processor 13 does not need to prepare its own operating system and application program, saves the memory of the slave processor 13, and improves the processing efficiency of the slave processor 13.

Further, the main processor 12 can also be used for:

An online detection message is sent to the slave processor 13 through the PCIe switch 11 to detect whether the slave processor 13 is connected normally.

Specifically, when it is determined that a slave processor connection fails, the data packet sent to the slave processor can be sent to another slave processor through the PCIe switch 11 according to a preset sending policy; when it is determined that the slave processor recovers When connected, a data packet sent to another slave processor is forwarded to the slave processor through the PCIe switch 11 . When the connection fails, it means that the slave processor is faulty (or the link between the two master processors is faulty), so the data needs to be forwarded to other slave processors to process the data. The "preset sending strategy" here is not limited specifically. For example, a certain slave processor can be defined in advance to process data when other slave processors (or links) fail. If other slave processors (or links) If there is a failure, the master processor will transfer the data to the dedicated slave processor for processing; or the "preset sending strategy" can also be the preset strategy of "sending according to the load of each slave processor" (like sending packets to slave processors with less load).

For example, there is a heartbeat detection mechanism between the master processor 12 and each slave processor 13, and the master processor 12 will periodically send creed detection messages to each slave processor 13 to detect whether the slave processors 13 are connected normally. When the heartbeat of a slave processor is lost, the master processor 12 migrates the service of the slave processor to another slave processor or other standby slave processors.

The main processor 12 provided by the embodiment of the present invention can be applied to the above-mentioned server single board. As shown in FIG. 2a, the main processor 12 includes:

The first receiving module 21 is configured to receive the first Ethernet data packet sent by other boards through the network port.

The first converting module 22 is configured to convert the first Ethernet data packet received by the first receiving module 21 into a first PCIe data packet.

The first sending module 23 is configured to forward the first PCIe data packet converted by the first converting module 22 to a slave processor connected to the PCIe switch through the PCIe switch.

The second receiving module 24 is configured to receive the second PCIe data packet sent from the processor through the PCIe switch.

The second converting module 25 is configured to convert the second PCIe data packet received by the second receiving module 24 into a second Ethernet data packet.

The second sending module 26 is configured to forward the second Ethernet data packet converted by the second converting module 25 to other boards through the network port.

The main processor provided by the embodiment of the present invention is applied to a server single board, and the server single board is applied to a server system, and the server system also includes at least one other single board connected to the server single board, and the server single board specifically includes a PCIe A switch, a main processor and a plurality of slave processors, wherein the PCIe switch includes an uplink port and a plurality of downlink ports; the main processor is connected to the uplink port of the PCIe, and a plurality of slave processors are respectively connected to the PCIe switch connected to the downstream port. Using such a structure of the server board, the main processor can send and receive data with other boards through the network port, and the main processor is connected to each slave processor through the PCIe switch. Therefore, the slave processor data Both sending and receiving and data exchange between slave processors can be completed by the main processor. In this way, the interconnection between all processors can be realized without using a multi-level tree structure, thereby avoiding data forwarding between multi-level processors, reducing the delay of the server single board, and improving network service efficiency. quality.

Wherein, the first sending module 23 is specifically configured to send the first PCIe data packet to the slave processor connected to the downlink port of the PCIe switch via the PCIe switch through the uplink port of the PCIe switch.

The second receiving module 24 is specifically configured to receive, from the uplink port of the PCIe switch, the second PCIe data packet sent from the processor from the downlink port of the PCIe switch and arriving at the uplink port of the PCIe switch via the PCIe switch.

Further, the second receiving module 24 can also be used to receive one of the third PCIe packets sent from the processor through the PCIe switch; the first sending module 23 can also be used to receive the second receiving module through the PCIe switch. The third PCIe packet is forwarded to another slave processor.

In this way, multiple slave processors can control the PCIe switch for data exchange through the main processor 12, thereby avoiding data forwarding between multi-level processors, reducing the delay of the server single board, and improving network performance. the quality of the service.

In the embodiment of the present invention, the first conversion module 22 can also be used for:

Encapsulating the first Ethernet data packet as a whole into the payload of the first PCIe data packet, or extracting the payload in the first Ethernet data packet, and encapsulating the payload in the first Ethernet data packet into the first PCIe data packet In the payload of the data packet;

Correspondingly, the second conversion module 25 can also be used for:

If the payload of the second PCIe packet includes a complete Ethernet packet, directly extract the Ethernet packet to obtain the second Ethernet packet, or if the payload of the second PCIe packet includes the net payload of the Ethernet packet The payload of the Ethernet data packet is extracted and encapsulated to obtain a second Ethernet data packet.

Further, as shown in FIG. 2b, the main processor 12 may also include:

The configuration table generating module 27 is configured to generate a path configuration table, where the path configuration table includes a slave processor identifier and routing information corresponding to the slave processor identifier.

The first conversion module 22 may also include:

The payload processing module 221 is used for encapsulating the first Ethernet data packet as a whole in the payload of the first PCIe data packet or for extracting the payload in the first Ethernet data packet, and encapsulating the first Ethernet data packet into the payload of the first Ethernet data packet The payload of is encapsulated into the payload of the first PCIe data packet.

The header processing module 222 is used to obtain the first routing information corresponding to the slave processor according to the path configuration table and the slave processor identification of the processor, and add the first routing information to the header of the first PCIe data packet After receiving the first PCIe data packet sent by the first sending module 23, the PCIe switch forwards the first PCIe data packet to the slave processor according to the first routing information in the header of the first PCIe data packet.

It should be noted that, in the embodiment of the present invention, the routing information may specifically include BDF (collectively referred to as Bus (bus), Device (device), and Function (function) numbers) information or BAR (Base Address Register, base address register) space address.

As shown in Figure 2b, the main processor 12 may also include:

The third receiving module 28 is configured to receive a loading request sent from the processor through the PCIe switch, and read the operating system and application program image files according to the loading request.

The third sending module 29 is configured to send the read operating system image file to the slave processor through the PCIe switch, so that the slave processor starts the operating system according to the operating system image file.

In this way, the image files of the operating system and application programs can be stored in the storage medium of the main processor 12 in advance, and when the slave processor needs to be loaded, only the image file needs to be taken out from the storage medium of the main processor 12. It only needs to be sent to the slave processors, so that each slave processor does not need to prepare its own operating system and application program, saves the memory of the slave processors, and improves the processing efficiency of the slave processors.

Further, the main processor 12 may also include:

The detection module 20 is used to send an online detection message to the slave processor through the PCIe switch, to detect whether the slave processor is normally connected;

When the detection module 20 determines that a slave processor connection fails, the first sending module 23 can also be used for:

According to the preset sending policy, the data packet sent to the slave processor is sent to another slave processor through the PCIe switch; when it is determined that a slave processor resumes the connection, the data packet sent to another slave processor is sent through PCIe The switch forwards to the one slave processor. When the connection fails, it means that the slave processor is faulty (or the link between the two master processors is faulty), so the data needs to be forwarded to other slave processors to process the data. The "preset sending strategy" here is not limited specifically. For example, a certain slave processor can be defined in advance to process data when other slave processors (or links) fail. If other slave processors (or links) If there is a failure, the master processor will transfer the data to the dedicated slave processor for processing; or the "preset sending strategy" can also be the preset strategy of "sending according to the load of each slave processor" (like sending packets to slave processors with less load).

For example, there is a heartbeat detection mechanism between the master processor 12 and each slave processor, and the master processor 12 will periodically send creed detection messages to each slave processor to detect whether the slave processors are connected normally. When the heartbeat of a slave processor is lost, the master processor 12 migrates the service of the slave processor to another slave processor or other standby slave processors.

It should be noted that, in the embodiment of the present invention, the master processor 12 may further include a memory unit and a storage medium, and the structures of the master processor 12 and the slave processor 13 may be the same. Wherein, the memory unit may specifically include DRAM (dynamic random access memory, dynamic random access memory) or SRAM (static random access memory, static random access memory); the storage medium may specifically include Flash (flash memory), SATA (serial advanced technology attachment, serial advanced technology attachment), SAS (Serial Attached SCSI, serial connection interface) hard disk or SSD (solid state disk, solid state disk), this storage medium can be used to store image files of operating systems and applications.

FIG. 3 is a schematic diagram of a connection structure of a server board 1 with low power consumption provided by an embodiment of the present invention. The server single board 1 includes a server bottom board 31, and the server bottom board 31 is specifically composed of a power supply 311, a single board management controller 312 and a cooling device (not shown in the figure). A main processor 12 and six slave processors 13 are connected to each other through a PCIe switch 11. In the embodiment of the present invention, the main processor 12 and the slave processors 13 all use multifunctional daughter cards with the same structure. The function daughter card mainly includes ARM processor, memory unit and storage medium.

Wherein, the server chassis 31 has a plurality of slots, and the multi-function daughter cards as the master processor 12 and the slave processor 13 are inserted into these slots. The slots are further divided into master slots and slave slots, and the slot address of the master slot and the slot address of the slave slot are different. When each multi-function sub-card is inserted into the slot and powered on, the ARM processor inserted into the multi-function sub-card of the main slot automatically configures itself as the main processor by identifying the address of the slot, and inserts itself into the slave slot. The ARM processor on the slot's multifunction daughter card automatically configures itself as a slave processor by recognizing the slot address.

The ARM processor of the main processor 12 is connected to the RC (rootcomplex, root component) interface of the PCIe switch 11, and the EP (end point, terminal equipment) interface of the PCIe switch 11 is connected to the ARM processor of the slave processor 13.

In the embodiment of the present invention, the main processor 12 includes a processing unit, a memory, and a storage medium, wherein the processing unit may include a receiving module, a conversion module, a sending module, an initialization module, a table look-up module, a power-down protection module, an XOR exclusive-or Acceleration module and security encryption module.

The main processor 12 is connected to the network port 14 of the server board 1. The main processor 12 is the service distribution point and the service convergence point of the slave processor 13, and the multi-function sub-card as the main processor 12 is an intelligent network card. The smart network card is mainly responsible for the sending and receiving of PCIe data messages and the sending and receiving of Ethernet messages; the address (including address routing, ID routing, implicit routing, etc.) Analysis of network packets and upper-layer packets, and query path configuration table according to the characteristics of Ethernet and upper-layer packets; format conversion between PCIe data packets and Ethernet packets. In addition to the above functions, the master processor 12 can also complete the initialization of the PCIe switch 11, scan the slave processor 13, manage the PCIe switch 11, and so on.

After the server board is powered on and started, the main processor 12 and the slave processor 13 are initialized respectively. After the main processor 12 completes the initialization of the PCIe switch 11, the system enters the loading stage. The slave processor 13 requests the host processor 42 to load the operating system and the application program through the PCIe switch 11 . After the main processor 12 receives the request from the processor 13, it reads the relevant operating system and application program from the storage medium (such as: Flash, SATA, SAS hard disk, SSD hard disk, etc.) to slave processor 13.

After completing the initialization of the PCIe switch 11 and the scanning of the slave processors 13 , the master processor 12 generates a path configuration table, and sends the table to each slave processor 13 . The slave processor 13 can communicate with the master processor 12 through the PCIe switch 11 according to the path configuration table, and can also communicate with other slave processors 13 on the server board.

In the embodiment of the present invention, the application program running on each slave processor 13 can be dynamically deployed, and the user can configure the working mode of each slave processor 13 through the master processor 12 for different applications. The slave processors 13 are in a cluster relationship, and each slave processor 13 runs its own operating system and application program. The main processor 12 also runs its own operating system and application programs. For example, the first slave processor 131 runs a calculation function, and the second slave processor 132 runs a storage function. These two slave processors can cooperate with each other to complete a specific service function. When the slave processor 131 in charge of calculation needs to get data from the slave processor 132 in charge of storage, the data exchange can be completed directly through the PCIe switch 11, that is, the data exchange is completed locally, which can reduce the delay and increase the bandwidth of the external network. No effect.

Further, the main processor 12 can also be used for:

An online detection message is sent to the slave processor 13 through the PCIe switch 11 to detect whether the slave processor 13 is connected normally.

Specifically, as shown in FIG. 3 , when it is determined that the first slave processor 131 fails to connect, the data packet sent to the first slave processor 131 is sent to the second slave processor 132 through the PCIe switch 11 .

For example, there is a heartbeat detection mechanism between the master processor 12 and each slave processor 13, and the master processor 12 will periodically send creed detection messages to each slave processor 13 to detect whether the slave processors 13 are connected normally. When the heartbeat of the first slave processor 131 is lost, the master processor 12 migrates the services on the first slave processor 131 to the second slave processor 132 or other standby slave processors.

It should be noted that, in the embodiment of the present invention, between the main processor and the slave processor, and between the slave processor and the slave processor, all can communicate through the Ethernet message sending and receiving interface customized under the Linux kernel state . In a specific physical form, the server single board provided by the embodiment of the present invention may be a rack-type server or a blade-type server.

The server board with such a structure can realize the interconnection between all processors without adopting a multi-level tree structure, thereby avoiding data forwarding between multi-level processors and reducing the delay of the server board. Improved network service quality.

The server single board implementation method provided by the embodiment of the present invention, as shown in FIG. 4, the server single board can be applied to a server system, and the server system also includes at least one other single board connected to the server single board. The method includes:

S401. The main processor receives the first Ethernet data packet sent by other boards through the network port.

It should be noted that, in the embodiment of the present invention, the structure of the master processor and the slave processor may be the same.

Specifically, the main processor may receive the first Ethernet data packet sent by other boards from the network port through the first receiving module 21 .

S402. The main processor converts the first Ethernet data packet into a first PCIe data packet.

Specifically, the main processor can convert the first Ethernet data packet into the first PCIe data packet through the first conversion module 22 . For example, the main processor can encapsulate the first Ethernet data packet into the payload of the first PCIe data packet, and the conversion of the data packet format can be realized efficiently and quickly by adopting such an overall encapsulation method; or, the main processor The device can also extract the payload in the first Ethernet data packet, and encapsulate the payload in the first Ethernet data packet into the payload of the first PCIe data packet, so that the encapsulated PCIe data packet Non-critical data including the header of the Ethernet data packet is not included in the data packet, which greatly reduces the capacity of the PCIe data packet and improves the encapsulation efficiency of the PCIe data packet.

S403. The main processor forwards the first PCIe data packet to the PCIe switch through the uplink port of the PCIe switch, so that the PCIe switch forwards the first PCIe data packet to the slave processor connected to the downlink port.

Specifically, the master processor may forward the first PCIe data packet to one or more slave processors through the first sending module 23 .

S404. The master processor receives the second PCIe data packet sent from the slave processor through the PCIe switch.

S405. The main processor converts the second PCIe data packet into a second Ethernet data packet.

Correspondingly, if the payload of the second PCIe data packet includes a complete Ethernet data packet, the main processor can directly extract the Ethernet data packet to obtain the second Ethernet data packet; or, if the second PCIe data packet The payload includes the payload of the Ethernet data packet, and the main processor can extract the payload of the Ethernet data packet and encapsulate it to obtain the second Ethernet data packet.

S406. The main processor forwards the second Ethernet data packet to other boards through the network port.

In this embodiment of the present invention, the processor may include an x86 processor or an ARM processor. Wherein, the x86 processor specifically refers to an x86-based low-power processor. In practical applications, due to the low cost and low power consumption of processors based on the ARM architecture, a server with higher performance can be obtained by clustering multiple lower-performance ARM processors, while ensuring server performance. The production cost is greatly reduced, and the power consumption of the server is reduced.

The embodiment of the present invention provides a method for implementing a server single board. The server single board is applied to a server system, and the server system further includes at least one other single board connected to the server single board. The server single board specifically includes a PCIe switch, and the main A processor and a plurality of slave processors, wherein the PCIe switch includes an uplink port and a plurality of downlink ports; the main processor is connected to the uplink port of the PCIe, and a plurality of slave processors are respectively connected to the downlink ports of the PCIe switch . Using such a structure of the server board, the main processor can send and receive data with other boards through the network port, and the main processor is connected to each slave processor through the PCIe switch. Therefore, the slave processor data Both sending and receiving and data exchange between slave processors can be completed by the main processor. In this way, the interconnection between all processors can be realized without using a multi-level tree structure, thereby avoiding data forwarding between multi-level processors, reducing the delay of the server single board, and improving network service efficiency. quality.

Further, as shown in FIG. 5, the method for implementing a server single board provided by the embodiment of the present invention includes:

S501. The main processor initializes the PCIe switch, so that the PCIe switch can work normally.

Specifically, during the initialization process of the PCIe switch, the master processor may distribute routing information to each slave processor connected to the PCIe switch.

S502. The master processor generates a path configuration table, the path configuration table includes a slave processor identifier and routing information corresponding to the slave processor identifier, wherein the routing information corresponding to the slave processor identifier is the same as that specified for the processor identifier The routing information assigned by the indicated slave processor is the same.

S503. The main processor receives the first Ethernet data packet sent by other boards through the network port.

S504. The main processor converts the first Ethernet data packet into a first PCIe data packet.

Specifically, the main processor can encapsulate the first Ethernet data packet as a whole into the payload of the first PCIe data packet or the main processor can extract the payload in the first Ethernet data packet, and the first Ethernet data packet The payload in the network packet is encapsulated into the payload of the first PCIe packet; according to the path configuration table and the slave processor identification of the slave processor, the first routing information corresponding to the slave processor is obtained, and the first Routing information is added to the header of the first PCIe data packet.

S505, the main processor forwards the first PCIe data packet to the PCIe switch through the uplink port of the PCIe switch, so that the PCIe switch forwards the first PCIe data packet according to the first routing information in the header of the first PCIe data packet For slave processors connected to downstream ports.

Specifically, the master processor can query the path configuration table through the table look-up module 25, and obtain routing information of one or more slave processors according to the path configuration table.

For example, the identity information of each slave processor is recorded in the path configuration table, and the identity information can be the bus ID where the processor resides or the MAC (Medium Access Control, medium access control layer) address of the slave processor, The identity information of each slave processor corresponds to a preset routing information. Before the main processor forwards the first PCIe data packet through the PCIe switch, it can search the path configuration table through the routing information recorded in the first PCIe data packet. The path configuration table obtains routing information of one or more slave processors, and forwards the first PCIe data packet to one or more slave processors through the PCIe switch.

Of course, multiple slave processors can also exchange data according to the path configuration table. For example, after the master processor completes the initialization of the PCIe switch and the scan of the slave processors, it generates a path configuration table and sends the path configuration table to each slave processor. When the switch forwards data, the data packet can be sent to the PCIe switch, and the identity information of the second slave processor is added in the forwarded data packet, and the PCIe switch can query the path configuration table, thereby according to the second slave processor The identity information of the second slave processor is used to determine the routing information of the second slave processor so as to complete the data forwarding.

S506. The master processor receives the loading request sent by the slave processor through the PCIe switch.

S507. The main processor reads the image file of the operating system and the application program according to the loading request.

Specifically, after the main processor receives the loading request, the main processor will read the image file of the operating system and the application program from the storage medium. Specifically, the storage medium may include Flash (flash memory), SATA (serial advanced technology attachment, serial advanced technology attachment), SAS (Serial Attached SCSI, serial connection interface) hard disk or SSD (solid state disk, solid state drive). Image files that can be used to store operating systems and applications

S508. The main processor sends the read operating system image file to the slave processor through the PCIe switch, so that the slave processor starts the operating system according to the operating system image file.

In the embodiment of the present invention, the application program running on each slave processor can be dynamically deployed, and the user can configure the working mode of each slave processor through the master processor for different applications. There is a cluster relationship between the slave processors, and each slave processor runs its own operating system and application program. The main processor also runs its own operating system and applications. For example: the first slave processor runs the computing function, and the second slave processor runs the storage function. These two slave processors can cooperate with each other to complete a specific business function. When the slave processor in charge of calculation needs to fetch data from the slave processor in charge of storage, the data exchange can be completed directly through the PCIe switch, that is, the data exchange is completed locally, which can reduce the delay and have no impact on the bandwidth of the external network.

In this way, the image files of the operating system and application programs can be placed in the storage medium of the main processor in advance, and when the slave processor needs to be loaded, it is only necessary to take the image file out of the storage medium of the main processor and send it to Only the slave processors are required, so that each slave processor does not need to provide its own operating system and application program, which saves the memory of the slave processor and improves the processing efficiency of the slave processor.

S509. The master processor sends an online detection message to the slave processor through the PCIe switch, so as to detect whether the slave processor is connected normally.

S510, when it is determined that a slave processor connection fails, the master processor sends the data packet sent to the slave processor to another slave processor through the PCIe switch according to the preset sending strategy; when it is determined that the slave processor recovers When connected, a data packet sent to another slave processor is forwarded to the slave processor through the PCIe switch.

When the connection fails, it means that the slave processor is faulty (or the link between the two master processors is faulty), so the data needs to be forwarded to other slave processors to process the data. The "preset sending strategy" here is not limited specifically. For example, a certain slave processor can be defined in advance to process data when other slave processors (or links) fail. If other slave processors (or links) If there is a failure, the master processor will transfer the data to the dedicated slave processor for processing; or the "preset sending strategy" can also be the preset strategy of "sending according to the load of each slave processor" (like sending packets to slave processors with less load).

For example, there is a heartbeat detection mechanism between the master processor and each slave processor, and the master processor will regularly send creed detection messages to each slave processor to detect whether the slave processors are connected normally. When the heartbeat of the first slave processor is lost, the master processor migrates the business of the first slave processor to the second slave processor or other standby slave processors.

S511. The master processor receives the second PCIe data packet sent by the slave processor through the PCIe switch.

S512. The main processor converts the second PCIe data packet into a second Ethernet data packet.

S513. The main processor forwards the second Ethernet data packet to other boards through the network port.

S514. The master processor receives the third PCIe data packet sent by one of the slave processors through the PCIe switch, and forwards the third PCIe data packet to another slave processor through the PCIe switch.

Such a server single board implementation method can realize the interconnection between all processors without using a multi-level tree structure, thereby avoiding data forwarding between multi-level processors and reducing the delay of the server single board. Improved network service quality.

Those of ordinary skill in the art can understand that all or part of the steps for realizing the above-mentioned method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the It includes the steps of the above method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (20)

1. a server veneer is applied to server system, and described server system also comprises at least one other veneer that is connected with described server veneer, it is characterized in that, described server veneer comprises:

The PCIe interchanger, primary processor and a plurality of from processor, described PCIe interchanger comprises a uplink port and a plurality of downlink port;

Described primary processor links to each other with the uplink port of described PCIe interchanger, described a plurality ofly link to each other with the downlink port of described PCIe interchanger respectively from processor;

Described primary processor is used for receiving the first Ethernet data bag that described other veneers send by network interface, described the first Ethernet data bag is changed into a PCIe packet, described uplink port by described PCIe interchanger is given described PCIe interchanger with a described PCIe package forward, so that described PCIe interchanger is given link to each other with described downlink port described from processor with a described PCIe package forward;

Described primary processor also is used for receiving described the 2nd PCIe packet that sends from processor by described PCIe interchanger, described the 2nd PCIe packet is changed into the second Ethernet data bag, transmit described the second Ethernet data bag by described network interface to described other veneers.

2. server veneer according to claim 1 is characterized in that:

Described primary processor also is used for, and receives one of them described the 3rd PCIe packet that sends from processor by described PCIe interchanger, and gives another described from processor described the 3rd PCIe package forward by described PCIe interchanger.

3. arbitrary described server veneer according to claim 1 and 2 is characterized in that, described primary processor is used for that described the 2nd PCIe packet is changed into the second Ethernet data bag and is specially:

If the payload of described the 2nd PCIe packet comprises complete Ethernet data bag, described primary processor is used for directly extracting described Ethernet data bag to obtain the second Ethernet data bag; Or,

If the payload of described the 2nd PCIe packet comprises the payload of Ethernet data bag, described primary processor encapsulates to obtain the second Ethernet data bag for the payload that extracts described Ethernet data bag.

4. arbitrary described server veneer is characterized in that according to claim 1-3, and described primary processor also is used for, generation pass allocation list, described path configuration table comprise from processor flag and with described from routing iinformation corresponding to processor flag;

Described primary processor is used for described the first Ethernet data bag is changed into a PCIe packet, described uplink port by described PCIe interchanger is given described PCIe interchanger with a described PCIe package forward, so that described PCIe interchanger from processor specifically is to link to each other with described downlink port described a described PCIe package forward:

Described primary processor is used for:

With in the payload of described the first Ethernet data bag overall package to the PCIe packet or described primary processor be used for extracting the payload of described the first Ethernet data bag, the payload in described the first Ethernet data bag is encapsulated in the payload of a PCIe packet; According to described path configuration table and described from the obtaining with described from the first routing iinformation corresponding to processor from processor flag of processor, described the first routing iinformation is added to the head of a described PCIe packet; Uplink port by described PCIe interchanger is given described PCIe interchanger with a described PCIe package forward, so that described PCIe interchanger is given link to each other with described downlink port described from processor according to described the first routing iinformation in the described PCIe packet head with a described PCIe package forward.

5. arbitrary described server veneer is characterized in that according to claim 1-4, and described primary processor also is used for:

Receive described from processor transmission load request by described PCIe interchanger;

According to described load request read operation system and application program image file;

The described operating system image file that reads is sent to by described PCIe interchanger described from server so that describedly start the operating system according to described operating system image file from processor.

6. arbitrary described server veneer is characterized in that according to claim 1-5, and described primary processor also is used for:

Send online detect-message to described from processor by described PCIe interchanger, describedly whether normally connect from processor to detect;

When determining one during from the processor connection failure, will be sent to a described packet from processor according to default sending strategy and be sent to another from processor by described PCIe interchanger.

7. server veneer according to claim 6 is characterized in that, when determining described one when recovering to connect from processor, be sent to described another from the described packet of processor by described PCIe interchanger be forwarded to described one from processor.

8. server veneer implementation method, described server veneer is applied to server system, and described server system also comprises at least one other veneer that is connected with described server veneer, it is characterized in that, comprising:

Primary processor receives the first Ethernet data bag that described other veneers send by network interface;

Described primary processor changes into a PCIe packet with described the first Ethernet data bag;

Described primary processor is given described PCIe interchanger by the described uplink port of described PCIe interchanger with a described PCIe package forward, so that described PCIe interchanger is given link to each other with described downlink port described from processor with a described PCIe package forward;

Described primary processor receives described the 2nd PCIe packet that sends from processor by described PCIe interchanger;

Described primary processor changes into the second Ethernet data bag with described the 2nd PCIe packet;

Described primary processor is transmitted described the second Ethernet data bag by described network interface to described other veneers.

9. method according to claim 8 is characterized in that, described method also comprises:

Described primary processor receives one of them described the 3rd PCIe packet that sends from processor by described PCIe interchanger, and gives another described from processor described the 3rd PCIe package forward by described PCIe interchanger.

10. according to claim 8 or 9 arbitrary described methods, it is characterized in that, described primary processor changes into the second Ethernet data bag with described the 2nd PCIe packet and comprises:

If the payload of described the 2nd PCIe packet comprises complete Ethernet data bag, described primary processor directly extracts described Ethernet data bag to obtain the second Ethernet data bag; Or,

If the payload of described the 2nd PCIe packet comprises the payload of Ethernet data bag, the payload that described primary processor extracts described Ethernet data bag encapsulates to obtain the second Ethernet data bag.

11. arbitrary described method is characterized in that according to claim 8-10, described method also comprises:

Generation pass allocation list, described path configuration table comprise from processor flag and with described from routing iinformation corresponding to processor flag;

Described primary processor changes into a PCIe packet with described the first Ethernet data bag and comprises:

With in the payload of described the first Ethernet data bag overall package to the PCIe packet or described primary processor extract payload in described the first Ethernet data bag, the payload in described the first Ethernet data bag is encapsulated in the payload of a PCIe packet; According to described path configuration table and described from the obtaining with described from the first routing iinformation corresponding to processor from processor flag of processor, described the first routing iinformation is added to the head of a described PCIe packet;

Described primary processor is given described PCIe interchanger by the described uplink port of described PCIe interchanger with a described PCIe package forward, so that described PCIe interchanger comprises to link to each other with described downlink port described a described PCIe package forward from processor:

Uplink port by described PCIe interchanger is given described PCIe interchanger with a described PCIe package forward, so that described PCIe interchanger is given link to each other with described downlink port described from processor according to described the first routing iinformation in the described PCIe packet head with a described PCIe package forward.

12. arbitrary described method is characterized in that according to claim 8-11, described method also comprises:

Described primary processor receives described from processor transmission load request by described PCIe interchanger;

According to described load request read operation system and application program image file;

The described operating system image file that reads is sent to by described PCIe interchanger described from server so that describedly start the operating system according to described operating system image file from processor.

13. arbitrary described method is characterized in that according to claim 8-12, described method also comprises:

Whether described primary processor sends online detect-message to described from processor by described PCIe interchanger, describedly normally connect from processor to detect;

When determining one during from the processor connection failure, described primary processor will be sent to a described packet from processor according to default sending strategy and be sent to another from processor by described PCIe interchanger.

14. method according to claim 13 is characterized in that, when determining described one when recovering to connect from processor, be sent to described another from the described packet of processor by described PCIe interchanger be forwarded to described one from processor.

15. a primary processor is applied to the server veneer, it is characterized in that, described primary processor comprises:

The first receiver module is used for receiving the first Ethernet data bag that other veneers send by network interface;

The first modular converter, described the first Ethernet data bag that is used for described the first receiver module is received changes into a PCIe packet;

The first sending module, be used for the described PCIe package forward that will described the first modular converter be converted to by the PCIe interchanger to link to each other with described PCIe interchanger from processor;

The second receiver module is used for receiving described the 2nd PCIe packet that sends from processor by described PCIe interchanger;

The second modular converter, described the 2nd PCIe packet that is used for described the second receiver module is received changes into the second Ethernet data bag;

The second sending module is used for transmitting described the second Ethernet data bag that described the second modular converter is converted to by described network interface to described other veneers.

16. primary processor according to claim 15 is characterized in that:

Described the first sending module, concrete be used for by the PCIe interchanger uplink port with a described PCIe packet via the PCIe interchanger send to link to each other with the downlink port of described PCIe interchanger from processor;

Described the second receiver module, concrete being used for receives the 2nd that described downlink port from processor from described PCIe interchanger sends, arrive the uplink port of described PCIe interchanger via described PCIe interchanger PCIe packet from the uplink port of described PCIe interchanger.

17. arbitrary described primary processor is characterized in that according to claim 15-16,

Described the second receiver module also is used for receiving one of them described the 3rd PCIe packet that sends from processor by described PCIe interchanger;

Described the first sending module also is used for by described PCIe interchanger described the 3rd PCIe package forward that described the second receiver module receives is described from processor to another.

18. arbitrary described primary processor is characterized in that according to claim 15-17, described primary processor also comprises:

The allocation list generation module is used for the generation pass allocation list, described path configuration table comprise from processor flag and with described from routing iinformation corresponding to processor flag;

Described the first modular converter comprises:

The payload processing module, be used for the payload of described the first Ethernet data bag overall package to the PCIe packet or for the payload that extracts described the first Ethernet data bag the payload in described the first Ethernet data bag being encapsulated in the payload of a PCIe packet;

The head processing module, be used for according to described path configuration table and described obtaining with described from the first routing iinformation corresponding to processor from processor flag from processor, described the first routing iinformation is added to the head of a described PCIe packet, so that after described PCIe interchanger receives the described PCIe packet that rear described the first sending module sends, according to described the first routing iinformation in the described PCIe packet head will a described PCIe package forward to described from processor.

19. arbitrary described primary processor is characterized in that according to claim 15-18, also comprises:

The 3rd receiver module is used for receiving the described load request that sends by described PCIe interchanger from processor, according to described load request read operation system and application program image file;

The 3rd sending module, the described operating system image file that is used for reading is sent to described from processor by described PCIe interchanger, so that describedly start the operating system according to described operating system image file from processor.

20. arbitrary described primary processor is characterized in that according to claim 15-19, described primary processor also comprises:

Whether detection module is used for sending online detect-message to described from processor by described PCIe interchanger, describedly normally connect from processor to detect;

Determine one during from the processor connection failure when described detection module, described the first sending module also is used for:

To be sent to described packet from processor according to default sending strategy and be sent to another from processor by described PCIe interchanger; When determining described one when recovering to connect from processor, be sent to described another from the described packet of processor by described PCIe interchanger be forwarded to described one from processor.

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