CN103016818B - Piezoelectric valve drive amplifier circuit - Google Patents

Abstract

The embodiment of the invention provides a piezoelectric valve drive amplifier circuit, which comprises two first logic circuits and two second logic circuits. By arranging a logic NOT gate in each first logic circuit, after an input signal passes through the two second logic circuits, output signals are the same with the input signal; and after the input signal passes through the two first logic circuits, the output signals are opposite to the input signal, so as to achieve the goal of controlling the output signals through the piezoelectric valve drive amplifier circuit when a single-chip microcomputer is reset in the prior art.

Description

A piezoelectric valve driving amplifier circuit

technical field

The present application relates to the technical field of valve positioners, in particular to a piezoelectric valve drive amplifier circuit.

Background technique

Pneumatic regulating valve is one of the industrial process control instruments widely used in petroleum, chemical, electric power, pharmaceutical, metallurgical and other enterprises. The pneumatic regulating valve is usually formed by connecting the pneumatic actuator and the regulating valve after installation and debugging. By controlling the size of the pneumatic signal entering the pneumatic actuator, the opening of the regulating valve is controlled, thereby controlling the medium flow rate of the production device to reach a predetermined value. Among them, Controlling the size of the pneumatic signal entering the pneumatic actuator is mainly done through the electric valve positioner. Therefore, the electric valve positioner plays a decisive role in the control performance and field function of the entire regulating valve.

Electric valve positioners in the prior art can be classified into electromagnetic electric valve positioners and piezoelectric electric valve positioners. Because the piezoelectric valve positioner uses piezoelectric ceramic materials with extremely high internal resistance, the power consumption is extremely small, and it is more advantageous when forming an intrinsically safe explosion-proof structure, so it is widely favored.

In the prior art, the piezoelectric valve driving amplifying circuit in the piezoelectric electric valve positioner is mainly controlled by a single-chip microcomputer to realize voltage output and thereby control the opening of the valve. However, in special cases (severe interference), it may cause the MCU to reset. When the MCU is reset, although it can be recovered by WATCHDOG, after the MCU is reset, the piezoelectric drive amplifier circuit of the piezoelectric valve positioner will lose the control of the output signal. Control, resulting in uncontrolled valve position, when this happens in some key positions, there may also be potential safety hazards.

Contents of the invention

In view of this, the embodiment of the present application provides a piezoelectric valve driving amplifying circuit to solve the problem in the prior art that the output signal cannot be controlled when the single-chip microcomputer is reset.

In order to achieve the above objectives, the technical solutions provided in the embodiments of the present application are as follows:

A piezoelectric valve driving amplifying circuit, comprising: two first logic circuits and two second logic circuits, wherein,

Both the first logic circuit and the second logic circuit include a first MOS transistor, a second MOS transistor, a first resistor, a second resistor, an inductor, and a Zener diode, wherein:

The drain of the first MOS transistor is connected to the first reference voltage terminal; the source of the first MOS transistor is connected to one end of the inductance, and the other end of the inductance is connected to the signal output end; The gate of the first MOS transistor is connected to the first reference voltage terminal through the first resistor;

The drain of the second MOS transistor is connected to the gate of the first MOS transistor; the source of the second MOS transistor is connected to the ground terminal; the gate of the second MOS transistor is connected to the signal input terminal connected;

The cathode of the Zener diode is connected to the gate of the first MOS transistor, and the anode of the Zener diode is connected to the source of the first MOS transistor;

One end of the second resistor is connected to the gate of the second MOS transistor, and the other end is connected to the ground terminal;

Each of the first logic circuits is provided with a logic NOT gate; in one of the first logic circuits, the logic NOT gate is connected in series with the gate of the second MOS transistor in the first logic circuit and the between the signal input terminals of the first logic circuit, and the output terminal of the logic NOT gate is connected with the gate of the second MOS transistor in the first logic circuit, and the input terminal of the logic NOT gate is connected with the The signal inputs of the first logic circuit are connected.

Preferably, each of the second logic circuits is provided with a diode;

The diode is connected in series between the gate of the second MOS transistor in the second logic circuit and the signal input end of the second logic circuit, and the cathode of the diode is in phase with the gate of the second MOS transistor. connected, the anode of the diode is connected to the signal input terminal of the second logic circuit.

Preferably, the other end of the second resistor in a first logic circuit is connected to the other end of the second resistor in a second logic circuit as a common end, and the circuit also includes a switch circuit, and the switch circuit includes a third MOS tube, the third resistor, the fourth resistor and the fifth resistor, wherein,

The drain of the third MOS transistor is connected to the common terminal;

The drain of the third MOS transistor is connected to the first reference voltage terminal through the third resistor;

The source of the third MOS transistor is connected to the ground terminal;

The gate of the third MOS transistor is connected to the second reference voltage terminal through the fourth resistor;

The gate of the third MOS transistor is connected to the reference signal input terminal through the fifth resistor.

It can be seen from the above technical solutions that the piezoelectric valve driving amplifying circuit provided by the embodiment of the present application includes two first logic circuits and two second logic circuits. By setting a logic NOT gate in each first logic circuit, So that when the input signal respectively passes through the two second logic circuits, the output signal is the same as the input signal. However, when the input signal passes through the two first logic circuits respectively, the output signal is opposite to the input signal, so that the output signal can be controlled when the single-chip microcomputer is reset in the prior art.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments described in this application. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic diagram of a piezoelectric valve drive amplification circuit provided in Embodiment 1 of the present application;

FIG. 2 is a schematic diagram of a piezoelectric valve drive amplification circuit provided in Embodiment 2 of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described The embodiments are only some of the embodiments of the present application, but not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

Embodiment one

FIG. 1 is a schematic diagram of a piezoelectric valve drive amplification circuit provided in Embodiment 1 of the present application.

As shown in Figure 1, the piezoelectric drive amplifier circuit includes: two first logic circuits 1 and two second logic circuits 2, wherein two of the first logic circuits 1 and two of the second logic circuits 2 are provided with a first MOS transistor M1, a second MOS transistor M2, a first resistor R1, a second resistor R2, an inductor L and a Zener diode ZD, and each of the first logic circuits 1 is also provided with a Logic NOT gate X.

The connection relationship of each device in the two second logic circuits will be introduced below.

The drain of the first MOS transistor M1 is connected to the first reference voltage terminal. In the embodiment of the present application, the voltage of the first reference voltage terminal may be 24V. The source of the first MOS transistor M1 is connected to one end of the inductor L, and the other end of the inductor L is connected to the signal output end, which is mainly used for outputting logic circuit signals. The gate of the first MOS transistor M1 is connected to the first reference voltage terminal through the first resistor R1.

The drain of the second MOS transistor M2 is connected to the gate of the first MOS transistor M1, the source of the second MOS transistor M2 is connected to the ground terminal, the gate of the second MOS transistor M2 is connected to the signal input terminal, and the signal The input terminal is mainly used for signal input.

The cathode of the Zener diode ZD is connected to the gate of the first MOS transistor M1, and the anode of the Zener diode ZD is connected to the source of the first MOS transistor M1.

One end of the second resistor R2 is connected to the gate of the second MOS transistor M2, and the other end is connected to the ground.

In addition to the devices in the two second logic circuits described above, the two first logic circuits also include a logic NOT gate X. For the connection relationship of the first MOS transistor M1, the second MOS transistor M2, the first resistor R1, the second resistor R2, the inductor L and the Zener diode ZD in the two first logic circuits, please refer to the above two second logic circuits The connection relationship of each component in , will not be repeated here.

Each first logic circuit is provided with a logic NOT gate X, which is connected in series between the gate of the second MOS transistor M2 and the signal input terminal, and the input terminal of the logic NOT gate X is connected to the signal input terminal. terminal, and the output terminal of the logic NOT gate X is connected to the gate of the second MOS transistor.

In the embodiment of the present application, the arrangement manner of the two first logic circuits and the two second logic circuits may be set arbitrarily. The arrangement of the two first logic circuits and the two second logic circuits shown in FIG. 1 is only a preferred way, and the inventors can set them arbitrarily according to their own needs.

As shown in Figure 1, when the piezoelectric valve driving amplifier circuit provided in the embodiment of the present application is reset, the input signals of the signal input terminals of the piezoelectric valve driving amplifier circuit are IN1=0, IN2=0, IN3= 0 and IN4=0, after the input signal passes through the two first logic circuits and the second logic circuit respectively, the output signals at the signal output terminal are IN1=1, IN2=0, IN3=1 and IN4=0, thus realizing the existing In technology, when the single-chip microcomputer is reset, the output signal can be controlled by the piezoelectric drive amplifier circuit, so that the valve position remains at the current position.

It can be seen from the above technical solutions that the piezoelectric valve driving amplifying circuit provided by the embodiment of the present application includes two first logic circuits and two second logic circuits. By setting a logic NOT gate in each first logic circuit, So that when the input signal respectively passes through the two second logic circuits, the output signal is the same as the input signal. However, when the input signal passes through the two first logic circuits respectively, the output signal is opposite to the input signal, so that the output signal can be controlled when the single-chip microcomputer is reset in the prior art.

Embodiment two

FIG. 2 is a schematic diagram of a piezoelectric valve drive amplification circuit provided in Embodiment 2 of the present application.

As shown in Fig. 2, the piezoelectric valve driving amplifying circuit provided by the present application includes two first logic circuits 1, two second logic circuits 2 and a switch circuit 3, wherein the two first logic circuits 1 and the two second logic circuits The structure of the second logic circuit 2 is the same as that of the two first logic circuits 1 and the two second logic circuits 2 in the first embodiment, and will not be repeated here.

The switch circuit includes a third MOS transistor M3, a third resistor R3, a fourth resistor R4 and a fifth resistor R5.

In the embodiment of the present application, the other end of the second resistor R2 in a first logic circuit is connected with the other end of the second resistor R2 in a second logic circuit as a common end, and the drain of the third MOS transistor M3 pole is connected to the common terminal.

The drain of the third MOS transistor M3 is also connected to the first reference voltage terminal through the third resistor R3; the source of the third MOS transistor M3 is connected to the ground terminal; the gate of the third MOS transistor M3 is connected through the fourth resistor R4 Connect to the second reference voltage terminal. In the embodiment of the present application, the voltage of the second reference voltage terminal may be 3V; the gate of the third MOS transistor is also connected to the reference signal input terminal through the fifth resistor R5.

The power-on states of the two first logic circuits 1 and the two second logic circuits 2 can be controlled by the switch circuit 3. When the voltage input by the reference signal input terminal of the switch circuit 3 is at a high level, the two first logic circuits 1 and 2 The two second logic circuits 2 are in the non-energized state; when the voltage input by the reference signal input terminal of the switch circuit 3 is low level, the two first logic circuits 1 and the two second logic circuits 2 are in the energized state.

As shown in FIG. 2 , the two first logic circuits 1 and the two second logic circuits 2 provided in the embodiment of the present application may further include a diode D.

Wherein, a diode D is connected in series between the gate of the second MOS transistor M2 of each second logic circuit 2 and the signal input terminal of the second logic circuit, and the cathode of the diode D is in phase with the gate of the second MOS transistor. connected, and the anode of the diode D is connected to the signal input terminal.

A diode D can also be arranged between the drains of the first MOS transistor M1 of the two first logic circuits 1 and the two second logic circuits 2 and the first reference voltage, and the cathode of the diode D and the first MOS transistor M1 The drain of the diode D is connected, and the anode of the diode D is connected to the first reference voltage terminal.

It can be seen that the piezoelectric valve driving amplifying circuit provided in the embodiment of the present application further includes a switch circuit, through which the power supply of the two first logic circuits and the two second logic circuits in the piezoelectric valve driving amplifying circuit can be directly controlled. state, so as to control whether the two first logic circuits and the two second logic circuits can work, so that the piezoelectric valve driving amplifying circuit provided by the embodiment of the present application is easier to control.

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.

The above are only preferred embodiments of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the application. Accordingly, the present application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein

Claims (3)

1. A piezoelectric valve driving amplifying circuit, characterized in that it comprises: two first logic circuits and two second logic circuits, wherein, Both the first logic circuit and the second logic circuit include a first MOS transistor, a second MOS transistor, a first resistor, a second resistor, an inductor, and a Zener diode, wherein: The drain of the first MOS transistor is connected to the first reference voltage terminal; the source of the first MOS transistor is connected to one end of the inductance, and the other end of the inductance is connected to the signal output end; The gate of the first MOS transistor is connected to the first reference voltage terminal through the first resistor; The drain of the second MOS transistor is connected to the gate of the first MOS transistor; the source of the second MOS transistor is connected to the ground terminal; the gate of the second MOS transistor is connected to the signal input terminal connected; The cathode of the Zener diode is connected to the gate of the first MOS transistor, and the anode of the Zener diode is connected to the source of the first MOS transistor; One end of the second resistor is connected to the gate of the second MOS transistor, and the other end is connected to the ground terminal; Each of the first logic circuits is provided with a logic NOT gate; in one of the first logic circuits, the logic NOT gate is connected in series with the gate of the second MOS transistor in the first logic circuit and the between the signal input terminals of the first logic circuit, and the output terminal of the logic NOT gate is connected with the gate of the second MOS transistor in the first logic circuit, and the input terminal of the logic NOT gate is connected with the The signal inputs of the first logic circuit are connected. 2. The circuit according to claim 1, wherein a diode is arranged in each of the second logic circuits; The diode is connected in series between the gate of the second MOS transistor in the second logic circuit and the signal input end of the second logic circuit, and the cathode of the diode is in phase with the gate of the second MOS transistor. connected, the anode of the diode is connected to the signal input terminal of the second logic circuit. 3. The circuit according to claim 2, characterized in that, the other end of the second resistor in a first logic circuit is connected with the other end of the second resistor in a second logic circuit as a common terminal, and the circuit also Including a switch circuit, the switch circuit includes a third MOS transistor, a third resistor, a fourth resistor and a fifth resistor, wherein, The drain of the third MOS transistor is connected to the common terminal; The drain of the third MOS transistor is connected to the first reference voltage terminal through the third resistor; The source of the third MOS transistor is connected to the ground terminal; The gate of the third MOS transistor is connected to the second reference voltage terminal through the fourth resistor; The gate of the third MOS transistor is connected to the reference signal input terminal through the fifth resistor.