CN102970008B - Rapid transient response pulse duration modulation circuit - Google Patents

Abstract

A fast transient response pulse width modulation circuit, including a PWM modulator, a slope compensation circuit, a current detection circuit and an error amplifier, the current detection circuit includes an LX voltage transfer circuit and a detection current generator, the output terminal of the LX voltage transfer circuit and the detection The input terminal of the current generator is connected; the PWM modulator includes a voltage-current comparator, an amplifying circuit and a shaping circuit. The terminals are respectively connected to the output signals of the detection current generator, the error amplifier and the slope compensation circuit, the output terminal of the voltage-current comparator is connected to the input terminal of the amplifying circuit, the output terminal of the amplifying circuit is connected to the input terminal of the shaping circuit, and the output terminal of the shaping circuit That is, the output signal of the PWM modulation circuit.

Description

A Fast Transient Response Pulse Width Modulation Circuit

technical field

The invention relates to a power converter, in particular to a fast transient response pulse width modulation circuit inside an integrated circuit, and belongs to the technical field of microelectronics.

Background technique

In system-on-chip design, the power supply scheme uses dynamic voltage adjustment technology to reduce the power consumption of the entire system. This technology requires variable output voltage and can be adjusted quickly. The traditional peak current mode DC-DC converter, because of its fast transient response and simple compensation circuit, has always been superior to the voltage mode control and has become the main control mode of the power chip. The topological structure of the peak current type, the basic topology is shown in Figure 1, and a core part of it is the pulse width modulator, that is, the PWM modulator. PWM modulation mainly receives the signal of slope compensation, current detection signal and signal of error amplifier (EA), performs arithmetic processing and then obtains the pulse width modulation signal required by the system. Generally, complex voltage-to-current, current superposition circuits, and a comparator circuit are required. Due to the need for high-speed voltage switching, complex topologies limit the speed increase.

Contents of the invention

The purpose of the present invention is to solve the problem of slow transient response when output voltage is switched due to long delay time caused by complex PWM modulator and current detection structure of traditional DC-DC power chip. For this reason, the present invention provides a pulse width modulation circuit with fast transient response, which compares the sum of the current I _EA converted from the voltage at the EA output terminal, the current I _SC converted from the slope compensation voltage, and the current I _CS output by the current detection circuit , when there is an intersection between the two, the circuit flips. The current detection circuit adopts a non-traditional nonlinear structure, and the functional expressions of the detection current Ics and the inductor current IL can be obtained. The slope compensation adopts piecewise linear compensation with a compensation slope of 0 when the duty cycle is small, which can effectively improve the load capacity and transient response of the system.

The above object of the present invention is achieved through the following technical solutions: a fast transient response pulse width modulation circuit, based on the peak current DC-DC converter topology, including a PWM modulator, a current detection circuit, a slope compensation circuit and an error amplifier, The PWM modulator receives the slope compensation signal, the current detection signal and the signal of the error amplifier, performs calculation processing and then obtains the pulse width modulation signal required by the system, and is characterized in that the current detection circuit includes a LX voltage transfer circuit and a detection current generator, LX The output terminal of the voltage transmission circuit is connected to the input terminal of the detection current generator; the PWM modulator includes a voltage-current comparator, an amplifier circuit and a shaping circuit, and the slope compensation circuit adopts a segmented slope compensation structure that converts the slope voltage into a current superposition and comparison , the input end of the voltage-current comparator is respectively connected to the output signal of the detection current generator, the error amplifier and the slope compensation circuit, the output end of the voltage-current comparator is connected to the input end of the amplifying circuit, and the output end of the amplifying circuit is connected to the shaping circuit The input terminal, the output terminal of the shaping circuit is the output signal of the PWM modulation circuit, where:

In the current detection circuit, the LX voltage transfer circuit includes a switch tube MP1 and a PMOS tube M1, the source of MP1 is connected to the power supply voltage, the gate of MP1 is connected to the control voltage Vcontrol1, the drain of MP1 is connected to the source of M1, and the gate of M1 is connected to The control signal Vcontrol2, the drain of M1 is the output terminal; the detection current generator includes PMOS transistors M2~M5, NMOS transistors M6~M7 and bias current Ibias1, the gate of M2 is connected to the control signal Vcontrol3, the source of M2 is connected to the power supply voltage, The drain of M2 is connected to the source of M3 and the drain of M1 in the LX voltage transfer circuit, the drain of M3 is connected to the bias current Ibias1 and the gates of M3 and M5, the other end of the bias current Ibias1 is grounded, and the source of M5 The pole is connected to the drain of M4, the source of M4 is connected to the power supply voltage, the gate of M4 is grounded, the drain of M5 is connected to the drain of the NMOS transistor M6, and the source of M6 is grounded. The gate of M6 and the drain of M6 are interconnected and connected to the gate of M7, the source of M7 is grounded, and the drain of M7 outputs current Ics;

The slope compensation circuit includes PMOS transistor M8, NMOS transistor M9, capacitor C1, and bias current Ibias2. The source of M8 is connected to the power supply voltage, the gate of M8 is connected to the gate of M9 and connected to the control voltage Vcontrol4, and the drain of M8 is passed through the bias current. The current Ibias2 is connected to the drain of M9 and one end of the capacitor C1 as the output voltage signal Vsc of the slope compensation circuit, and the source of M9 and the other end of the capacitor C1 are grounded;

In the PWM modulator, the voltage-current comparator includes NMOS transistors M10-M12, PMOS transistors M13-M14, and resistors R3 and R4. The gate of M10 is used as an input terminal of the PWM modulator, and is connected to the output Vea of the error amplifier. The source of M10 is connected to one end of resistor R3, the other end of R3 is grounded, the drain of M10 is connected to the drain of M13, the source of M13 is connected to the power supply voltage, the gate of M13 is connected to the drain and connected to the gate of M14 , the source of M14 is connected to the power supply voltage, the drain of M14 is connected to the drain of M12, the gate of M12 is connected to the bias voltage Vbias1, the source of M12 is connected to the drain of M11, as another input terminal of the PWM modulator and In the current detection circuit, the output current Ics of the detection current generator is connected, the gate of M11 is connected to the output voltage signal Vsc of the slope compensation circuit as the third input terminal of the PWM modulator, the source of M11 is connected to one end of the resistor R4, and the The other end is grounded; the amplifier circuit includes PMOS transistor M15 and NMOS transistor M16, the gate of M15 is connected to the source of M12 and the drain of M11 in the voltage-current comparator, the source of M15 is connected to the power supply voltage, and the drain of M15 is connected to M16 The drain, and as the output of the amplifying circuit, the gate of M16 is connected to the bias voltage Vbisa2, the source of M16 is grounded; the shaping circuit includes an inverter INV1, the input of INV1 is connected to the output of the amplifying circuit, and the output of INV1 The terminal is the pulse width modulation signal output terminal.

Advantage of the present invention and remarkable effect:

(1) The PWM modulator of the present invention adopts a voltage-current superposition comparator structure, and compares the current converted from the voltage at the EA output terminal with the current converted from the slope compensation voltage and the sum of the current output from the current detection circuit; and after the mirror current source A N tube is used for clamping. This structure greatly simplifies the traditional complex PWM circuit structure, saves the delay time of the loop, and improves the voltage following ability and response speed of the system.

(2) The present invention utilizes the equation relationship that the gate voltages of the two common-gate P tubes are equal to obtain a simple nonlinear current detection structure. Like the PWM structure, this simple circuit structure improves the dynamic voltage adjustment capability of the system.

(3) The slope compensation circuit converts the slope voltage into a current superposition and comparison method to realize segmental slope compensation that does not compensate under a small duty cycle. This structure can avoid overcompensation when the duty ratio is less than 0.5, improves the load capacity of the system, expands the system bandwidth, and is conducive to improving the voltage following performance of the system.

Description of drawings

Fig. 1 is a topological block diagram of an existing peak current type DC-DC circuit;

Fig. 2 is a block diagram of the present invention;

Fig. 3 is a circuit diagram of a specific realization of the present invention.

Detailed ways

As shown in Figure 2, the present invention includes a PWM modulator, a current detection circuit, a slope compensation circuit, and an error amplifier. The PWM modulator receives the slope compensation signal Vsc, the current detection signal Ics, and the signal Vea of the error amplifier, performs arithmetic processing and then obtains the required value of the system. pulse width modulated signal. The current detection circuit includes an LX voltage transfer circuit 1 and a detection current Ics=f(I _L ) generator 2 . LX is the connection node voltage of MP1 tube and MN1 tube in Fig. 1, the output V1 of LX voltage transfer circuit 1 is connected with the input terminal of detection current generator 2; PWM modulator includes voltage-current comparator 4, amplifying circuit 5 and shaping Circuit 6, the slope compensation circuit adopts the segmented slope compensation 3 which converts the slope voltage into a current superposition and comparison, and its input signal is the control voltage Vcontrol4. The input terminal of the voltage-current comparator 4 is respectively connected to the output current Ics of the detection current generator, the output signal Vsc of the error amplifier output Vea and the slope compensation circuit, and the output V2 of the voltage-current comparator 4 is connected to the input terminal of the amplifying circuit 5 to amplify The output V3 of the circuit 5 is connected to the input terminal of the shaping circuit 6, and the output of the shaping circuit 6 is the pulse width modulation signal output by the PWM modulation circuit.

As shown in Figure 3, in the current detection circuit, the LX voltage transmission circuit 1 includes the main switch tube MP1 and the PMOS tube M1, the source of MP1 is connected to the power supply voltage, the gate of MP1 is connected to the control voltage Vcontrol1, and the drain of MP1 is the voltage of LX point, which is connected to The source of M1, the gate of M1 are connected to the control signal Vcontrol2, and the drain of M1 is the output terminal V1. The LX voltage transmission circuit 1 is used to copy and transmit the voltage on the LX node to the Ics=f(IL) generator 2 during the rising phase of the inductor current. As shown in Figure 3, the voltage on the LX point can be approximately copied by using a MOS transistor M1 working in the deep linear region.

The detection current generator 2 includes PMOS transistors M2-M5, NMOS transistors M6-M7 and bias current Ibias1, the gate of M2 is connected to the control signal Vcontrol3, the source of M2 is connected to the power supply voltage, and the drain of M2 is connected to the source of M3 as The input end is connected to the drain output V1 of M1 in the LX voltage transfer circuit 1, the drain of M3 is connected to the bias current Ibias1 and the gates of M3 and M5, the other end of the bias current Ibias1 is grounded, the source of M5 is connected to the gate of M4 The drains are connected, the source of M4 is connected to the power supply voltage, the gate of M4 is grounded, the drain of M5 is connected to the drain of the NMOS transistor M6, and the source of M6 is grounded. The gate of M6 is interconnected with the drain of M6 and connected with the gate of M7, the source of M7 is grounded, and the drain of M7 outputs the current Ics. Ics=f(IL) Generator 2 can use a mirror structure to linearly replicate the current of IL, but because the linear structure needs to accurately replicate the current, the required circuit structure will be very complicated, and the delay time of the device will be very long. As shown in FIG. 3 , the present invention adopts a simple nonlinear structure, using the relationship that the gate voltages of MOS transistors M5 and M7 are equal, the current expressions of Ics and I _L can be obtained.

The slope compensation circuit 3 includes a PMOS transistor M8, an NMOS transistor M9, a capacitor C1, and a bias current Ibias2. The source of M8 is connected to the power supply voltage, the gate of M8 is connected to the gate of M9 and connected to the control voltage Vcontrol4, and the drain of M8 passes through The bias current Ibias2 is connected to the drain of M9 and one end of the capacitor C1 as the output voltage signal Vsc of the slope compensation circuit, and the source of M9 and the other end of the capacitor C1 are grounded. The input signal Vcontrol4 of the slope compensation circuit 3 is a feedback control signal generated after the output signal of the PWM comparator passes through the digital circuit. Vcontrol4 is a square wave signal, which is related to the duty cycle of the system, and can realize segmented linear compensation by controlling the charging and discharging time of the slope compensation capacitor. The compensation slope is 0 when the duty cycle is less than 0.5, and it is a fixed slope compensation slope when the duty cycle is greater than 0.5.

In the PWM modulator, the voltage-current comparator 4 includes NMOS transistors M10-M12, PMOS transistors M13-M14, and resistors R3 and R4. The gate of M10 is used as an input terminal of the PWM modulator, and is connected to the output Vea of the error amplifier, , the source of M10 is connected to one end of resistor R3, the other end of R3 is grounded, the drain of M10 is connected to the drain of M13, the source of M13 is connected to the power supply voltage, the gate of M13 is connected to the drain and connected to the gate of M14 The source of M14 is connected to the power supply voltage, the drain of M14 is connected to the drain of M12, the gate of M12 is connected to the bias voltage Vbias1, and the source of M12 is connected to the drain of M11, which is used as the other input terminal of the PWM modulator It is connected to the output current Ics of the detection current generator in the current detection circuit, the gate of M11 is used as the third input terminal of the PWM modulator and connected to the output voltage signal Vsc of the slope compensation circuit, the source of M11 is connected to one end of the resistor R4, R4 The other end of the ground. The voltage-current comparator 4 is to convert the voltage Vea at the output terminal of EA and the voltage Vsc at the output terminal of the slope compensation circuit 3 into current signals, superimpose the currents of I _SC and I _CS , and then combine the sum of I _EA with I _SC and I _CS Compare. The voltage-current comparator 4 can adopt a comparator structure, utilize the current characteristic of the comparator tube, convert the input voltage into a current, directly compare the current, and send the comparison result to the next-stage amplifying circuit 5 .

Amplifying circuit 5 includes PMOS transistor M15 and NMOS transistor M16, the gate of M15 is connected to the source of M12 in the voltage-current comparator 4 and the drain of M11 outputs V2, the source of M15 is connected to the power supply voltage, and the drain of M15 is connected to M16 The drain, and as the output terminal V3 of the amplifying circuit, the gate of M16 is connected to the bias voltage Vbisa2, and the source of M16 is grounded. The amplifying circuit 5 can adopt various structures, not only a cascode structure, but also a common source structure. Under the condition that the gain is satisfied, in order to obtain the most compact circuit structure, Figure 3 adopts the simplest common-source amplifier structure, and the V2 signal is input into the amplifier circuit 5 to obtain the signal V3, which is amplified and sent to the next stage shaping circuit 6.

The shaping circuit 6 includes an inverter INV1, the input terminal of INV1 is connected to the output terminal V3 of the amplifying circuit, and the output terminal of INV1 is the pulse width modulation signal of the present invention. The function of the shaping circuit 6 is to shape the output signal V3 of the amplifying circuit 5 . The output signal of the amplifying circuit V3 is an analog signal. In order to obtain the digital signal PWM_OUT at the PWM output terminal, the analog signal needs to be shaped.

The working principle of the circuit of the present invention is as follows: when the inductance current is in the rising stage, the control signal Vcontrol2 makes the M1 tube work, and the control signals Vcontrol1 and Vcontrol3 make the MP1 and M2 tubes cut off. The LX voltage is transmitted through the M1 tube working in the deep linear region, that is, V ₁ ≈V _LX . The M4 tube works in the deep linear region, which is equivalent to a resistor. The bias current Ibias1 provides bias to M3, the gate voltages of M5 and M3 are equal, and M6 and M7 are current mirror replication circuits. By adjusting the width-to-length ratio of M6 and M7, the proportional coefficient of the current mirror replication can be obtained. Now assume (W/L) ₇ (W/L) ₆ =1. Using the same gate voltage of M7 and M5, V _G3 =V _G5 , Ics=f(I _L ) can be obtained as follows:

$\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}}{{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; OX</span>}}{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; TH</span>}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; ]</span>}<span\; class="notranslate">\; =</span>\sqrt{\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; CS</span>}}}{{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; OX</span>}}{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; TH</span>}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; CS</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; OX</span>}}{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; TH</span>}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; ]</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; SG</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}$

Among them, I _L is the inductor current, μ _p is the mobility of the PMOS transistor, C _OX is the capacitance of the gate oxide layer per unit area of the PMOS transistor, (W/L) _MP1 and V _{|TH|_MP1} are the PMOS transistor shown in Figure 1 Aspect ratio and threshold voltage, (W/L) _M4 , (W/L) _M5 and V _{|TH|_M4} , V _{|TH|_M5} are the width-to-length ratio and threshold voltage of the M4 and M5 tubes in Figure 3, respectively, Ics is the drain output current Ics of M7 in Figure 3, and V _DD is the power supply voltage. Since the bias current _Ibias1 is a constant, the gate-source voltage of M3 is a constant in VGS3. As shown in the above formula, because the principle of current mirror replication is not used, the current Ics obtained by this current detection circuit has a nonlinear relationship with the inductor current _IL . The structure of this circuit is simple, the delay is small and the power consumption is low.

The control signal Vcontrol4 of the slope compensation circuit is a feedback control signal related to the duty ratio generated after the output signal of the PWM modulator passes through the digital circuit, which can realize segmental slope compensation. When Vcontrol4 is low, M8 is turned on, M9 is turned off, the bias current Ibias2 charges capacitor C1, and the Vsc ramp voltage signal is output; when Vcontrol4 is high, M8 is turned off, M9 is turned on, and capacitor C1 is discharged through M9. When the duty cycle is small, less than 0.5, the capacitor charging time becomes shorter, the output Vsc voltage is too small to turn on the M11 tube, and the slope compensation voltage cannot be converted into a current for comparison in the PWM modulator. This means that when the duty cycle is small, the slope compensation slope is 0, and when the duty cycle is large, it is a fixed slope compensation slope, which realizes the function of piecewise linear compensation.

The PWM modulator is a comparator structure, the first stage is a current comparator, and the second stage is a first-stage amplifier plus a shaping circuit. When the PWM modulator is working, the output voltage Vea of the error amplifier is converted into the current I _ea through the M10 tube, and V _sc is converted into the current I _sc through the M11 tube. M13 and M14 are a current mirror with a proportional coefficient of 1, which replicates the current I _ea . The mirror current I _ea1 is obtained. The derived current is:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; ea</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ea</span>}}<span\; class="notranslate">\; \&times;</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 10</span>}}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 10</span>}}<span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}$

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; SC</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; SC</span>}}<span\; class="notranslate">\; \&times;</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 11</span>}}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}$

Among them, g _m10 and g _m11 are the transconductances of M10 tube and M11 tube in Fig. 3 respectively, and R3 and R4 are the resistance values of the resistors shown in Fig. 3 . At V2, I _ea is compared with the sum of I _SC and I _CS , and when there is an intersection point between the two, the voltage at V2 is reversed, and the signal PWM_OUT is output through the amplification and shaping circuit.

In order to ensure that the M14 tube can more accurately copy the current of the M13 tube, the M14 tube needs to work in the saturation region, so the M12 tube is introduced. The M12 tube has the function of switching and clamping. First, set Vbias1 to an appropriate value, and then adjust the M12 tube to make it in the linear region during normal operation, so that the Vds of M14 has a certain value, making it work in the saturation region, and the point of V2 The voltage will not be too high, so that M15 works in the saturation region to amplify.

The present invention is different from the traditional PWM modulator structure adopting a voltage-current-voltage+comparator structure. This voltage-current comparator has a simple structure, and cooperates with the slope compensation circuit to realize a low duty cycle slope compensation with a slope of 0. The segmented slope compensation not only reduces the delay time of the system, but also improves the system bandwidth and greatly improves the rapid dynamic voltage adjustment capability of the system.

Claims (1)

1. A fast transient response pulse width modulation circuit, based on the peak current type DC-DC converter topology, including a PWM modulator, a current detection circuit, a slope compensation circuit and an error amplifier, and the PWM modulator receives the signal of the slope compensation, The current detection signal and the signal of the error amplifier are processed to obtain the pulse width modulation signal required by the system. It is characterized in that the current detection circuit includes a voltage transfer circuit and a detection current generator, and the output terminal of the voltage transfer circuit and the detection current generator The input terminal of the PWM modulator includes a voltage-current comparator, an amplifier circuit and a shaping circuit. The slope compensation circuit adopts a segmented slope compensation structure that converts the slope voltage into a current superimposed comparison. The input terminals of the voltage-current comparator are respectively connected to Detect the output signals of the current generator, error amplifier and slope compensation circuit, the output terminal of the voltage-current comparator is connected to the input terminal of the amplifying circuit, the output terminal of the amplifying circuit is connected to the input terminal of the shaping circuit, and the output terminal of the shaping circuit is the PWM The modulation circuit outputs a signal where: In the current detection circuit, the voltage transmission circuit includes a switch tube MP1 and a PMOS tube M1. The source of MP1 is connected to the power supply voltage, the gate of MP1 is connected to the control voltage Vcontrol1, the drain of MP1 is connected to the source of M1, and the gate of M1 is connected to the control voltage. Signal Vcontrol2, the drain of M1 is the output terminal; the detection current generator includes PMOS transistors M2~M5, NMOS transistors M6~M7 and bias current Ibias1, the gate of M2 is connected to the control signal Vcontrol3, the source of M2 is connected to the power supply voltage, M2 The drain of M3 is connected to the source of M3 and the drain of M1 in the voltage transfer circuit, the drain of M3 is connected to the bias current Ibias1 and the gates of M3 and M5, the other end of the bias current Ibias1 is grounded, the source of M5 is connected to the gate of M5 The drain of M4 is connected, the source of M4 is connected to the power supply voltage, the gate of M4 is connected to the ground, the drain of M5 is connected to the drain of the NMOS transistor M6, the source of M6 is connected to the ground, the gate of M6 and the drain of M6 are interconnected and Connected to the gate of M7, the source of M7 is grounded, and the drain of M7 outputs the current Ics; The slope compensation circuit includes a PMOS transistor M8, an NMOS transistor M9, a capacitor C1, and a bias current Ibias2. The source of M8 is connected to the power supply voltage, the gate of M8 is connected to the gate of M9 and connected to the control voltage Vcontrol4, and the drain of M8 passes through the bias current. The current Ibias2 is connected to the drain of M9 and one end of the capacitor C1 as the output voltage signal Vsc of the slope compensation circuit, and the source of M9 and the other end of the capacitor C1 are grounded; In the PWM modulator, the voltage-current comparator includes NMOS transistors M10-M12, PMOS transistors M13-M14, and resistors R3 and R4. The gate of M10 is used as an input terminal of the PWM modulator, and is connected to the output Vea of the error amplifier. The source of M10 is connected to one end of resistor R3, the other end of R3 is grounded, the drain of M10 is connected to the drain of M13, the source of M13 is connected to the power supply voltage, the gate of M13 is connected to the drain and connected to the gate of M14 , the source of M14 is connected to the power supply voltage, the drain of M14 is connected to the drain of M12, the gate of M12 is connected to the bias voltage Vbias1, the source of M12 is connected to the drain of M11, as another input terminal of the PWM modulator and In the current detection circuit, the output current Ics of the detection current generator is connected, the gate of M11 is connected to the output voltage signal Vsc of the slope compensation circuit as the third input terminal of the PWM modulator, the source of M11 is connected to one end of the resistor R4, and the The other end is grounded; the amplifier circuit includes PMOS transistor M15 and NMOS transistor M16, the gate of M15 is connected to the source of M12 and the drain of M11 in the voltage-current comparator, the source of M15 is connected to the power supply voltage, and the drain of M15 is connected to M16 The drain, and as the output of the amplifying circuit, the gate of M16 is connected to the bias voltage Vbisa2, the source of M16 is grounded; the shaping circuit includes an inverter INV1, the input of INV1 is connected to the output of the amplifying circuit, and the output of INV1 The terminal is the pulse width modulation signal output terminal.