CN102932009B - Based on QC-LDPC parallel encoding method in the DTMB of look-up table - Google Patents

Abstract

The present invention relates to a kind of scheme solving 3 kinds of different code check QC-LDPC code parallel encodings in DTMB system, it is characterized in that, the parallel encoder of the QC-LDPC code of described system primarily of register, look-up table, bc position two inputs XOR gate and b position two inputs XOR gate four part composition.The compatible multi code Rate of Chinese character of QC-LDPC parallel encoder provided by the invention, the look-up table function in fpga logic resource can be made full use of, keeping effectively reducing resource requirement under the constant condition of coding rate, have control simple, resource consumption is few, power consumption is little, low cost and other advantages.

Description

Based on QC-LDPC parallel encoding method in the DTMB of look-up table

Technical field

The present invention relates to Digital Terrestrial Television Broadcast field, particularly a kind of Parallel Implementation method of QC-LDPC code coder in DTMB system.

Background technology

Because the various distortion that exists in transmission channel and noise can produce interference to transmission signal, receiving terminal inevitably digital signal produces the situation of error code.In order to reduce the error rate, need to adopt channel coding technology.

Low-density checksum (Low-DensityParity-Check, LDPC) code becomes the study hotspot of field of channel coding with the excellent properties that it approaches Shannon limit.Quasi-cyclic LDPC code (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code, and its coding can adopt shift register to add accumulator (Shift-Register-Adder-Accumulator, SRAA) and be realized.

SRAA method utilizes generator matrix G to encode.The generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array that (1≤i≤a, 1≤j≤t) is formed, t=a+c.The a part of generator matrix corresponding with information vector is unit matrix, and the remainder generator matrix corresponding with verification vector is high-density matrix.The a road SRAA method that walks abreast completes first encoding and needs b+t clock cycle, needs (ac+t) b register, acb two inputs to input XOR gate with door and acb individual two.

DTMB standard have employed the QC-LDPC code of 3 kinds of different code checks.For these 3 kinds of QC-LDPC codes, all have t=59 and b=127, one of common divisor of 3 kinds of a is u=6.Fig. 1 gives parameter a under different code check η and c.

In DTMB system, the existing solution of QC-LDPC high spped coding adopts a road to walk abreast SRAA method, and the parallel encoder realizing 3 kinds of QC-LDPC codes needs 301371 registers altogether, 278892 two inputs input XOR gate with door and 278892 two.When adopting FPGA to realize, need more logical resource, equipment cost will certainly be caused high, and power consumption is large.

Summary of the invention

The large shortcoming of resources requirement existed in existing implementation for DTMB system multi code Rate of Chinese character QC-LDPC code high spped coding, the invention provides a kind of parallel encoding method based on look-up table, make full use of the look-up table function in fpga logic resource, can keep, under the prerequisite that coding rate is constant, effectively reducing resource requirement.

As shown in Figure 2, in DTMB system, the parallel encoder of multi code Rate of Chinese character QC-LDPC code forms primarily of 4 parts: register, look-up table, bc position two input XOR gate and b position two inputs XOR gate.Whole cataloged procedure divides 4 steps to complete: the 1st step, and input information vector s, is saved to register R _c+1~ R _t, reset register R ₁~ R _c; 2nd step, register R _c+1~ R _tserial moves to left 1 time, look-up table L ₁~ L _xinput vector h respectively ₁~ h _xwith output vector v ₁~ v _x, bc position two inputs XOR gate B ₁~ B _x-1to vector v ₁~ v _xsummation, obtains vector v _x+1, b position two inputs XOR gate A _l(1≤l≤c) is by vector v _x+1l section b bit and register R _lserial loop moves to left the results added of 1 time, and deposits back register R _l; 3rd step, repeats the 2nd step b time; 4th step, parallel output code word (p, s).

The compatible multi code Rate of Chinese character of QC-LDPC parallel encoder provided by the invention, can keep effectively reducing resource requirement under the constant prerequisite of coding rate, thus reach the object reducing hardware cost and power consumption.

Be further understood by ensuing detailed description and accompanying drawings about the advantages and spirit of the present invention.

Accompanying drawing explanation

Fig. 1 gives parameter a, c and x under different code check η;

Fig. 2 is the parallel encoder overall structure of compatible 3 kinds of code check QC-LDPC codes in DTMB standard;

Fig. 3 compares traditional a road and to walk abreast SRAA method and resource consumption of the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as a limitation of the invention.

QC-LDPC code is the special LDPC code of a class, and its generator matrix G and check matrix H are all the arrays be made up of circular matrix, have stages cycle feature, therefore are called as quasi-cyclic LDPC code.From the angle of row, each provisional capital of circular matrix is the result of lastrow (first trip is footline) ring shift right one; From the angle of row, each row of circular matrix are all the results that previous column (first is terminal column) circulation moves down.The set that the row vector of circular matrix is formed is identical with the set that column vector is formed, and therefore, circular matrix can be characterized by its first trip or first completely.The generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _{i, j}the array that (1≤i≤a, 1≤j≤t) is formed:

G(or H) continuous b capable and b row be called as the capable and block row of block respectively.Suppose g _i,j(1≤i≤a, 1≤j≤c) is circular matrix G _{i, j}first trip, so can define a × bc rank block first trip matrix F in the following manner:

F is made up of the first trip of all circular matrixes during c block before generator matrix G arranges, and can be considered to be made up of bc a dimensional vector.Suppose that a is not prime number, can be broken down into a=ux, wherein, u and x is all the positive integer of non-1.So, u (m-1)+1 ~ um(1≤m≤x of block first trip matrix F) row constitutes u × bc rank matrix, and be referred to as sub-block first trip matrix, be denoted as F _m.F _mcan be considered and to be made up of bc u dimensional vector.

For DTMB standard, the corresponding code word (p, s) of generator matrix G, that the front c block row of G are corresponding is the vectorial p of verification, and that rear a block row are corresponding is information vector s.Be one section with b bit, verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c); Information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a).For i-th (1≤i≤a) segment information vector s _i, have s _i=(s _{i, 1}, s _{i, 2}..., s _i,b).DTMB standard have employed the QC-LDPC code of 3 kinds of different code checks, all has t=59 and b=127, and one of common divisor of 3 kinds of a is u=6.Fig. 1 gives parameter a, c and x under different code check η.

By the feature of formula (1), (2) and circular matrix, Fig. 2 gives the parallel encoder being applicable to 3 kinds of code check QC-LDPC codes in DTMB standard, it primarily of register, look-up table, bc position two input XOR gate and b position two inputs XOR gate four kinds of functional modules compositions.

Register R ₁~ R _cfor calculating and store the vectorial p=(p of verification ₁, p ₂..., p _c), register R _c+1~ R _tfor cache information vector s=(s ₁, s ₂..., s _a).

Look-up table L ₁~ L _xall there is u position to input and the output of bc position, complete different u position information bits and sub-block first trip matrix F respectively ₁~ F _xproduct.The u position information bit s of parallel input _{mu-u+1, k}, s _{mu-u+2, k}..., s _{mu, k}(1≤m≤x, 1≤k≤b) forms vectorial h _m={ s _{mu-u+1, k}, s _{mu-u+2, k}..., s _{mu, k}.Look-up table L _minput be h _m, it is h that each road exports _mwith sub-block first trip matrix F _mthe product of respective column, total output constitutes vector v _m.If the unit of substantially searching of look-up table is considered as one two input and door, need xcb two input and doors so altogether.

Bc position two inputs XOR gate B ₁~ B _x-1by vector v ₁~ v _xbe added together, obtain vector v _x+1.In fact, v _x+1in each element be vector { h ₁, h ₂..., h _xwith the product of block first trip matrix F respective column, v _x+1vector { h ₁, h ₂..., h _xwith the product of block first trip matrix F.

B position two inputs XOR gate A _l(1≤l≤c) is by vector v _x+1continuous b bit be added to register R _lin.

It is xcb that all bc positions two input the two input XOR gate sums that XOR gate and b position two input XOR gate.

The invention provides a kind of QC-LDPC parallel encoding method based on look-up table, in conjunction with the parallel encoder (as shown in Figure 2) of multi code Rate of Chinese character QC-LDPC code in DTMB system, its coding step is described below:

1st step, input information vector s, is saved to register R _c+1~ R _t, reset register R ₁~ R _c;

2nd step, register R _c+1~ R _tserial moves to left 1 time, look-up table L ₁~ L _xinput vector h respectively ₁~ h _xwith output vector v ₁~ v _x, bc position two inputs XOR gate B ₁~ B _x-1to vector v ₁~ v _xsummation, obtains vector v _x+1, b position two inputs XOR gate A _l(1≤l≤c) is by vector v _x+1l section b bit and register R _lserial loop moves to left the results added of 1 time, and deposits back register R _l;

3rd step, repeats the 2nd step b time, after completing, and register R ₁~ R _cthat store is the vectorial p=(p of verification ₁, p ₂..., p _c), register R _c+1~ R _tthat store is information vector s=(s ₁, s ₂..., s _a);

4th step, parallel output code word (p, s).

Be not difficult to find out from above step, whole cataloged procedure needs b+t clock cycle altogether, and this and the traditional a road SRAA method that walks abreast is identical.

Fig. 3 compares traditional a road and to walk abreast SRAA method and resource consumption of the present invention.Note, the unit of substantially searching of look-up table is considered as one two input and door here.Can know from Fig. 3 and see, walk abreast compared with SRAA method with a road, present invention uses less register, XOR gate and with door, consumption is that a road walks abreast 7%, 17% and 17% of SRAA method respectively.

As fully visible, walk abreast compared with SRAA method with traditional a road, the present invention maintains coding rate, can make full use of the look-up table function in fpga logic resource, have control simple, resource consumption is few, power consumption is little, low cost and other advantages.

Above-described embodiment, just the present invention's more preferably embodiment, the usual change that those skilled in the art carries out within the scope of technical solution of the present invention and replacement all should be included in protection scope of the present invention.

Claims (4)

1. one kind is suitable for the parallel encoder of 3 kinds of different code check QC-LDPC codes that DTMB system adopts, DTMB is the English abbreviation of digital television terrestrial broadcasting system, English full name is the generator matrix G of DigitalTelevisionTerrestrialMultimediaBroadcasting, QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array formed, wherein, a, t and b is all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, 3 kinds of different code check η are 0.4 respectively, 0.6, 0.8, for these 3 kinds different code check QC-LDPC codes, all there is t=59 and b=127, the parameter a that 3 kinds of different code checks are corresponding is 24 respectively, 36, 48, the parameter c that 3 kinds of different code checks are corresponding is 35 respectively, 23, 11, one of common divisor of 3 kinds of a is u=6, a=ux, the parameter x that 3 kinds of different code checks are corresponding is 4 respectively, 6, 8, corresponding code word (the p of generator matrix G, s), that the front c block row of G are corresponding is the vectorial p of verification, that rear a block row are corresponding is information vector s, it is one section with b bit, verify vectorial p and be divided into c section, i.e. p=(p ₁, p ₂..., p _c), information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), the i-th segment information vector s _i=(s _{i, 1}, s _{i, 2}..., s _i,b), it is characterized in that, described encoder comprises following parts:

Register R ₁~ R _t, register R ₁~ R _cfor calculating and store the vectorial p=(p of verification ₁, p ₂..., p _c), register R _c+1~ R _tfor cache information vector s=(s ₁, s ₂..., s _a);

Look-up table L ₁~ L _x, the vectorial h of parallel input u position information bit formation respectively _m={ s _{mu-u+1, k}, s _{mu-u+2, k}..., s _{mu, k}, parallel output bc bit vector v _m, wherein, 1≤m≤x, 1≤k≤b;

Bc position two inputs XOR gate B ₁~ B _x-1, by vector v ₁~ v _xbe added together, obtain vector v _x+1;

B position two inputs XOR gate A ₁~ A _c, A _lby vector v _x+1the continuous b bit of l section be added to register R _lin, wherein, 1≤l≤c.

2. parallel encoder as claimed in claim 1, is characterized in that, described look-up table L ₁~ L _xcomplete different u position information bits and sub-block first trip matrix F respectively ₁~ F _xproduct, look-up table L _minput be h _m, it is h that each road exports _mwith sub-block first trip matrix F _mthe product of respective column, total output constitutes vector v _m.

3. parallel encoder as claimed in claim 1, is characterized in that, described vector v _x+1in each element be vector { h ₁, h ₂..., h _xwith the product of block first trip matrix F respective column, v _x+1vector { h ₁, h ₂..., h _xwith the product of block first trip matrix F.

4. one kind is suitable for the parallel encoding method of 3 kinds of different code check QC-LDPC codes that DTMB system adopts, DTMB is the English abbreviation of digital television terrestrial broadcasting system, English full name is the generator matrix G of DigitalTelevisionTerrestrialMultimediaBroadcasting, QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array formed, wherein, a, t and b is all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, 3 kinds of different code check η are 0.4 respectively, 0.6, 0.8, for these 3 kinds different code check QC-LDPC codes, all there is t=59 and b=127, the parameter a that 3 kinds of different code checks are corresponding is 24 respectively, 36, 48, the parameter c that 3 kinds of different code checks are corresponding is 35 respectively, 23, 11, one of common divisor of 3 kinds of a is u=6, a=ux, the parameter x that 3 kinds of different code checks are corresponding is 4 respectively, 6, 8, corresponding code word (the p of generator matrix G, s), that the front c block row of G are corresponding is the vectorial p of verification, that rear a block row are corresponding is information vector s, it is one section with b bit, verify vectorial p and be divided into c section, i.e. p=(p ₁, p ₂..., p _c), information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), the i-th segment information vector s _i=(s _{i, 1}, s _{i, 2}..., s _i,b), it is characterized in that, described coding method comprises the following steps:

1st step, input information vector s, is saved to register R _c+1~ R _t, reset register R ₁~ R _c;

2nd step, register R _c+1~ R _tserial moves to left 1 time, look-up table L ₁~ L _xinput vector h respectively ₁~ h _xwith output vector v ₁~ v _x, bc position two inputs XOR gate B ₁~ B _x-1to vector v ₁~ v _xsummation, obtains vector v _x+1, b position two inputs XOR gate A _lby vector v _x+1l section b bit and register R _lserial loop moves to left the results added of 1 time, and deposits back register R _l, wherein, 1≤l≤c;

3rd step, repeats the 2nd step b time, after completing, and register R ₁~ R _cthat store is the vectorial p=(p of verification ₁, p ₂..., p _c), register R _c+1~ R _tthat store is information vector s=(s ₁, s ₂..., s _a);

4th step, parallel output code word (p, s).