CN102929816A

CN102929816A - Radio frequency communication transceiver device utilizing memory controller to load programs and relative method

Info

Publication number: CN102929816A
Application number: CN2012104337388A
Authority: CN
Inventors: 刘丽霞
Original assignee: CHANGSHA JINGJIA MICROELECTRONIC Co Ltd
Current assignee: CHANGSHA JINGJIA MICROELECTRONIC Co Ltd
Priority date: 2012-11-02
Filing date: 2012-11-02
Publication date: 2013-02-13

Abstract

The invention discloses a program loading device applied to a radio frequency communication transceiver and a relative method. In an embodiment, all memories have a plurality of bus interfaces and one access memory arbiter. Loading of radio frequency communication processing program is achieved by utilizing the memory controller. The method includes processing program and constant parameter and initializing data loading. The device and the method have the advantage of utilizing identical hardware to load different software programs to achieve different functions and being capable of conveniently debugging the software programs.

Description

Utilize radio communication receiver equipment thereof and the correlation technique of Memory Controller loading procedure

Technical field

The present invention relates to a kind of program loading equipemtn and method for radio frequency (RF) communication transceiver height Integrated Solution, more specifically refer to a kind of program loading equipemtn and method for audio broadcasting transceiver height Integrated Solution.

Background technology

Along with the develop rapidly of integrated circuit (IC) design and manufacturing technology, radio-frequency (RF) communication system has been stepped into the SOC epoch.Radio communication height Integrated Solution has overcome the shortcoming that volume is large, cost is high, power consumption is high of Integrated Solution on traditional employing multi-chip plate, set up highly integrated SOC (system on a chip), the components and parts that only need to add seldom just can be worked, and performance has also had large increase, has possessed high receiving sensitivity.

Semiconductor system comprises FPGA (Field Programmable Gate Array) usually, such as processor, controller etc., can realize several functions by programming to same semiconductor system, designs and develops the cycle with shortening, thereby saves cost.The digital signal processor that comprises in the radio communication Integrated Solution (DSP), MCU are typical FPGA (Field Programmable Gate Array), the functions such as FM receiver, AM/SW/LW receiver, WB receiver, FM transmitter can be realized by writing different programs, different parameters can also be disposed to adapt to the demand of different geographical.

Summary of the invention

The problem that the present invention solves provides the program loading equipemtn in a kind of radio communication Integrated Solution, and the program loading method that utilizes this equipment to realize.

For solving the problems of the technologies described above, the solution that the present invention proposes is: DSP, MCU, bus control interface, Memory controller and storer are integrated in on the semiconductor device, utilize the Memory controller, by the register in external bus control interface or the MCU configuration Memory controller, realization is carried out read-write operation to internal storage, also can realize the data transmission between the on-chip memory.When carrying out data transmission between the Memory controller control store, but assigned source start address, target start address and data transfer size are carried out transmission of data blocks.Storer comprises other storer on the special function register of the program storage of the program storage of DSP and data-carrier store, MCU and data-carrier store, MCU and the sheet.After the Memory controller is finished several transformation tasks of MCU appointment, send interrupt request to MCU, notice MCU task is finished.The Memory controller has an independently address mapping table, and all memory mapped are to corresponding address space, irrelevant with the address mapping of DSP and MCU.

Nonvolatile memory among the present invention comprises non-programmable nonvolatile memory and programmable non-volatile memory.MCU controls Memory controller reading and writing internal storer or when internal storage carried out data transmission, the program that at first needs to control the Memory controller write the MCU program storage, has certain limitation.Therefore bus control interface can directly be accessed the register of Memory controller among the present invention, can pass through bus interface reading and writing internal storer and register, and flexible operation has overcome the former limitation, but inconvenient user use.The present invention is in conjunction with the advantage of two kinds of methods, do not need the parameter of debugging and algorithm stores in non-programmable nonvolatile memory, needs the parameter of debugging and algorithm stores in programmable non-volatile memory.In the algorithm debugs process by bus interface with algorithm and parameter read-in internal volatile memory, after debugging is finished with remaining algorithm and parameter read-in programmable non-volatile memory.System at first carries out data and loads when starting, by the programmed control Memory controller of MCU, give volatile memory with the data in the nonvolatile memory.

Storer among the present invention has a plurality of bus interface and a memory access moderator.Described a plurality of bus interface has host separately, and the host of one of them interface is the Memory controller, and each host has different memory access priority.If when only having a host accesses storer, this host is connected with storer and carries out read-write operation so.When if a plurality of host accesses storer is arranged simultaneously, the memory access moderator will be according to each host's priority, and the host that priority is high is connected with storer and carries out read-write operation.In the program loading procedure, only has Memory controller access storer.

Description of drawings

Fig. 1 is program loading equipemtn block diagram;

Fig. 2 is multi-bus interface storer synoptic diagram;

Fig. 3 is that program loads process flow diagram.

Embodiment

The invention will be further described below with reference to accompanying drawing and implementation.

As shown in Figure 1, the invention provides the program loading equipemtn in the integrated scheme of a kind of radio communication transceiver, comprise Memory controller, MCU, bus control interface and a plurality of storer.As shown in Figure 2, the storer among the present invention has a plurality of bus interface and a memory access moderator.

Program loading equipemtn of the present invention has two kinds of data sources, the outer data of the data in the sheet in the nonvolatile memory and sheet.The invention provides two kinds of program loading methods, a kind of is to use bus control interface from the outer loading program of sheet, is called the outer Loading Method of sheet; Another kind is to use MCU control Memory controller nonvolatile memory in the sheet to load data, is called Loading Method in the sheet.The below illustrates respectively this two kinds of program loading methods.

Bus control interface is from equipment interface in the present embodiment, is connected with another host device interface, and host device interface sends the order of read-write memory.The process that sends order is at first to send the order of reading address register or writing address register, sends the order of read/write data register again.In the present embodiment, the input of address register comprises oneself and increases 1 logic, so the address consecutive hours of reference-to storage, only need send for the first time start address, do not need afterwards to repeat to send the order of reading address register or writing address register, can directly send the order of read/write data register.In the present embodiment, bus control interface is serial control interface, also can be parallel bus interface.

Fig. 3 has showed the idiographic flow of Loading Method in the sheet, and whole process only has reset operation to need user program to participate in, and other is all finished automatically by chip.Automatically finished by the Memory controller after being carried in of bootstrap block resets, from nonvolatile memory, boot block data is copied to the program storage of MCU.The effect of bootstrap block is by MCU control Memory controller, boot is written into the MCU program storage from nonvolatile memory.The effect of boot is by MCU control Memory controller, from nonvolatile memory, algorithm is written into MCU program storage and DSP program storage, and the parameter of using in the algorithm is written in the special function register of DSP data-carrier store, MCU data-carrier store and MCU.In the present embodiment, Loading Method adopts the mode that segmentation loads in the sheet, also can adopt disposable monoblock to load, and can select segmentation loading and monoblock to load according to practical situations.The Memory controller is whenever finished one piece of data and is transmitted backward MCU transmission interrupt request, judges by the interrupt service subroutine of MCU whether the data loading is finished.

Claims

1. a radio communication transceiver comprises digital signal processor (DSP), microcontroller (MCU), bus control interface, storer (Memory) controller, a plurality of storeies;

Comprise in the described Memory controller and read address register, writing address register, data register and a plurality of control register, register has two interfaces, and an Interface ﹠ Bus control interface connects, and another interface is connected with MCU;

Described bus control interface is realized the operation of access on-chip memory and register by the register of configuration Memory controller;

Described MCU realizes the transmission of data blocks between the on-chip memory by the register of configuration Memory controller, and the Memory controller is finished the backward MCU of specified data block transformation task and sent interrupt request, and notice MCU task is finished.

2. bus control interface according to claim 1 is characterized in that: all storeies of addressable inside and register.

3. Memory controller according to claim 1 is characterized in that: internal storage and register are had independently address mapping table.

4. a plurality of storer according to claim 1 comprises volatile memory and nonvolatile memory, and nonvolatile memory comprises non-programmable nonvolatile memory and programmable non-volatile memory.

5. a plurality of storer according to claim 1, it is characterized in that: storer has a plurality of bus interface and a moderator, and the host of one of them bus interface is the Memory controller.

6. Memory controller according to claim 1, it is characterized in that: the Memory controller comprises the steering logic of programmable non-volatile memory; By the external bus control interface programmable non-volatile memory is programmed.

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