CN102916128A - Method for producing tungsten oxide based resistive memorizer - Google Patents
Method for producing tungsten oxide based resistive memorizer Download PDFInfo
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- CN102916128A CN102916128A CN2011102215536A CN201110221553A CN102916128A CN 102916128 A CN102916128 A CN 102916128A CN 2011102215536 A CN2011102215536 A CN 2011102215536A CN 201110221553 A CN201110221553 A CN 201110221553A CN 102916128 A CN102916128 A CN 102916128A
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Abstract
本发明属于电阻型存储器技术领域，涉及一种与标准逻辑工艺兼容的氧化钨基电阻型存储器的制备方法，其包括步骤：构图刻蚀所述上电极材料层以在存储阵列部分的钨栓塞上的氧化钨基阻变存储介质层之上形成上电极；其中，设置所述上电极材料层的刻蚀工艺条件以使逻辑部分的钨栓塞上的氧化钨基阻变存储介质在所述刻蚀步骤的过刻蚀过程中去除。该方法无需增加额外掩膜版即可形成氧化钨基存储介质层，可省去一次光刻步骤，简化工艺流程，节省制造成本。
The invention belongs to the technical field of resistive memory, and relates to a preparation method of a tungsten oxide-based resistive memory compatible with a standard logic process, which includes the steps of: patterning and etching the upper electrode material layer to form a tungsten plug on the memory array part The upper electrode is formed on the tungsten oxide-based resistive storage medium layer; wherein, the etching process conditions of the upper electrode material layer are set so that the tungsten oxide-based resistive storage medium on the tungsten plug of the logic part is etched step is removed during the overetch. The method can form a tungsten oxide-based storage medium layer without adding an additional mask plate, which can save a photolithography step, simplify the process flow, and save manufacturing costs.
Description
Technical field
The invention belongs to the resistor-type memory technical field, relate to a kind of preparation method of WOx-based resistive memory, relate in particular to the preparation method with the WOx-based resistive memory of standard logic process compatibility.
Background technology
Memory occupies an important position in semi-conductor market, because portable electric appts is constantly universal, the share of nonvolatile memory in whole storage market is also increasing.Nearest non-volatile resistor-type memory (Resistance Random Access Memory, RRAM) but because the characteristics of its high density, low cost break-through skill node development restriction cause show great attention to.Resistor-type memory utilizes the resistance of storage medium to come storage signal in the characteristic of reversible transformation under the effect of the signal of telecommunication, between high resistant and low-resistance.Storage medium can have a variety of, comprises binary or multi-element metal oxide, even organic compound, wherein, binary metal oxide because it is simple in structure, speed is fast, low in energy consumption, compatible strong with traditional cmos process, and receive much concern.
WO
x(1＜x≤3) are a kind of as binary metal oxide, and are perfect compatible with the Al interconnection process, need not to introduce new material, and can autoregistration form WO on tungsten plug
xStorage medium, cost advantage is obvious.
Present report based on WO
x" medium/metal/metal " resistor-type memory structure (be WOx-based resistive memory, tungsten oxide base storage medium is WO
x) adopt tungsten plug to make bottom electrode, the upper layer interconnects line is as memory top electrode, WO
xThe storage medium autoregistration is formed at the tungsten plug top, but in the practical application, can not form WO on the tungsten plug of logical gate (not being integrated with the part of resistor-type memory)
xThereby logical gate need to be covered up in the memory cell in preparation, guarantee that its tungsten plug is not oxidized, this causes the storage array part need to separate with logical gate making, increase extra lithography step and prepare top electrode, thereby increase process complexity and cost.
Summary of the invention
The object of the invention is to defective and deficiency that prior art exists, a kind of preparation method of new WOx-based resistive memory is provided, relate in particular to the preparation method with the WOx-based resistive memory of standard logic process compatibility, the method can reduce complexity and the cost of technique.
For realizing above purpose or other purpose, the invention provides a kind of preparation method of WOx-based resistive memory, described WOx-based resistive memory forms by the tungsten plug oxidation to the interconnection rear end structure, described tungsten plug comprises the tungsten plug of storage array part and the tungsten plug of logical gate, and this preparation method may further comprise the steps:
The structure that tungsten plug exposes in the interconnection rear end structure is provided;
To the tungsten plug oxidation of all exposures to form tungsten oxide base resistance-change memory dielectric layer;
Deposition upper electrode material layer is to cover described tungsten oxide base resistance-change memory dielectric layer; And
The described upper electrode material layer of patterned etch is to form top electrode on the tungsten oxide base resistance-change memory dielectric layer on the tungsten plug of described storage array part;
It is characterized in that, in described etch step, arrange described upper electrode material layer etch technological condition so that the tungsten oxide base resistance-change memory medium on the tungsten plug of described logical gate in the over etching process of described etch step, remove.
According to preparation method provided by the invention, wherein, under described etch technological condition, the gas of the described upper electrode material of etching simultaneously can the described tungsten oxide base of etching resistance-change memory dielectric layer.
In an embodiment of the present invention, preferably, described very aluminium, aluminium copper, titanium nitride, titanium, hafnium, cobalt, zirconium or the Ti/TiN composite bed of powering on.
In preparation method's of the present invention embodiment, preferably, described etching technics adopts dry etching, and etching gas can be Cl
2, BCl
3, CCl
4Or SiCl
4
In preparation method's of the present invention embodiment, preferably, described tungsten plug is as the bottom electrode of described WOx-based resistive memory.
Among the present invention, described tungsten oxide base resistance-change memory dielectric layer is WO
x, 1＜x≤3 wherein.
In an embodiment of the present invention, preferably, described tungsten oxide base resistance-change memory dielectric layer can be first to reoxidizing formation after the silication of bottom electrode tungsten.
In an embodiment of the present invention, preferably, described method for oxidation can be for oxidation in the oxygen-containing atmosphere, by the oxygen plasma oxidation or by the ion injection method oxidation.
In an embodiment of the present invention, preferably, described silicification method can be to finish by the ion injection method of silication or silicon in silication in the silicon-containing gas, the silicon plasma.
In an embodiment of the present invention, preferably, the thickness range of described tungsten oxide base resistance-change memory dielectric layer can be 1 nanometer to 20 nanometer.
In an embodiment of the present invention, preferably, described tungsten plug is the tungsten plug in aluminium interconnection or the copper-connection rear end structure.
In an embodiment of the present invention, preferably, the time range of described over etching is 30 seconds to 10 minutes.
Beneficial effect of the present invention is, the preparation method's of the WOx-based resistive memory of of the present invention and standard logic process compatibility advantage has:
When making described resistor-type memory, form tungsten oxide base dielectric layer and deposit the upper electrode material layer to cover described tungsten oxide base dielectric layer by the tungsten plug autoregistration oxidation to storage array part and logical gate, afterwards the etch technological condition by described upper electrode material layer is set so that the tungsten oxide base medium on the tungsten plug of described logical gate in the over etching process of described etch step, remove, thereby need not to increase the extra mask version and can form tungsten oxide base storage medium layer, can save lithography step one time, simplification of flowsheet is saved manufacturing cost.
Description of drawings
Fig. 1 is the method schematic diagram for preparing WOx-based resistive memory that provides according to one embodiment of the invention;
Fig. 2 is the structural representation after the perforate in interlayer dielectric layer (PMD);
Fig. 3 is that deposition forms storage array partly and the structural representation behind the tungsten plug of logical gate;
Fig. 4 is to the structural representation behind the tungsten plug oxidation formation tungsten oxide base resistance-change memory dielectric layer of all exposures;
Fig. 5 is the structural representation behind the deposition upper electrode material layer;
Fig. 6 is the structural representation after mask exposure forms photoetching offset plate figure;
Fig. 7 be the described upper electrode material layer of patterned etch and in the over etching process, remove logical gate tungsten oxide base dielectric layer after structural representation;
Fig. 8 is the structural representation after finishing top electrode on the tungsten oxide base resistance-change memory dielectric layer on the tungsten plug of described storage array part;
Fig. 9 is the structural representation behind the ground floor aluminum lead material layer of deposition of aluminum interconnection rear end;
Figure 10 is the structural representation after photoetching forms ground floor aluminum lead figure.
Embodiment
Describe more completely the present invention in the reference example in conjunction with being shown in hereinafter, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein.In the drawings, amplify layer and regional thickness for clear, but should not be considered to strictly reflect the proportionate relationship of physical dimension as schematic diagram.
Be the schematic diagram of idealized embodiment of the present invention at this reference diagram, embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of dry etching has crooked or mellow and full characteristics usually, but in embodiment of the invention diagram, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.
In this article, " storage array part " refers to be integrated with in the rear end structure array portion of WOx-based resistive memory; " logical gate " refers to not be integrated with in the rear end structure the corresponding integration section of standard logic process of WOx-based resistive memory.
Figure 1 shows that the method schematic diagram for preparing WOx-based resistive memory that one embodiment of the invention provides.In this embodiment, mainly provide the committed step that is different from prior art, other do not embody spirit of the present invention, those skilled in the art know the concrete grammar step of knowing no further details to be given herein.Fig. 2 illustrates the preparation process schematic diagram of method shown in Figure 1 to Figure 10 shows that by structure example.Below in conjunction with Fig. 2 to Figure 10, the method for preparing WOx-based resistive memory of this embodiment is described in detail.
Step S10 provides the structure that tungsten plug exposes in the interconnection rear end structure.
Figure 2 shows that the structural representation after the perforate in interlayer dielectric layer (PMD).After interconnection front end metal-oxide-semiconductor is finished, above it deposit etching barrier layer and inter-level dielectric 100 (PMD), etching barrier layer can be Si
3N
4, SiC or other play the material of same purpose, pmd layer 100 refers to the dielectric layer between ground floor wiring and the MOS device, it can be the low-k dielectric materials such as the silica (PSG) of mixing phosphorus or SiCOH.Afterwards in pmd layer 100, by method formation storage array part tungsten plug cavity 101 and the logical gate tungsten plug cavity 102 of mask lithography.
With reference to Figure 3 shows that deposition forms storage array partly and the structural representation behind the tungsten plug of logical gate.In pmd layer 100, form storage array part tungsten plug 201 and diffusion impervious layer 200, and logical gate tungsten plug 203 and diffusion impervious layer 202, wherein tungsten plug connects ground floor aluminum lead and metal-oxide-semiconductor source electrode or drain electrode.Tungsten plug 201 or 203 and pmd layer 100 between for preventing that tungsten diffusion from introducing diffusion impervious layer 200 or 202, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, such as TiSiN, WN
x, WN
xC
y, Ru or TiZr/TiZrN etc.Need to carry out the planarization operation by chemico-mechanical polishing after filling tungsten plug 201 and 203.So far, provide the structure that exposes as the tungsten plug of WOx-based resistive memory bottom electrode.
Further, step S20 is to the tungsten plug oxidation formation tungsten oxide base resistance-change memory dielectric layer of all exposures.
As shown in Figure 4, synchronously form tungsten oxide base dielectric layer at the tungsten plug 201 of storage array part and tungsten plug 203 tops of logical gate, wherein, tungsten oxide base dielectric layer 300 is tungsten oxide base dielectric layers of storage array part, it is used for keeping the resistor-type memory that formation is integrated in rear end structure, tungsten oxide base dielectric layer 301 is tungsten oxide base dielectric layers of logical gate, for fear of its impact on logical circuit, needs to remove in subsequent process.Particularly, mainly adopt oxidation in the oxygen-containing atmosphere, prepare tungsten oxide base dielectric layer by the oxygen plasma oxidation or by methods such as ion injection method oxidations.Owing to be directly to the oxidation of tungsten plug top, thereby belong to self-registered technology, need not increase extra mask plate.Tungsten oxide base resistance-change memory dielectric layer 300 and 301 thickness ranges are 1 nanometer to 20 nanometer, for example, and 12 nanometers.In another embodiment, also can adopt first to form tungsten oxide base storage medium layer to reoxidizing after the tungsten plug silication, wherein silicidation mainly adopts the methods such as Implantation of silication in silication in the silicon-containing gas, the silicon plasma or silicon to finish.Contain silicon doping in the tungsten oxide base storage medium layer that reoxidizes after elder generation's silication, and the tungsten oxide base storage medium layer that forms is fine and close, low resistance state resistance is high, thereby is conducive to reduce power consumption.
Need to prove, in the present invention, the WO that tungsten oxide base storage medium layer refers to have storage characteristics
x(1＜x≤3) or have storage characteristics and the WO of certain doped chemical is arranged
x(1＜x≤3) (for example, WO of doped silicon
x).
Further, step S30, deposition upper electrode material layer is to cover described tungsten oxide base resistance-change memory dielectric layer.
As shown in Figure 5, deposition one deck top electrode metal level 400 above tungsten oxide base dielectric layer, the gas that the over etching step requires etching top electrode metal material after considering simultaneously can etching oxidation tungsten based dielectric material, and the top electrode metal material can be but be not limited only to be aluminium, aluminium copper, titanium nitride, titanium, hafnium, cobalt, zirconium or Ti/TiN composite bed etc.Top electrode covers the tungsten oxide base resistance-change memory dielectric layer (300 and 301) of storage array part and logical gate fully.
Step S40, the described upper electrode material layer of patterned etch is to form top electrode on the tungsten oxide base resistance-change memory dielectric layer on the tungsten plug of described storage array part.
As shown in Figure 6, spin coating one deck photoresist above upper electrode material layer 400, and utilize the mask plate exposure of special definition tungsten oxide base storage medium top electrode to form photoetching offset plate figure 500.
Further with reference to shown in Figure 7, core of the present invention is by the etch technological condition that described upper electrode material layer is set so that the tungsten oxide base resistance-change memory medium on the tungsten plug of logical gate is removed in the over etching process of the etch step of S40, thereby under the condition that does not increase the extra mask version, both partly formed tungsten oxide base resistance-change memory dielectric layer 300 at storage array, stay pure tungsten plug directly to contact (in the process of tungsten oxide base resistance-change memory dielectric layer 301 at over etching by simultaneously etching remove) with afterwards aluminum lead at logical gate again, realized the good compatibility with standard logic process.Etch technological condition in this step can regulated aspect the parameters such as etching gas, etch period, preferably, based on the aluminium interconnection process, adopts dry etching, etching gas can but to be not limited to be Cl
2, BCl
3, CCl
4Or SiCl
4Deng, the etch period scope is 30 seconds to 10 minutes.Those skilled in the art are according to above enlightenment, can select particularly (or experiment draws) etch technological condition (the particularly process conditions in the over etching process) according to thickness and the material behavior of the thickness of upper electrode material layer 400 and material, tungsten oxide base resistance-change memory dielectric layer; Preferentially, in the etching process, over etching and whole etching process are carried out continuously, for example, keep same etching gas (this etching gas is energy while etching upper electrode material layer 400 and tungsten oxide base dielectric layer 301 under this set etching condition).When judging whether tungsten oxide base resistance-change memory dielectric layer 301 is removed by over etching fully, can test the tungsten oxide base dielectric layer 301 of decision logic part whether to remove fully by Real-Time Monitoring or electricity aspect connectivity.
With reference to shown in Figure 8, remove the photoresist of top electrode 600 tops.
So far, finish top electrode 600 preparations of the tungsten oxide base resistance-change memory dielectric layer of described storage array part.Tungsten plug, tungsten oxide resistance-change memory dielectric layer 300 and top electrode 600 form a resistor-type memory unit.
Can continue afterwards to finish conventional aluminium interconnection backend process, comprise the steps such as formation of each layer aluminum lead and tungsten plug.
As shown in Figure 9, deposition of aluminum lead material layer.Wherein weld layer 701 is formed between upper strata aluminum lead 700 and the pmd layer 100, cover simultaneously storage array part top electrode 600 and logical gate tungsten plug 203, the main adhesive attraction that rises, reduce the contact resistance between tungsten plug and the metal lead wire, it can be Ti, TiN, Ti/TiN composite bed, or other plays the electric conducting material of same purpose, such as TiSiN, WN
x, WN
xC
y, TiZr/TiZrN etc.The material of aluminum lead 700 is the ground floor aluminum lead at this embodiment, and it can be Al or AlCu alloy etc.Anti-reflecting layer 702 is positioned on the aluminum lead 700, mainly plays the antireflective effect, improves lithographic accuracy, can be TiN, or the non-organic substance such as SiON and the organic substance material that plays same purpose.
Further with reference to shown in Figure 10, photoetching forms ground floor aluminum lead figure.Ground floor aluminum lead 801 covers top electrode 600, links to each other with the upper strata tungsten plug as storage array lead-in wire partly; Ground floor aluminum lead 802 directly contacts with tungsten plug 203, as the lead-in wire of logical gate.
Among the above embodiment, only the tungsten plug in pmd layer being formed resistor-type memory is illustrated, those skilled in the art should be understood that, the preparation method of above WOx-based resistive memory is equally applicable on the tungsten plug of different layers of aluminium interconnection rear end structure, also or go on the tungsten plug of copper-connection rear end.
Above embodiment has mainly illustrated the method that technique of the present invention is integrated.Although only the some of them embodiments of the present invention are described, those of ordinary skills should understand, and the present invention can be within not departing from its purport and scope implements with many other forms.Therefore, the example of showing and execution mode are regarded as illustrative and not restrictive, and in situation about not breaking away from such as the defined spirit of the present invention of appended each claim and scope, the present invention may be contained various modifications and replacement.
Claims (12)
1. the preparation method of a WOx-based resistive memory, described WOx-based resistive memory forms by the tungsten plug oxidation to the interconnection rear end structure, described tungsten plug comprises the tungsten plug of storage array part and the tungsten plug of logical gate, and this preparation method may further comprise the steps:
The structure that tungsten plug exposes in the interconnection rear end structure is provided;
To the tungsten plug oxidation of all exposures to form tungsten oxide base resistance-change memory dielectric layer;
Deposition upper electrode material layer is to cover described tungsten oxide base resistance-change memory dielectric layer; And
The described upper electrode material layer of patterned etch is to form top electrode on the tungsten oxide base resistance-change memory dielectric layer on the tungsten plug of described storage array part;
It is characterized in that, in described etch step, arrange described upper electrode material layer etch technological condition so that the tungsten oxide base resistance-change memory medium on the tungsten plug of described logical gate in the over etching process of described etch step, remove.
2. preparation method as claimed in claim 1 is characterized in that, under described etch technological condition, the gas of the described upper electrode material of etching is the described tungsten oxide base of etching resistance-change memory dielectric layer simultaneously.
3. preparation method as claimed in claim 1 or 2 is characterized in that, described very aluminium, aluminium copper, titanium nitride, titanium, hafnium, cobalt, zirconium or the Ti/TiN composite bed of powering on.
4. such as claim 1 or 2 or 3 described preparation methods, it is characterized in that described etching technics adopts dry etching, etching gas is Cl
2, BCl
3, CCl
4Or SiCl
4
5. preparation method as claimed in claim 1 is characterized in that, described tungsten plug is as the bottom electrode of described WOx-based resistive memory.
6. preparation method according to claim 1 is characterized in that, described tungsten oxide base resistance-change memory dielectric layer is WO
x, 1＜x≤3 wherein.
7. preparation method according to claim 1 is characterized in that, described tungsten oxide base resistance-change memory dielectric layer is first to reoxidizing formation after the silication of bottom electrode tungsten.
8. such as claim 1 or 7 described preparation methods, it is characterized in that described method for oxidation is oxidation in the oxygen-containing atmosphere, passes through the oxygen plasma oxidation or pass through the ion injection method oxidation.
9. preparation method according to claim 7 is characterized in that, described silicification method is to finish by the ion injection method of silication or silicon in silication in the silicon-containing gas, the silicon plasma.
10. according to claim 1 or 6 described preparation methods, it is characterized in that the thickness range of described tungsten oxide base resistance-change memory dielectric layer is 1 nanometer to 20 nanometer.
11. preparation method according to claim 1 is characterized in that, described tungsten plug is the tungsten plug in aluminium interconnection or the copper-connection rear end structure.
12. preparation method according to claim 1 and 2 is characterized in that, the time range of described over etching is 30 seconds to 10 minutes.
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