CN102915948A - Forming method of a shallow-groove isolation structure - Google Patents
Forming method of a shallow-groove isolation structure Download PDFInfo
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- CN102915948A CN102915948A CN2012103989717A CN201210398971A CN102915948A CN 102915948 A CN102915948 A CN 102915948A CN 2012103989717 A CN2012103989717 A CN 2012103989717A CN 201210398971 A CN201210398971 A CN 201210398971A CN 102915948 A CN102915948 A CN 102915948A
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Abstract
A forming method of a shallow-groove isolation structure comprises the following steps of providing a substrate; forming an isolation groove inside the substrate; precipitating a medium layer inside the isolation groove and on the surface of the substrate, and fulfilling the isolation groove with the medium layer and covering the substrate on two sides of the isolation groove with the medium layer; etching the medium layer; and flattening the etched medium layer until the substrate is exposed, and forming the shallow-groove isolation structure. Due to adopting the forming method of the shallow-groove isolation structure, the flatness of the surface of the shallow-groove isolation structure is improved, the isolation performance of the shallow-groove isolation structure is improved, and the performance of a semiconductor device comprising the shallow-groove isolation structure is further improved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of formation method of fleet plough groove isolation structure.
Background technology
Along with semiconductor technology enters the deep-submicron epoch, the element below 0.18 micron (for example between the active area of CMOS integrated circuit) mostly adopts fleet plough groove isolation structure (STI) to carry out lateral isolation and makes.
Fleet plough groove isolation structure is as a kind of device separation, and its concrete technology comprises: with reference to figure 1, provide substrate 101; With reference to figure 2, form silicon nitride layer 103 at described substrate 101; With reference to figure 3, form the opening 105 that runs through described silicon nitride layer 103, described opening 105 has the shape corresponding with the isolation structure that defines active area; With reference to figure 4, take the silicon nitride layer 103 that comprises opening 105 as mask, etched substrate 101 is to form isolated groove 107; With reference to figure 5, the silicon nitride layer 103 surface deposition silica materials 109 of in isolated groove 107 and the opening 105 and opening both sides in Fig. 4, described silica material 109 are filled full isolated groove 107 and opening 105 and are covered the silicon nitride layer 103 of opening 105 both sides; With reference to figure 6, by unnecessary silica material 109 on the silicon nitride layer 103 among CMP technique removal Fig. 5, form fleet plough groove isolation structure 111; With reference to figure 7, remove silicon nitride layer 103, and form grid structure at active area, in the active area of grid structure both sides, form heavily doped region.
Along with constantly reducing of feature sizes of semiconductor devices, the size that is used for the fleet plough groove isolation structure of device isolation also diminishes, accordingly, the depth-to-width ratio that is used to form the isolated groove of fleet plough groove isolation structure becomes large, accumulation occurs and causes isolated groove to seal in advance in silica material at silicon nitride layer 103 split sheds 105 edges in the silica deposition process, avoid formed fleet plough groove isolation structure 111 interior existence cavities, existing technique mainly adopts the technique of the etching while depositing to carry out the silica deposition.Yet, be positioned at silica material unnecessary on the silicon nitride layer 103 109 by the removal of CMP technique, when forming fleet plough groove isolation structure 111, easily form cut on formed fleet plough groove isolation structure 111 surfaces, cause the isolation performance of fleet plough groove isolation structure 111 not good, the semiconductor device that comprises fleet plough groove isolation structure 111 easily leaks electricity, and has had a strong impact on the stability of the semiconductor device that comprises fleet plough groove isolation structure 111.
In being the United States Patent (USP) of US7112513, the patent No. can also find more relevant informations about the shallow trench isolation technology.
Therefore, how to avoid forming cut at formed surface of shallow trench isolation structure, improve the isolation performance of the fleet plough groove isolation structure that forms, just become those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of fleet plough groove isolation structure, improves the evenness of the surface of shallow trench isolation structure that forms, and then improves the performance of the semiconductor device that forms.
For addressing the above problem, the invention provides a kind of formation method of fleet plough groove isolation structure, comprising: substrate is provided; In described substrate, form isolated groove; In described isolated groove and the substrate surface metallization medium layer, described dielectric layer is filled full isolated groove and is covered the substrate of isolated groove both sides; Described dielectric layer is returned quarter; The dielectric layer that returns after carving is carried out planarization, to exposing substrate, form fleet plough groove isolation structure.
Optionally, the material of described dielectric layer is silica.
Optionally, in described isolated groove and the method for substrate surface metallization medium layer be: in metallization medium layer the dielectric layer that has deposited is carried out etching, wherein the speed of cvd dielectric layer is greater than to the speed of metallization medium layer etching.
Optionally, the method for metallization medium layer is chemical vapour deposition (CVD).
Optionally, the reacting gas of described chemical vapour deposition (CVD) is silane and oxygen, and the volume ratio of silane and oxygen is 1:2 ~ 1:3, and temperature is 600 degrees centigrade ~ 800 degrees centigrade, and the time is 50s ~ 70s.
The method of optionally, the dielectric layer that has deposited being carried out etching is dry etching.
Optionally, described dielectric layer being returned the method for carving is dry etching.
Optionally, the etching gas of described dry etching is inert gas, and the flow of etching gas is 60sccm ~ 120sccm, and pressure is 5mTorr ~ 11mTorr, and etch period is 5s ~ 20s.
The method of optionally, the dielectric layer after return carving being carried out planarization is chemical mechanical milling tech.
Optionally, before forming isolated groove, also comprise: deposit stop-layer at described substrate.
Optionally, the material of described stop-layer is silicon nitride.
Compared with prior art, technical solution of the present invention has the following advantages:
In formed isolated groove and after the substrate surface metallization medium layer, by dielectric layer is returned quarter, the drift angle that is arranged in substrate surface dielectric layer tip-angled shape projection is increased, reduce the difference in height between the summit of isolated groove medium layer surface and tip-angled shape projection, with when the dielectric layer after returning quarter is carried out planarization, it is inhomogeneous that the dielectric layer that improvement causes because thickness of dielectric layers is inhomogeneous is removed speed, guarantee that formed surface of shallow trench isolation structure is smooth, improve the isolation performance of the fleet plough groove isolation structure that forms, and then improve the performance of the semiconductor device that comprises the fleet plough groove isolation structure that forms.
Description of drawings
Fig. 1 to Fig. 7 is the cross-sectional view of fleet plough groove isolation structure that prior art forms;
Fig. 8 is the schematic flow sheet of an execution mode of formation method of fleet plough groove isolation structure of the present invention;
Fig. 9 to Figure 16 by among embodiment of formation method of fleet plough groove isolation structure of the present invention the cross-sectional view of formation fleet plough groove isolation structure.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subjected to the restriction of following public implementation.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the invention was described in detail in detail, for ease of explanation, described schematic diagram was example, and it should not limit the scope of protection of the invention at this.
Just as described in the background section, prior art is being positioned at silica material unnecessary on the silicon nitride layer by the removal of CMP technique, when forming fleet plough groove isolation structure, easily form cut at surface of shallow trench isolation structure, cause the isolation performance of fleet plough groove isolation structure not good, the semiconductor device that comprises fleet plough groove isolation structure easily leaks electricity, the poor stability of semiconductor device.
The inventor finds through research, existing technique is when the process deposits silica material by the etching while depositing, the depositing operation in the horizontal direction silica material deposition rate of each position is identical, but because the silicon nitride layer of edge of opening at an angle, so that the silica material contact-making surface that etching gas and edge of opening have deposited in the etching technics is larger, cause silica material etch rate to edge of opening greater than the etch rate to silica material on the silicon nitride layer, and then cause silica material to be piled up at silicon nitride layer, form the tip-angled shape projection.And along with constantly reducing of active area live width, the drift angle that is positioned at tip-angled shape projection on the silicon nitride layer is also more and more less, and the difference in height between the top of tip-angled shape projection and the isolated groove Oxygen Above SiClx material surface is increasing.Follow-up when removing silica material unnecessary on the silicon nitride layer by CMP technique, because the difference in thickness of each position silica material is too large on the silicon nitride layer, CMP technique is inhomogeneous to the removal speed of silica material, forms cut at surface of shallow trench isolation structure.
And, the inventor also finds after further research, make in the silicon nitride layer process-exposed by CMP technique removal silica material, also may expose because the overmastication to the part silicon nitride layer makes the substrate that is positioned at the silicon nitride layer below, to the substrate injury, affect the formation technique of follow-up semiconductor device and the performance of the semiconductor device that forms.
For defects, the invention provides a kind of formation method of fleet plough groove isolation structure, forming isolated groove and in described isolated groove and after substrate surface deposited dielectric layer, dielectric layer is returned quarter, reduce the difference in height between the substrate surface dielectric layer between isolated groove medium layer and the isolated groove, when the dielectric layer after returning quarter is carried out planarization, avoid forming cut at formed surface of shallow trench isolation structure, improve the isolation performance of the fleet plough groove isolation structure that forms, and then improved the stability of the semiconductor device that comprises the fleet plough groove isolation structure that forms.
With reference to figure 8, the schematic flow sheet for formation method one execution mode of fleet plough groove isolation structure of the present invention comprises:
Step S1 provides substrate;
Step S2 deposits stop-layer at described substrate;
Step S3, the described stop-layer of etching to exposing substrate, forms some openings;
Step S4 along the described substrate of opening etching, forms isolated groove;
Step S5, in described isolated groove and opening and stop-layer surface deposition dielectric layer, described dielectric layer is filled full isolated groove and opening and is covered the stop-layer of described opening both sides;
Step S6 returns quarter to described dielectric layer;
Step S7 carries out planarization to the dielectric layer that returns after carving, and to exposing stop-layer, forms fleet plough groove isolation structure;
Step S8 removes described stop-layer.
Be elaborated below in conjunction with accompanying drawing.
With reference to figure 9 ~ Figure 16, show the cross-sectional view of the fleet plough groove isolation structure that forms among formation method one embodiment of fleet plough groove isolation structure of the present invention, in conjunction with Fig. 9 ~ Figure 16, elaborate by the formation method of specific embodiment to fleet plough groove isolation structure of the present invention.
With reference to figure 9, provide substrate 201.
Particularly, described substrate 201 can be silicon substrate, germanium silicon substrate or silicon-on-insulator (SOI), or well known to a person skilled in the art other semiconductive material substrate.In the present embodiment, described substrate 201 is silicon substrate.
With reference to Figure 10, form stop-layer 203 at described substrate 201.
In the present embodiment, the material of described stop-layer 203 is silicon nitride.The formation method of described stop-layer 203 is chemical vapour deposition (CVD) (CVD, Chemical Vapor Deposition) technique.
With reference to Figure 11, form the opening 205 that runs through described stop-layer 203, described opening 205 has the shape corresponding with the fleet plough groove isolation structure that defines active area.
In the present embodiment, form when running through the opening 205 of described stop-layer 203, comprise the steps:
Form successively from the bottom to top mask layer and photoresist layer (not shown) on described stop-layer 203 surfaces;
The described photoresist layer of patterning forms the photoresist layer that comprises patterns of openings;
Take photoresist layer as mask, along the described mask layer of patterns of openings etching, form the mask layer that comprises patterns of openings;
Take the mask layer that comprises patterns of openings as mask, the described stop-layer 203 of etching forms the opening 205 that runs through described stop-layer 203;
Remove described photoresist layer and the mask layer that comprises patterns of openings.
With reference to Figure 12, take the stop-layer 203 that is formed with opening 205 as mask, the described substrate 201 of etching forms isolated groove 207.
In the present embodiment, the method for the described substrate 201 of etching can be dry etching, and its concrete lithographic method is well known to those skilled in the art, and does not do at this and gives unnecessary details.
With reference to Figure 13, in isolated groove described in Figure 12 207 and opening 205 and stop-layer 203 surface deposition dielectric layer 209a, described dielectric layer 209a fills full isolated groove 207 and opening 205 and covers the stop-layer 203 of described opening 205 both sides.
In the present embodiment, the method that deposits described dielectric layer 209a is: in metallization medium layer 209a the dielectric layer 209a that has deposited is carried out etching, wherein the speed of dielectric layer 209a deposition is greater than the speed to the dielectric layer 209a etching that deposited.
In the present embodiment, the method that deposits described dielectric layer 209a is chemical vapor deposition method, and the reacting gas of described chemical vapour deposition (CVD) is silane (SiH
4) and oxygen (O
2), the volume ratio of silane and oxygen is 1:2 ~ 1:3, and temperature is 600 degrees centigrade ~ 800 degrees centigrade, and the reaction time is 50s ~ 70s.
The method of the dielectric layer 209a that has deposited being carried out etching is dry etching.The etching gas of described dry etching is inert gas, such as argon gas, helium etc.; The flow of described etching gas is 60sccm ~ 120sccm, and pressure is 5mTorr ~ 11mTorr.
In the present embodiment, form described dielectric layer 209a by the method for in metallization medium layer 209a, the dielectric layer 209a that has deposited being carried out etching, can avoid dielectric layer 209a in the generation accumulation of opening 205 edges and cause isolated groove 207 to seal in advance, and then avoid having the cavity in the formed fleet plough groove isolation structure, improved the isolation performance of the fleet plough groove isolation structure that forms.
When the described dielectric layer 209a of deposition, the deposition rate of each position, stop-layer 203 top is identical; But, because the stop-layer 203 at opening 205 edges at an angle, when the dielectric layer 209a that has deposited is carried out etching, etching gas is larger with the dielectric layer 209a contact-making surface that is positioned at opening 205 edges, cause etch rate to the dielectric layer 209a at opening 205 edges greater than the etch rate to dielectric layer 209a on stop-layer 203 between the adjacent apertures 205, and then cause dielectric layer 209a to pile up at stop-layer 203, form tip-angled shape projection 213a among Figure 13, the sidewall of described tip-angled shape projection 213a and the angle α of vertical direction are less, cause the difference in height h on tip-angled shape projection 213a top and dielectric layer 209a surface, isolated groove 207 top
1Larger.
With reference to Figure 14,209a returns quarter to dielectric layer described in Figure 13.
In the present embodiment, it is dry etching that described dielectric layer 209a is returned the method for carving, and the etching gas of described dry etching is inert gas, and the flow of etching gas is 60sccm ~ 120sccm; Pressure is 5mTorr～11mTorr.
Because to be positioned on the isolated groove 207 contact-making surface of dielectric layer 209a and etching gas large for the contact-making surface of tip-angled shape projection 213a and etching gas among the dielectric layer 209a, dielectric layer 209a is being returned in the process at quarter, etching technics is very fast to tip-angled shape projection 213a etch rate among the dielectric layer 209a, the sidewall of the tip-angled shape projection 213b of Hui Kehou and the angle of vertical direction
Angle α than the sidewall that returns paracone angular protrusions 213a at quarter among Figure 13 and vertical direction is large (namely
), and return the difference in height h that carves metacone angular protrusions 213b top and dielectric layer 209b surface, isolated groove 207 top
2Than returning the difference in height h that carves paracone angular protrusions 213a top and dielectric layer 209a surface, isolated groove 207 top among Figure 13
1Little (is h
2＜h
1), reduced the difference in height of isolated groove 207 top dielectric layer 209b and stop-layer 203 top dielectric layer 209b in the vertical directions, be beneficial to the flatening process of subsequent dielectric layers 209b.
With reference to Figure 15, dielectric layer 209b described in planarization Figure 14 is to exposing stop-layer 203.
In the present embodiment, the method for the described dielectric layer 209b of planarization is chemical mechanical milling tech.
Because the difference in height of isolated groove 207 top dielectric layer 209b and stop-layer 203 top dielectric layer 209b in the vertical directions is less, during the described dielectric layer 209b of planarization, etching technics is more consistent to the removal speed of dielectric layer 209b, the fleet plough groove isolation structure 209c surfacing, the isolation performance that form after the planarization are better, have improved the performance that comprises the semiconductor device of fleet plough groove isolation structure 209c that forms.
And because the difference in height of isolated groove 207 top dielectric layer 209b and stop-layer 203 top dielectric layer 209b in the vertical directions is less, when by CMP technique dielectric layer 209b being carried out planarization, probability to stop-layer 203 overetch is less, and described stop-layer 203 can effectively avoid flatening process that substrate 201 is impacted.
With reference to Figure 16, remove described stop-layer 203.
In the present embodiment, described stop-layer 203 is silicon nitride, and the method for removing described stop-layer 203 is wet etching, as can adopt hot phosphoric acid process directly remove as described in stop-layer 203.
After removing described stop-layer 203, the upper surface of the fleet plough groove isolation structure 209c that forms is a little more than the upper surface of substrate 201, and the isolation performance of fleet plough groove isolation structure 209c is better.
So far, finished the formation technique of fleet plough groove isolation structure 209c.
Described fleet plough groove isolation structure 209c can be used at the bottom of the isolation liner active area (not shown) in 201, and described active area is used for follow-up formation device, as: transistor, diode, resistor, capacitor, inductor etc.; Also can be used for other active and passive semiconductor devices that isolation forms by multiple integrated circuit fabrication process.According to the difference of actual fabrication device, follow-up formation technique is not identical yet, does not repeat them here.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (12)
1. the formation method of a fleet plough groove isolation structure is characterized in that, comprising:
Substrate is provided;
In described substrate, form isolated groove;
In described isolated groove and the substrate surface metallization medium layer, described dielectric layer is filled full isolated groove and is covered the substrate of isolated groove both sides;
Described dielectric layer is returned quarter;
The dielectric layer that returns after carving is carried out planarization, to exposing substrate, form fleet plough groove isolation structure.
2. the formation method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the material of described dielectric layer is silica.
3. the formation method of fleet plough groove isolation structure as claimed in claim 1 or 2, it is characterized in that, in described isolated groove and the method for substrate surface metallization medium layer be: in metallization medium layer the dielectric layer that has deposited is carried out etching, wherein the speed of cvd dielectric layer is greater than to the speed of metallization medium layer etching.
4. the formation method of fleet plough groove isolation structure as claimed in claim 3 is characterized in that, the method for metallization medium layer is chemical vapour deposition (CVD).
5. the formation method of fleet plough groove isolation structure as claimed in claim 4, it is characterized in that, the reacting gas of described chemical vapour deposition (CVD) is silane and oxygen, and the volume ratio of silane and oxygen is 1:2 ~ 1:3, temperature is 600 degrees centigrade ~ 800 degrees centigrade, and the time is 50s ~ 70s.
6. the formation method of fleet plough groove isolation structure as claimed in claim 3 is characterized in that, the method for the dielectric layer that has deposited being carried out etching is dry etching.
7. the formation method of fleet plough groove isolation structure as claimed in claim 6 is characterized in that, the etching gas of described dry etching is inert gas, and the flow of etching gas is 60sccm ~ 120sccm, and pressure is 5mTorr ~ 11mTorr, and etch period is 5s ~ 20s.
8. the formation method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, it is dry etching that described dielectric layer is returned the method for carving.
9. the formation method of fleet plough groove isolation structure as claimed in claim 8 is characterized in that, the etching gas of described dry etching is inert gas, and the flow of etching gas is 60sccm ~ 120sccm, and pressure is 5mTorr ~ 11mTorr, and etch period is 5s ~ 20s.
10. the formation method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the method for the dielectric layer after time quarter being carried out planarization is chemical mechanical milling tech.
11. the formation method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, before forming isolated groove, also comprises: deposit stop-layer at described substrate.
12. the formation method of fleet plough groove isolation structure as claimed in claim 11 is characterized in that, the material of described stop-layer is silicon nitride.
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| CN104517884A (en) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN107221511A (en) * | 2016-03-22 | 2017-09-29 | 世界先进积体电路股份有限公司 | Method for manufacturing trench isolation structure |
| CN112750755A (en) * | 2019-10-30 | 2021-05-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
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