CN102903821A - Wafer level packaging structure and manufacturing method thereof - Google Patents

Abstract

A wafer-level packaging structure, comprising a packaging substrate, an insulating layer, a conductive layer, a light-emitting element arranged on the conductive layer, and a packaging layer covering the light-emitting element, the bottom surface of the insulating layer forms several In the heat dissipation structure, the insulating layer forms at least one layer of several conductive structures, and the at least one layer of several conductive structures is electrically connected with the conductive layer and the several heat dissipation structures, and the several conductive structures are spaced apart from each other. The present invention uses semiconductors and metals to fill the via holes formed on the upper and lower sides of the packaging substrate to form a one-layer or multi-layer conductive structure, which has good stability and efficient thermal and electrical conductivity, and can avoid glue dispensing and glue leakage of the packaging layer , At the same time, the heat generated by the heating element can be quickly transferred to the external heat dissipation metal pad. The invention also relates to a manufacturing method of the wafer-level packaging structure.

Description

Wafer level packaging structure and manufacturing method thereof

technical field

The invention relates to a packaging structure and a manufacturing method thereof, in particular to a wafer-level packaging structure and a manufacturing method thereof.

Background technique

Different from the traditional packaging technology that takes a single chip as the processing target, wafer-level packaging uses wafers as the packaging processing object. Its main purpose is to simplify the chip packaging process to save time and cost. After the integrated circuits on the wafer are fabricated, the entire wafer can be packaged directly, and then wafer sawing is performed to form multiple chip packages. The completed chip package can be mounted on a carrier board.

In the application of wafer-level packaging, the packaging substrate is relatively thick. Generally, the required pattern structure is formed by etching, and via holes are formed on the upper and lower sides of the packaging substrate. During the packaging process, the light-emitting element will be covered with a package. Layer, the material of the encapsulation layer is encapsulation glue doped with phosphor powder, the traditional method adopts the way of filling the conductive glue at the via hole to solve the problem of dispensing glue leakage, because the heat dissipation performance of the conductive glue is insufficient and the long-term heat It will cause the conductive adhesive itself to change, thereby affecting the service life of the packaging structure, and at the same time, the relatively high production cost of filling all metal substances. Therefore, how to provide a packaging structure that solves glue dispensing and glue leakage, and has excellent heat dissipation effect and low manufacturing cost is still a problem to be solved in the industry.

Contents of the invention

In view of this, it is necessary to provide a wafer-level packaging structure and a manufacturing method thereof that can solve glue dispensing and glue leakage, and have excellent heat dissipation effect and low manufacturing cost.

A wafer-level packaging structure, comprising a packaging substrate, an insulating layer, a conductive layer, a light-emitting element arranged on the conductive layer, and a packaging layer covering the light-emitting element, the bottom surface of the insulating layer forms several In the heat dissipation structure, the insulation layer forms at least one layer of several conductive structures, and the at least one layer of several conductive structures is electrically connected with the conductive layer and the plurality of heat dissipation structures, and the several conductive structures are spaced apart from each other.

A method for manufacturing a wafer-level packaging structure, the steps of which include: providing a packaging substrate, the packaging substrate includes a first surface and a second surface, forming a plurality of grooves on the second surface; forming an etch stop layer, the insulating layer is attached to the plurality of grooves; forming a groove on the first surface, and partially exposing the etch stop layer; forming an insulating dielectric layer on the surface of the groove , the insulating dielectric layer is partially in contact with the etch stop layer; at least one layer of a plurality of mutually separated via holes is formed at the contact portion of the etch stop layer and the insulating dielectric layer, and metal is filled in the plurality of via holes to form a plurality of conductive structure; a plurality of heat dissipation structures are formed by clamping in the second groove, and the plurality of heat dissipation structures are electrically connected to the conductive structure; a conductive layer is formed on the insulating dielectric layer, and the conductive layer includes a plurality of spaced electrodes, The plurality of electrodes are electrically connected to the plurality of conductive structures; a light-emitting element is provided, and the light-emitting element is electrically connected to the plurality of electrodes by wire bonding or flip-chip; a packaging layer is provided, and the packaging layer is doped with fluorescent light. Powder encapsulation glue, the encapsulation layer covers the light-emitting element and is bonded to the insulating dielectric layer.

Compared with the prior art, the present invention uses semiconductors and metals to fill the via holes formed on the upper and lower sides of the packaging substrate to form a one-layer or multi-layer conductive structure, which has good stability and efficient thermal and electrical conductivity, and can avoid the encapsulation layer Dispensing and leakage of glue, and at the same time, the heat generated by the heating element can be quickly transferred to the external heat dissipation metal pad.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a wafer-level packaging structure according to an embodiment of the present invention.

2 to 5 are schematic cross-sectional views of wafer-level packaging structures according to different embodiments of the present invention.

FIG. 6 to FIG. 12 are schematic diagrams of various steps of a manufacturing method of a wafer-level packaging structure according to an embodiment of the present invention.

Description of main component symbols

Package Substrate 10 etch stop layer 20 insulating dielectric layer 30 conductive layer 40 Light emitting element 50 encapsulation layer 60 Heat dissipation metal pad 70 conductive structure 80 first surface 11 second surface 12 first groove 110 first slope 111 second slope 112 First Positioning Department 113 second groove 120 first conductive structure 81 Body 71 Extension 72 third slope 31 fourth slope 32 Second Positioning Department 33 second conductive structure 82 first electrode 41 second electrode 42 Card set 410 reflector 411 Connection 412 first protrusion 115 second protrusion 36 conductive structure 83,84 third electrode 43 first part 13 the second part 14 the third part 34 fourth part 35

The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

Detailed ways

Please refer to FIG. 1, the wafer level packaging structure of a preferred embodiment of the present invention includes a package substrate 10, an etch stop layer 20, an insulating dielectric layer 30, a conductive layer 40, and the A light emitting element 50 and an encapsulation layer 60 covering the insulating dielectric layer 30 . A plurality of heat dissipation metal pads 70 are formed on the bottom surface of the etching stop layer 20 , and the insulating dielectric layer 30 forms a two-layer conductive structure 80 . The two-layer conductive structure 80 forms an electrical connection with the conductive layer 40 and the plurality of heat dissipation metal pads 70 .

Specifically, the packaging substrate 10 has a first surface 11 and a second surface 12 opposite to the first surface 11 . The first surface 11 adopts photolithography to form a patterned structure, and adopts an etching method to form a first groove 110. The first groove 110 includes two symmetrical slopes and a bottom surface, and the bottom surface is horizontal. Extending, each slope is stepped, including a first slope 111, a second slope 112 and a horizontal first positioning portion 113 connecting the first slope 111 and the second slope 112, wherein the two symmetrical first slopes The horizontal distance of 111 is greater than the horizontal distance of the two symmetrical second slopes 112 . The second surface 12 of the packaging substrate 10 forms several second grooves 120 at intervals, and the number of the second grooves 120 is three in this embodiment. The packaging substrate 10 can be a conductive substrate or an insulating substrate, the conductive substrate can be a copper foil substrate or any other suitable conductive material; the insulating substrate can be made of one or more of the following materials: silicon (Si), arsenic Gallium oxide (GaAs), zinc oxide (ZnO) and indium phosphide (InP), etc.

The etch stop layer 20 is formed on the second surface 12 of the packaging substrate 10 and adheres to the three second grooves 120 of the second surface 12 . The etching stop layer 20 is an insulating layer, which can be made of insulating materials such as silicon oxide and silicon nitride. Since the first surface 11 of the packaging substrate 10 adopts photolithography and etching to form a patterned concave structure (ie, the first groove 110 ), the upper surface of the etching stop layer 20 is partially exposed. The etch stop layer 20 is partially etched corresponding to the second groove 120 to form two symmetrical vias, the two vias are spaced apart from each other, and the vias are filled with a metal material to form the first conductive structure 81 .

A plurality of heat dissipation metal pads 70 are formed on the bottom surface of the etching stop layer 20 and are inserted and accommodated in the plurality of second grooves 120. In this embodiment, the number of the plurality of heat dissipation metal pads 70 is three, and each heat dissipation metal pad 70 includes a body part 71 and two extension parts 72 extending symmetrically from both sides of the body part 71. Each extension part 72 first extends obliquely downward along the side of the second groove 120 and then bends along the second groove 120. The surface 12 extends horizontally so as to be clamped and fixed in the second groove 120 of the second surface 12 .

The insulating dielectric layer 30 is formed on the first surface 11 of the packaging substrate 10 and adheres to the first surface 11 of the packaging substrate 10 and the upper surface of the etching stop layer 20 , corresponding to the first groove 110 The shapes exhibit a similar structure. The insulating dielectric layer 30 includes a third slope 31 , a fourth slope 32 and a horizontal second positioning portion 33 connecting the third slope 31 and the fourth slope 32 . The insulating dielectric layer 30 is an insulating layer and can be made of insulating materials such as silicon oxide and silicon nitride. The insulating dielectric layer 30 is etched to form a plurality of guide holes corresponding to the positions of the exposed etching stop layer 20. In this embodiment, the number of the guide holes is 4, and adjacent guide holes are spaced apart from each other and filled with metal materials. A second conductive structure 82 is formed. The second conductive structure 82 is electrically connected to the first conductive structure 81 .

A conductive layer 40 is formed on the insulating dielectric layer 30, and the conductive layer 40 includes a plurality of spaced electrodes. In this embodiment, the number of the plurality of electrodes is three, including two symmetrical first electrodes 41 located on both sides and a second electrode 42 located between the two first electrodes 41 . Each first electrode 41 includes an engaging portion 410 , a reflecting portion 411 and a connecting portion 412 . The engaging portion 410 is attached to the second positioning portion 33 to fix the first electrode 41 . The reflection part 411 is attached to the third slope 31 and has a reflection function, which can make the light output of the packaging structure more uniform. The connection portion 412 is in contact with the second conductive structure 82 to achieve an effective electrical connection. The second electrode 42 is in the shape of a rectangular plate, the second electrode 42 is in contact with the second conductive structure 82 and is used to support the light emitting element 50 .

The light-emitting element 50 is disposed on the second electrode 42 , and the light-emitting element 50 may be a light-emitting device such as a light-emitting diode die, an organic light-emitting diode die, or the like. In this embodiment, the light-emitting element 50 is a light-emitting diode crystal grain, and is electrically connected to the two first electrodes 41 that are symmetrical on both sides by bonding.

The encapsulation layer 60 is arranged on the light-emitting element 50, and the encapsulation layer 60 is attached to the upper surface of the insulating dielectric layer 30. The encapsulation layer 60 is an encapsulation glue doped with phosphor powder, and the fluorescent tape contains garnet-based phosphor One or more of silicate-based phosphors, orthosilicate-based phosphors, sulfide-based phosphors, thiogallate-based phosphors, nitrogen oxide-based phosphors, and nitride-based phosphors kind.

Please refer to FIG. 2, which is another embodiment of the wafer-level packaging structure of the present invention, including a package substrate 10, an etch stop layer 20, an insulating dielectric layer 30, a conductive layer 40, and the conductive layer 40 A light-emitting element 50 on the top and an encapsulation layer 60 covering the insulating dielectric layer 30 . A plurality of heat dissipation metal pads 70 are formed on the bottom surface of the etching stop layer 20 , and a layer of conductive structures 83 spaced apart from each other is formed on the insulating dielectric layer 30 . The conductive structure 83 is electrically connected to the conductive layer 40 and the plurality of heat dissipation metal pads 70 .

Specifically, the packaging substrate 10 has a first surface 11 and a second surface 12 opposite to the first surface 11 . The first surface 11 adopts photolithography to form a patterned structure, and adopts an etching method to form a first groove 110. The first groove 110 includes a first portion 13 located above and further on the first portion 13. Two second parts 14 formed by extending downwards at intervals. A first protruding portion 115 is formed between the two second portions 14 , and the first protruding portion 115 is used for carrying the light emitting element 50 . The first portion 13 of the first groove 110 has a first slope 111 , the second portion 14 has a second slope 112 , and a horizontal first positioning portion 113 is connected between the first slope 111 and the second slope 112 . The horizontal distance between the two symmetrical first slopes 111 is greater than the horizontal distance between the two symmetrical second slopes 112 . The second surface 12 of the packaging substrate 10 forms a plurality of second grooves 120 at intervals. In this embodiment, the number of the second grooves 120 is two, and the positions correspond to the second part 14 of the first groove 110. . The packaging substrate 10 can be a conductive substrate or an insulating substrate, the conductive substrate can be a copper foil substrate or any other suitable conductive material; the insulating substrate can be made of one or more of the following materials: silicon (Si), arsenic Gallium oxide (GaAs), zinc oxide (ZnO) and indium phosphide (InP), etc.

The etch stop layer 20 is formed on the second surface 12 of the packaging substrate 10, and is attached to the two second grooves 120 of the second surface 12. The etch stop layer 20 is an insulating layer, which can be made of silicon oxide, nitrogen Made of insulating materials such as silicon carbide. Since the first surface 11 of the packaging substrate 10 adopts photolithography and etching to form a patterned concave structure, the upper surface of the etching stop layer 20 is partially exposed.

A plurality of heat dissipation metal pads 70 are formed on the bottom surface of the etching stop layer 20 and are inserted and accommodated in the plurality of second grooves 120. In this embodiment, the number of the plurality of heat dissipation metal pads 70 is two, and each heat dissipation metal pad 70 includes a body part 71 and two extension parts 72 extending symmetrically from both sides of the body part 71. Each extension part 72 first extends obliquely downward along the side of the second groove 120 and then bends along the second groove 120. The surface 12 extends horizontally so as to be clamped and fixed in the second groove 120 of the second surface 12 .

The insulating dielectric layer 30 is formed on the first surface 11 of the packaging substrate 10 and adheres to the first surface 11 of the packaging substrate 10 and the upper surface of the etching stop layer 20 , corresponding to the first groove 110 The shape presents a similar structure, including an upper third portion 34 and two fourth portions 35 further extending downward from the third portion 34 at intervals. A second protruding portion 36 is formed between the two fourth portions 35 , and the second protruding portion 36 is used for carrying the light emitting element 50 . The third portion 34 has a third slope 31 , the fourth portion 35 has a fourth slope 32 , and a horizontal second positioning portion 33 is connected between the third slope 31 and the fourth slope 32 . The horizontal distance between the two symmetrical third slopes 31 is greater than the horizontal distance between the two symmetrical fourth slopes 32 . The insulating dielectric layer 30 is an insulating layer and can be made of insulating materials such as silicon oxide and silicon nitride. The insulating dielectric layer 30 is etched to form a plurality of guide holes corresponding to the positions of the exposed etching stop layer 20. In this embodiment, the number of the guide holes is 4, and adjacent guide holes are spaced apart from each other and filled with metal materials. A conductive structure 83 is formed.

A conductive layer 40 is formed on the insulating dielectric layer 30, and the conductive layer 40 includes a plurality of spaced electrodes. In this embodiment, the number of the plurality of electrodes is four, including two symmetrical first electrodes 41 located on both sides, and a second electrode 42 located on the protruding portion. Each first electrode includes an engaging portion 410 , a reflecting portion 411 and a connecting portion 412 . The engaging portion 410 is attached to the second positioning portion 33 to fix the first electrode 41 . The reflection part 411 is attached to the third slope 31 and has a reflection function, which can make the light output of the packaging structure more uniform. The connecting portion 412 is in contact with the conductive structure 83 to achieve an effective electrical connection. The second electrode 42 is in the shape of a rectangular block for supporting the light emitting element 50 .

The light-emitting element 50 is disposed on the second electrode 42 , and the light-emitting element 50 may be a light-emitting device such as a light-emitting diode die, an organic light-emitting diode die, or the like. In this embodiment, the light-emitting element 50 is a light-emitting diode crystal grain, and is electrically connected to the two first electrodes 41 that are symmetrical on both sides by bonding.

The encapsulation layer 60 is arranged on the light-emitting element 50, and the encapsulation layer 60 is attached to the upper surface of the insulating dielectric layer 30. The encapsulation layer 60 is an encapsulation glue doped with phosphor powder, and the fluorescent tape contains garnet-based phosphor One or more of silicate-based phosphors, orthosilicate-based phosphors, sulfide-based phosphors, thiogallate-based phosphors, nitrogen oxide-based phosphors, and nitride-based phosphors kind.

Please refer to FIG. 3, which is another embodiment of the wafer-level packaging structure of the present invention. The wafer-level packaging structure in this embodiment is similar to the embodiment shown in FIG. The first electrode 41 on the side is connected as a whole, and an electrical connection point of the light emitting element 50 is in direct contact with the second electrode 42 to form an electrical connection. Another electrical connection point of the light-emitting element 50 is effectively electrically connected to the first electrode 41 on the right by wire bonding.

Please refer to FIG. 4, which is another embodiment of the wafer-level packaging structure of the present invention. The wafer-level packaging structure in this embodiment is similar to the embodiment shown in FIG. 2, except that the etching stop layer 20 corresponds to the first Partial etching of the two grooves 120 forms two symmetrical square guide holes, the two guide holes are spaced apart from each other and metal material is filled in the guide holes to form another conductive structure 84 .

Please refer to FIG. 5, which is another embodiment of the wafer-level packaging structure of the present invention. The wafer-level packaging structure in this embodiment is similar to the embodiment shown in FIG. 2, except that the two symmetrical first electrodes 41 all extend to the second protruding portion 36, and the light-emitting element 50 is effectively electrically connected to the two electrodes in a flip-chip manner.

Compared with the prior art, the present invention uses semiconductors and metals to fill the via holes formed on the upper and lower sides of the packaging substrate to form a one-layer or multi-layer conductive structure, which has good stability and efficient thermal and electrical conductivity, and can avoid the encapsulation layer Dispensing and leakage of glue, and at the same time, the heat generated by the heating element can be quickly transferred to the external heat dissipation metal pad.

Taking the wafer-level packaging structure of the embodiment of the present invention as an example, the manufacturing process of the wafer-level packaging structure will be described with reference to FIG. 1 .

The first step, please refer to FIG. 6, provides a packaging substrate 10, the packaging substrate 10 can be a conductive substrate or an insulating substrate, the conductive substrate can be a copper foil substrate or any other suitable conductive material; the insulating substrate can be made of the following materials One or more of: silicon (Si), gallium arsenide (GaAs), zinc oxide (ZnO) and indium phosphide (InP), etc. The packaging substrate has a first surface 11 and a second surface 12. Photolithography and etching techniques are used to form a patterned structure on the second surface 12. The second surface 12 includes a plurality of second grooves 120. In this embodiment, The number of the plurality of second grooves 120 is three.

The second step, please refer to FIG. 7, forms an etch stop layer 20 on the second surface 12 of the package substrate 10, and the etch stop layer 20 is attached to the three second grooves 120. The etch stop layer 20 is An insulating layer may be made of insulating materials such as silicon dioxide, silicon nitride, titanium dioxide, tantalum dioxide, etc., preferably, silicon dioxide in this embodiment.

The third step, please refer to FIG. 8 , is to use photolithography to form a patterned structure on the first surface 11 of the packaging substrate 10, and to form a first groove 110 by etching. The first groove 110 includes symmetrical Two slopes and a bottom surface, the bottom surface extends horizontally, each slope includes a first slope 111, a second slope 112 and a horizontal first positioning portion 113 connecting the first slope 111 and the second slope 112 , wherein the horizontal distance between the two symmetrical first slopes 111 is greater than the horizontal distance between the two symmetrical second slopes 112 . The positions of the plurality of second grooves 120 corresponding to the second surface 12 are etched until the etching stop layer 20 is exposed.

The fourth step, referring to FIG. 9 , is to form an insulating dielectric layer 30 on the first surface 11 of the packaging substrate 10, the insulating dielectric layer 30 is attached to the bottom surface and the two slopes of the first groove 110, and is in contact with The exposed etch stop layer 20 is attached. The shape corresponding to the first groove 110 presents a similar structure, which includes a third slope 31, a fourth slope 32 and a horizontal second positioning portion 33 connecting the third slope 31 and the fourth slope 32, while The bottom surface of the insulating dielectric layer 30 is attached to the bottom surface of the first groove 110 and presents the same structure. The insulating dielectric layer 30 is an insulating layer, which can be made of insulating materials such as silicon dioxide, silicon nitride, titanium dioxide, tantalum dioxide, etc., preferably, silicon dioxide in this embodiment.

The fifth step, please refer to FIG. 10 , using etching technology to form one or more layers of several guide holes in the etch stop layer 20 and the insulating dielectric layer 30, the several guide holes are spaced apart from each other, and filling the several guide holes Metal. In this embodiment, the number of guide holes in the etching stop layer 20 is two, and the number of guide holes in the insulating dielectric layer 30 is four. After the metal is filled, two first conductive structures 81 are formed in the two guide holes of the etching stop layer 20, and four second conductive structures 82 are formed in the four guide holes of the insulating dielectric layer 30. The first The conductive structure 81 is electrically connected to the second conductive structure 82 .

The sixth step is to form a plurality of heat dissipation metal pads 70 on the bottom surface of the etching stop layer 20, and the plurality of heat dissipation metal pads 70 are clamped and accommodated in the plurality of second grooves 120. In this embodiment, the plurality of heat dissipation metal pads 70 The number is three, and each heat dissipation metal pad 70 includes a body portion 71 and two extension portions 72 extending symmetrically from both sides of the body portion 71, and each extension portion 72 is inclined along the side of the second groove 120 first. Extending downwards and then bending along the second surface 12 to extend horizontally, so as to be clamped and fixed in the second groove 120 of the second surface 12, the plurality of heat dissipation metal pads 70 and the first conductive structure 81 and the second The conductive structure 82 forms an electrical connection.

In the seventh step, please refer to FIG. 11 , a conductive layer 40 is formed on the insulating dielectric layer 30 , and the conductive layer 40 includes a plurality of spaced electrodes. In this embodiment, the number of the plurality of electrodes is three, including two first electrodes 41 located symmetrically on both sides and a second electrode 42 located between the two first electrodes 41 . Each first electrode 41 includes a clamping portion 410, a reflective portion 411 and a connecting portion 412. The clamping portion 410 is attached to the second positioning portion 33 to fix the first electrode 41. The reflective portion 411 is in contact with the third slope 31 and has a reflective function, which can make the light output of the packaging structure more uniform. The connection part 412 is in contact with the second conductive structure 82 to achieve an effective electrical connection. The second electrode 42 is in the shape of a rectangular plate, the second electrode 42 is in contact with the second conductive structure 82 and is used to support the light emitting element 50 .

The eighth step, please refer to FIG. 12 , disposes a light-emitting element 50 on the second electrode 42 , and the light-emitting element 50 may be a light-emitting device such as a light-emitting diode die or an organic light-emitting diode die. In this embodiment, the light-emitting element 50 is a light-emitting diode crystal grain, and is electrically connected to the two first electrodes symmetrical on both sides by bonding.

Finally, an encapsulation layer 60 is provided on the light-emitting element 50, the encapsulation layer 60 is attached to the upper surface of the insulating dielectric layer 30, the encapsulation layer 60 is an encapsulation glue doped with phosphor, and the fluorescent tape contains pomegranate One of stone-based phosphors, silicate-based phosphors, orthosilicate-based phosphors, sulfide-based phosphors, thiogallate-based phosphors, oxynitride-based phosphors, and nitride-based phosphors one or more species.

It can be understood that those skilled in the art can make various other corresponding changes and modifications according to the technical concept of the present invention, and all these changes and modifications should belong to the protection scope of the claims of the present invention.

Claims (10)

1. A wafer-level packaging structure, comprising a packaging substrate, an insulating layer, a conductive layer, a light-emitting element arranged on the conductive layer and a packaging layer covering the light-emitting element, the bottom surface of the insulating layer Forming a plurality of heat dissipation structures is characterized in that: the insulating layer forms at least one layer of several conductive structures, the at least one layer of several conductive structures is electrically connected to the conductive layer and the plurality of heat dissipation structures, and the plurality of conductive structures are spaced apart from each other. 2. The wafer-level packaging structure according to claim 1, wherein the insulating layer comprises an etch stop layer and an insulating dielectric layer, the package substrate comprises a first surface and a second surface, the etching A stop layer is formed on the second surface, the insulating dielectric layer is formed on the first surface, and the etching stop layer is partially in contact with the insulating dielectric layer, and the conductive structure is located at a portion where the etching stop layer contacts the insulating dielectric layer . 3 . The wafer level packaging structure according to claim 2 , wherein a plurality of via holes are formed at the contact portion of the etching stop layer and the insulating dielectric layer, and conductive materials are arranged in the via holes to form the conductive structure. 4 . 4. The wafer level packaging structure according to claim 3, wherein the number of vias on the etching stop layer is different from the number of vias on the insulating dielectric layer. 5 . The wafer level packaging structure according to claim 2 , wherein the conductive layer includes two electrodes spaced apart from each other, and the light emitting element is electrically connected to the two electrodes by means of flip chip. 6. The wafer level packaging structure according to claim 2, wherein the conductive layer comprises two symmetrical first electrodes and a second electrode located between the two first electrodes, the two first electrodes and The second electrodes are spaced apart from each other. 7 . The wafer level packaging structure according to claim 6 , wherein the light emitting element is disposed on the second electrode, and is electrically connected to the first electrodes on both sides by wire bonding. 8 . 8. A method for manufacturing a wafer-level packaging structure, the steps comprising: A packaging substrate is provided, the packaging substrate includes a first surface and a second surface, and a plurality of grooves are formed on the second surface; An etching stop layer is formed on the bottom of the second surface, and the insulating layer is attached to the plurality of grooves; forming a groove on the first surface and partially exposing the etching stop layer; forming an insulating dielectric layer on the surface of the groove, the insulating dielectric layer is in partial contact with the etch stop layer; Forming at least one layer of several conducting holes separated from each other at the contact portion of the etching stop layer and the insulating dielectric layer, filling the several conducting holes with metal to form several conductive structures; A plurality of heat dissipation structures are clamped in the second groove, and the plurality of heat dissipation structures are electrically connected to the conductive structure; forming a conductive layer on the insulating dielectric layer, the conductive layer includes a plurality of spaced electrodes, and the plurality of electrodes are electrically connected to the plurality of conductive structures; providing a light-emitting element, the light-emitting element is electrically connected to the plurality of electrodes by wire bonding or flip-chip; An encapsulation layer is provided, the encapsulation layer is an encapsulation glue doped with fluorescent powder, the encapsulation layer is covered on the light-emitting element and partially attached to the insulating dielectric layer. 9. The method for manufacturing a wafer-level packaging structure as claimed in claim 8, wherein: the plurality of conductive structures are spaced apart from each other. 10. The manufacturing method of the wafer level packaging structure according to claim 8, wherein the number of via holes on the etch stop layer is different from the number of via holes on the insulating dielectric layer.

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