CN102882371A - High efficiency pfm control for buck-boost converter - Google Patents

Abstract

A buck-boost voltage regulator generates a regulated output voltage in response to an input voltage and a plurality of control signals. The buck/boost voltage regulator includes a plurality of switching transistors responsive to a plurality of control signals. A control circuit monitors the regulated output voltage and generates a plurality of control signals in response thereto. a control circuit controls operation of a plurality of switching transistors to allow a charge phase in a first mode of operation, a pass phase in a second mode of operation, and a phase of discharge in a third mode of operation in the buck/boost voltage regulator, The occurrence of four-switch switching states is thereby eliminated.

Description

High Efficiency PFM Control for Buck-Boost Converters

Cross References to Related Applications

This application claims the U.S. patent application titled "HIGH EFFICIENCY PFM CONTROLFOR BUCK-BOOST CONVERTER (High Efficiency PFM Control for Buck-Boost Converters)" filed on December 30, 2011 (Docket No. INTS-30600)" U.S. Patent Application No. 13/341,496, filed December 6, 2011, entitled "HIGH EFFICIENCY PFM CONTROL FOR BUCK-BOOST CONVERTER" (Designated Case No. INTS-31056)" and U.S. Provisional Application 61/567,120 filed March 8, 2011 entitled "HIGH EFFICIENCY PFM CONTROL FOR BUCK-BOOST CONVERTER (High Efficiency PFM Control for Buck-Boost Converters ) (Attorney Docket No. INTS-30656)", the specifications of which are hereby incorporated by reference in their entirety.

technical field

The present invention relates to buck-boost converters, and more particularly to buck-boost converters defining four switch switching states.

Background technique

A boost mode of operation is included in a buck-boost converter, where the output voltage is higher than the input voltage. In boost mode, the converter uses pulse frequency modulation (PFM) to control the operation of switching transistors within the converter. In conventional buck-boost converters, boost-mode PFM is very inefficient. This is essentially due to the four-switch switching state that occurs when each of the four switching transistors of the buck-boost converter are switched substantially simultaneously. Some method to limit the four-switch switching state occurrence in the buck-boost converter in the PFM mode of operation can greatly improve the efficiency of the converter.

Contents of the invention

An aspect of the invention includes a DC/DC converter comprising an input terminal for receiving an input voltage from an input voltage source set at an input voltage level. The output terminal provides an output voltage at an output voltage level different from the input voltage level to a load connected to the output terminal. A charge storage element receives and stores charge from an input voltage source on its input side via an input terminal and transfers at least a portion of the stored charge from its output side to a load. The control system controls the storage of charge to and transfer of charge from the charge storage element in at least three repeated stages to obtain the desired level of the output voltage level. The three stages include: a charge storage stage for storing charge from the input terminals in the charge storage element; a first charge transfer stage for transferring only a portion of the stored charge from the charge storage element to the load; The charge transfer stage where charge is transferred to the load.

Description of drawings

For a more complete understanding, reference is now made to the following description in conjunction with the accompanying drawings, in which:

Figure 1 shows the top-level diagram of a PFM buck-boost DC/DC converter;

Figure 1A shows a detailed schematic diagram of an H-bridge switch;

FIG. 2 shows a schematic diagram of different operating modes of a buck-boost converter as a function of input voltage;

3A and 3B illustrate a state of switching operation in boost mode, showing switch states and associated timing diagrams;

4A and 4B illustrate a second state of switching operation in boost mode, showing switch states and associated timing diagrams;

5A and 5B illustrate a third state of switching operation in boost mode, showing switch states and associated timing diagrams;

FIG. 6 shows a timing diagram for boosting voltage using first and second states in PFM operation;

Figure 7 shows the inductor current for a single cycle of the PFM operation of Figure 6;

FIG. 8 shows a first embodiment of boost operation of a buck-boost converter and associated control circuitry with an improved boost PFM control scheme;

FIG. 9 shows waveforms associated with operation of the buck-boost converter of FIG. 8;

Fig. 10 shows the state diagram of the embodiment of Fig. 8 and Fig. 9;

FIG. 11 shows a timing diagram of the state diagram of FIG. 10;

Figure 12 shows an alternative embodiment of boost operation of a buck-boost converter and associated control circuitry with an improved buck-boost PFM control scheme;

FIG. 13 shows waveforms associated with operation of the buck-boost converter of FIG. 12;

Fig. 14 shows the state diagram of the embodiment of Fig. 12 and Fig. 13;

FIG. 15 shows a timing diagram of the state diagram of FIG. 14;

16 and 16A illustrate the operation of the buck side of the converter; and

Figure 17 illustrates an electronic/electrical system including electronic/electrical circuitry with switching circuitry, according to one embodiment.

Detailed ways

Referring now to the drawings, wherein like reference numerals are used to refer to like elements throughout, there is illustrated and described a system and system for high efficiency PFM (pulse frequency modulation) control of a buck-boost converter Various views and embodiments of the method, and other possible embodiments are also described. The drawings are not necessarily to scale and in some instances have been exaggerated and/or simplified in several places for illustrative purposes only. Those of ordinary skill in the art will recognize many possible applications and variations based on the following examples of possible embodiments.

Referring now to FIG. 1 , there is shown a high level schematic diagram of a pulse frequency modulated (PFM) buck-boost DC/DC converter. The DC/DC converter consists of a switching bridge 101 operative to transfer charge from a voltage _input node 116, labeled VIN, to a charge storage element 115 and subsequently to a load, The load is configured as a shunt capacitor 130 (designated C _O ) and resistor _132R placed between voltage output node 128 (designated V _OUT ) and a reference voltage on node 103, which is typically set at ground potential. The bridge 101 is controlled by a PFM buck-boost controller 105 which operates according to a pulse frequency modulation (PFM) mode of operation. This PFM operation is divided into two operations, one for charging the charge storage element 115 and one for transferring the charge stored therein to the load. The PFM operation changes the ratio between these two operations, as briefly described below. A clock input from clock 106 provides the time base for PFM operation.

The bridge 101 is an H bridge. This consists of two nodes 122, 126 between which the charge storage element 115 is arranged. The first switch 106 is connected between the input node 116 and the node 122 . The second switch 108 is connected between the node 122 and the reference node 103 . These two switches 106, 108, as briefly described below, are typically used on the buck side of a buck-boost converter. The other side of the H-bridge includes: a first switch 110 connected between the output voltage node 128 and node 126 on the other side of the charge storage element 115; and a second switch 112 connected between node 126 and the reference Between nodes 103. Switches 110, 112 are typically used in the boost portion of a buck-boost converter. However, the H-bridge configuration allows for versatility in how charge is transferred to and subsequently from the charge storage element 115 to the output node 128, as described in more detail below.

Referring now to FIG. 1A , a more detailed schematic diagram of implementing the H-bridge 101 is shown in FIG. 1A . In this configuration, switch 106 is configured with a p-channel transistor, switch 108 is configured with an n-channel transistor, switch 110 is configured with a p-channel transistor, and switch 112 is configured with an n-channel transistor. The signals controlling the gates of transistors 106, 108 are the BUCK_HS and BUCK_LS signals, respectively. Similarly, the signals controlling the gates of transistors 110, 112 are PFM Boost-d (PFM boost-d) and PFM Boost (PFM boost), respectively. The term "switch" for elements 106, 108, 110, and 112 is interchangeable with the term "transistor" for the same elements appearing in this specification. Charge storage element 115 consists of inductor 114 connected between nodes 122 and 126 .

Referring now to FIG. 2A , FIG. 2A shows a graph of input voltage associated with a target V _OUT voltage as a function of buck-boost mode. The V _OUT voltage is indicated by the dashed line. When the input voltage is lower than V _{OUT_TARGET} -dV ₁ , the DC/DC converter operates in boost mode. When V _IN is between V _{OUT_TARGET} +dV ₂ and V _{OUT_TARGET} -dV ₁ , the DC/DC converter works in buck mode or boost mode. If V _IN is greater than V _{OUT_TARGET} +dV ₂ , the DC/DC converter works in buck mode. When operating in buck-boost mode, this is often referred to as the "transition" phase.

DC/DC converters operate using pulse frequency modulation (PFM), which is sometimes referred to as pulse frequency mode. This utilizes a fixed clock frequency where the charge storage element 115 or inductor 114 is charged for a duration T _ON , followed by a transfer operation for a duration T _OFF . By varying the ratio between T _ON and T _OFF , the amount of charge transferred to the load can be varied as shown in Figure 2B. In boost mode, for example, transistor 106 is closed and transistors 110, 112 are switched to enable store and transfer operations, as described in more detail below. To charge the inductor in boost mode, ie store charge therein, node 126 is pulled down to ground potential by closing transistor 112 and opening transistor 110 when transistor 106 is closed. This is the phase labeled T _ON in Figure 2B. At the end of the T _ON period, transistor 112 is turned off and transistor 110 is closed, transferring charge to the output node 128, which is denoted as the T _OFF period, which lasts until the next occurring edge of the clock. By changing the ratio of the duration of the two cycles T _ON and T _OFF , the amount of charge transferred to the load can be changed. This will be described in more detail below with respect to the operation of the controller 105 in boost mode.

The boost mode operation will be described in the figures below. In general, there are three states in the boost mode of the disclosed embodiments. The first charge phase is used to store charge in the inductor 114, followed by a second transfer state to partially transfer the charge from the inductor 114 to the resistor 132 and a second transfer state to completely transfer the charge in the inductor 114 to the load. Three transfer states.

Referring to Fig. 3A, Fig. 3A shows a schematic diagram of a switch shown in a simplified schematic diagram. For simplicity, the transistor 106 is labeled as S1, the transistor 108 is labeled as S2, the transistor 110 is labeled as S3 and the transistor 112 is labeled as S4, and only the labels of S1, S2, S3 and S4 are shown in the figure. In a first state, labeled state [1], a charging operation is shown. In this operation, S1 is closed and S2 is open such that the voltage V _IN at node 116 is connected to node 122 , which is connected to one side of inductor 114 . The other side of the inductor 114 is connected to a node 126 which is connected to a reference voltage via a switch S4 when the switch S3 is open. This allows the inductor current to ramp up. Figure 3B illustrates this operation. The switch configuration of FIG. 3A in the first state begins at clock edge 301 . The current flowing through switch S4 is illustrated as waveform I _S4 , which shows the current ramping up to point 303 below the current limit. This is the predetermined current value to which the current stored in the inductor 114 can ramp. Once the current is detected at this level, switch S4 will open and the current in inductor 114 will show a charging operation in the waveform labeled _IL .

Referring now to FIGS. 4A and 4B , a simplified schematic diagram of the switch in state [2] and associated timing diagrams are shown in FIGS. 4A and 4B . When the inductor current has reached the predetermined current limit, the state switches from state [1] to state [2] as before, where switch S4 is opened and switch S3 is closed at point 303 . This results in node 126 being connected to output node 128 and resistor 132 . This type of operation is sometimes referred to as "ringing inductor" operation, where the voltage across inductor 114 is reversed because the current flowing through inductor 114 cannot be changed immediately. Therefore, the voltage on the side of the inductor connected to node 126 will be higher than the voltage on node 122 . This causes current to flow to node 128 (when connected to node 128), thereby raising its voltage. This will cause the charge transfer to occur until the end of the clock period on the next clock edge 305 . This operation between time point 303 and clock edge 305 will result in a decrease in inductor current _IL , which is indicative of charge transfer to the load. However, this operation only transfers a fraction of the amount of energy stored in the inductor, and therefore, the inductor current will not decrease to a zero current level. This is indicated at point 307. Likewise, it can be seen that the current through switch S3 will initially rise to the peak current level at which the inductor current is placed at point 309 to indicate current flow therefrom to node 128 when switch S3 is closed. The current flowing through switch S3 is a combination of the current from inductor 114 and the current sourced from V _IN . This current will track the inductor current until point 307, at which point the PFM cycle will change to the next state. The current at this point 307 is not at zero level.

In this state [2], the voltage V _IN is connected to the load through the inductor 114 . Therefore, current will flow out of inductor 114 (stored energy) and also out of node 122 sourced from V _IN . When V _IN is approximately equal to V _OUT , the voltage across inductor 114 will be close to zero, but current will still flow from V _IN .

Referring now to FIGS. 5A and 5B , a simplified schematic diagram of the switches for the third state, State [3] , and associated timing diagrams are shown in FIGS. 5A and 5B . In this state, the transition operation to state [2] will terminate prematurely at point 311 before the next occurring clock edge 305 occurs. The state shown in FIG. 5A begins at point 311 . At this point, an event is detected, such as reaching a voltage limit (ie, a target voltage). This will cause switch S1 to open and switch S2 to close. When this occurs, the rate at which energy is transferred from inductor 114 to node 128 will increase, thereby increasing the rate at which energy is transferred to the load and the rate at which current _IL flows from inductor 114 . This is in part because when current I _L reaches zero at point 313 as determined by current sensor 119, no additional current is sourced from V _IN , switches S2 and S3 will be opened, as this indicates a DC/DC conversion The converter is at the target voltage and no additional energy needs to be transferred to the output load. This can be observed with reference to the current flowing through S3, which drops from the peak current through the inductor down to zero current.

Referring now to FIG. 6, FIG. 6 shows a timing diagram of operation in one embodiment, where state [1] and state [2] occur sequentially. State [1] is the charging cycle and is denoted T _ON , which indicates that S1 is closed and S4 is closed, while state [2] is shown by T _OFF representing S1 on, S4 off and S3 on. In this illustration, the current in inductor 114 is never fully discharged at the beginning of operation. The preceding occurrence is described for the timing diagram of FIG. 4B , where at point 307 the inductor 114 has not been fully charged and therefore there is energy left in the inductor 114 when the clock edge 305 occurs. This results in a current level at the beginning of the next charging cycle or at the beginning of the next state. Therefore, at point 601, the current at the end of the previous state [2] will be at a level greater than zero. At this point, at clock edge 603, switch S1 is closed and switch S3 is open and at clock edge 603 the current through switch S4 is already high but not yet at the peak level of inductor 114, the I _LIMIT level, the predetermined current limit. Therefore, during this state, additional charge will be transferred to the inductor 114 . When the current flowing through the inductor 114 reaches I _LIMIT , the switch S3 will be closed and the switch S4 will be opened. The current level of I _LIMIT is set at a sufficiently high level to ensure that sufficient energy is stored in the inductor 114 for the desired load level. Therefore, when this current level is reached, at current limit edge 605, the current flowing through inductor 114 and through switch S1 will reach I _LIMIT at point 606, and when switch S4 opens, this will be in state [ 2] The level of current flowing through switch S4 initially. Current will be diverted to the load and energy will be dissipated from the inductor 114, and since the side of the inductor 114 at node 126 connected to the load has a voltage initially higher than the input voltage, the voltage across the load will rise above V _IN and energy will be transferred to the load, thereby reducing the energy in the inductor and reducing the current through the inductor. This transfer of energy from the inductor 114 to the load continues until the next clock edge, clock edge 607 . At clock edge 607, switch S4 is closed and switch S3 is opened for the next PFM cycle starting with state [1].

Depending on the load value and the current diverted to the load, the amount of energy removed from the inductor 114 will cause the current drain from the inductor 114 to have a greater or lesser slope as a function of the voltage between V _IN and V _OUT values of both load and voltage. Therefore, on the next clock edge 607 the current level will be lower than the current level at point 601 . In this illustration, at point 609 on the inductor current waveform, the level of the inductor current at point 609 is lower than the current at point 601 . This will cause inductor 114 to need additional time to charge back to current I _LIMIT at point 611 , which increases time T _ON . As time T _ON increases, time T _OFF must decrease so that less time is used to transfer energy from the inductor to the load. Therefore, since the clock period is fixed, the amount of time between T _ON and T _OFF will vary dynamically. It should be understood that since this is a boost operation and node 122 is connected to V _IN through switch S1 during the transition state of state [1], current is diverted both from inductor 114 and from V _IN . Therefore, when the voltages V _IN and V _OUT are substantially equal at the transition between boost and buck operation, the decrease in current from the beginning to the end of T _OFF will be very small. This is shown in FIG. 7 .

For Figure 7, it shows one cycle of the clock between points 701 where switch S4 is closed at the initial current in the previous state. Depending on the current level, the duration of time T _ON will vary until the current reaches I _LIMIT at point 703 . This initiates the next state, state[2], for the transfer operation. The length of this time relative to T _ON depends on the current level at point 701 . The lower the current level, the longer the duration of T _ON and the shorter the duration of T _OFF . During T _OFF , the transfer speed is a function of the load and voltage between V _IN and V _OUT . Thus, it can be seen that the slope of the transfer—that is, the speed at which energy is transferred from the inductor—is represented by the dashed line, which indicates that the slope can be flat, if the voltages are substantially equal, up to a steep slope. However, it can be seen that the inductor current does not fall to the zero crossing point and only a portion of the energy in the inductor 114 is transferred from the inductor 114, so that at the beginning of the next state [1], at point 705, the current through the inductor 114 does not to zero. It can be seen that switch S3 does not need to be opened since the zero crossing is not passed, and switch S1 prevents current flow from the load to the inductor 114 and thus has less output ripple and less switching since switch S2 is not yet closed to completely transfer the charge. As described below in connection with Figures 5A and 5B, at some point during T _OFF , switch S2 is closed and switch S1 is open to increase the rate at which energy is discharged from the inductor, since the current is no longer supplied by V _IN and once the zero crossing is fully Discharging, all switches S1 , S2 , S3 and S4 are open for tri-state nodes 122 , 126 .

Referring further to Figure 7, it can be seen that the fixed clock will provide a clock period of T _Sw between clock edges. The peak current level and T _SW are chosen such that for all load and voltage levels of V _IN , V _OUT and V _OUT-TARGET (or V _LIMIT ), current _IL will not fall to zero current level. Therefore, T _ON is not fixed but varies, and the ratio of T _ON /T _OFF is varied to continuously transfer charge during T _OFF without terminating the inductor from the load until the target voltage is met. This is for a switching operation where switch S3, as opposed to a diode, is a make or break switch that will be reverse biased at near zero current.

Referring now to FIG. 8, details of the boost operation of the buck-boost converter are shown, showing the H-bridge 101 and the associated boost control circuit 104, which communicates with the boost PFM A first embodiment of the (Pulse Frequency Modulation) control mechanism is associated with this boost PFM control mechanism utilizing the state [2] phase passing between the state [1] and state [3] charge and discharge phases to avoid the Four-switch switching state during boost operation. Four-switch switching occurs when each of the four switching transistors in the buck-boost converter switches between one of a logic high state or a logic low state for the same time period. This occurs when the buck-boost converter transitions from a charge phase to a discharge phase or vice versa (as long as state[1] and state[3] are used). The charging phase occurs when the inductor current flowing through the buck-boost converter's inductor 114 increases, and the discharging phase occurs when the inductor current flowing through the buck-boost converter decreases towards the zero-crossing potential. The PFM boost mode of operation utilizes a charge phase in state[1] followed by state[2] by introducing a transfer operation into a "pass through phase" during boost PFM operation between A pass phase in to partially transfer the energy stored in the inductor 114 to the load, and then a discharge phase in state [3] is introduced at some time in the charging operation to fully discharge the inductor 114. This pass phase operation connects V _IN to node 122 and node 126 to output node 128 by turning on transistors 106, 110 and allows inductor current _IL to flow from V _IN to V _OUT , as shown generally at 805 , while allowing current to flow from the inductor 114. When the passing phase occurs, there is no point in time at which the four-switch switching state occurs. This improves the efficiency of the buck-boost converter by up to 15% in boost PFM mode of operation.

Referring now to the drawings, and particularly to FIG. 8 , there is shown an H-bridge 102 and associated control circuit 104 of a buck-boost converter operating in boost mode according to one embodiment. Control circuit 104 monitors the output voltage at node 128 using a resistor divider consisting of resistor 134 connected between node 128 and node 136 and resistor 138 connected between node 136 and ground. Node 136 provides feedback voltage V _FB to the non-inverting input of voltage comparator 140 . The non-inverting input of voltage comparator 140 receives reference voltage V _REF . The output of voltage comparator 140 produces a voltage limited signal, which is provided to a first input of OR gate 142 .

Another input of OR gate 142 is connected to receive the current limit signal from the output of voltage comparator 144 . Voltage comparator 144 receives the _ISNS voltage signal from current sensor 118 at its non-inverting input and the V _LIMIT voltage limit signal from comparator 140 at its inverting input. The output of OR gate 142 is connected to the R input of SR latch 148 . The output of OR gate 142 will generate a logic "high" value in response to the voltage-limit signal or current-limit signal from the outputs of comparators 140, 144, respectively, thereby turning to a logic "high" level. When the feedback voltage V _FB exceeds the reference voltage V _REF , the voltage limit signal turns to a logic "high" level. When the _ISNS signal from the current sensor 118 exceeds the Vi _LIMIT voltage, the current limit signal goes to a logic "high" level.

The output of comparator 140 is also provided as input to buffer 150 . The output of buffer 150 is connected to one input of AND gate 822 and provides the BUCK_LS signal provided as a control signal to the gate of transistor 108 . The output of buffer 150 is connected to the input of buffer 152, which provides the BUCK_HS signal at its output. The BUCK_HS signal is applied to the gate of transistor 106 as a control signal.

SR latch 148, in addition to receiving the output of OR gate 142 at its R input, also receives a clock signal (CLK) at its S input. SR latch 148 generates PFM_BOOST from its Q output in response to the CLK signal and the output of OR gate 142 . The PFM_BOOST signal is provided to one input of OR gate 146 to generate the PFM_BOOST-d signal. While the gate of transistor 110 is connected to the PFM_BOOST-d signal, the PFM_BOOST-d signal is provided to the gate of transistor 112, and the BUCK_HS and BUCK_LS signals are provided to the gates of transistors 106, 108, respectively.

To achieve state [3], where inductor 114 is connected between node 103 and node 128, where switch 108 is on and switch 106 is off and switch 110 is on and switch 112 is off, a comparator 820 is provided which 820 has an inverting input connected to a reference voltage indicative of a level at which the current through inductor 114 has been discharged to zero as indicated by current sensor 119 . This level is denoted V _zerolimit . The non-inverting input of the comparator 820 is connected to the output of the current sensor 119 . The output provides a logic "high" signal when the current is indicated to be above zero and provides a logic "low" when the current falls to a value at or below zero. The output of comparator 820 is labeled _Vz and is connected to the other input of AND gate 822, one input of which is connected to the output of buffer 150, the output of which provides the BUCK_LS output. When the current is determined to be below zero, the output of AND gate 822 is low and turns off transistor 108 . Likewise, the output of comparator 820 is connected to one input of another input AND gate 822, which is an inverting input, and one input of which is connected to the output of OR gate 146, which receives the PFM_BOOST signal from the output of AND gate 822 , for driving the gate of transistor 110 . Therefore, when the output of comparator 820 goes low, the _Vz signal is input to the inverting input of AND gate 822 and will cause the output to go high, turning off transistor 110 . Since the output of OR gate 142 is high due to the voltage limit state, this will result in a tri-state condition of inductor 114 .

Referring now to FIG. 9, FIG. 9 illustrates the operation of the buck-boost converter and associated control circuitry of FIG. 9 in a buck-boost PFM boost mode of operation. For simplicity, node 122 is pulled to either the voltage on node 116 or the reference voltage on node 103, and is said to be at a logic "high" level when at the voltage level of node 116, and to be at a logic "high" level when at node 103 The voltage level is said to be at a logic "low" level. The signal at node 122 will be labeled SW1. Likewise, the signal at node 126 will be pulled up to the voltage level of output node 128 or pulled down to the voltage level of node 103 . Node 126 is labeled SW2, and when the level is at the level of node 128, it will be said to be at a logic "high" level, and when at the voltage level of node 103, it will be said to be at a logic "high" level. "Low" level. The levels of both nodes 122 and 126 are characterized as being in one of these two states or levels, it being understood that the state is actually a varying voltage level, i.e. the reference voltage at node 103, the input voltage level at the corresponding node level or output voltage level. Additionally, when all switches are off, nodes 122 and 126 will "float" at a tri-state level, sometimes referred to as a tri-state state.

At time T ₁ , the PFM_BOOST signal at the output of SR latch 148 goes from a logic "low" level to a logic "high" level in response to the clock signal going to a logic "high" level at the input of SR latch 148. "High" level. Switches 108 and 110 are turned off and switches 106, 112 are turned on. This causes switch node (SW1) 122 to go to a logic "high" level and switch node (SW2) 126 to go to a logic "low" level. This causes the inductor current _IL to increase from time _T1 to time _T2 . At time T ₂ , the PFM_BOOST signal will transition from a logic "high" level to a logic "low" level in response to the current limit signal transitioning to a logic "high" level. When switch 110 is on and switch 112 is off, switch node SW2 (node 126 ) is brought to a logic "high" level while switch node SW1 (node 122 ) is held at a logic "high" level. Inductor current _IL decreases from time _T2 to time _T3 . At time T ₃ , in response to the next clock signal, PFM_BOOST transitions from a logic “low” level to a logic “high” level, turning off transistor 110 and turning on transistor 112 , which is after the inductor current has reached zero crossing level before terminating the charge transfer operation and thus keeping the inductor current at a non-zero level. This causes switch node SW2 126 to go to a logic "low" level while keeping switch node SW1 122 "high". The inductor current increases from a non-zero level from time _T3 to time _T4 in the subsequent inductor charging operation.

At time _T4 , the current limit signal transitions the PFM_BOOST signal from a logic "high" level to a logic "low" level, turning on transistor 10 and turning off transistor 112, which terminates the charge phase and initiates the next charge transfer stage. This causes switch node SW2 126 to go to a logic "high" level while keeping switch node SW1 122 "high". Inductor current _IL decreases from time _T4 to time _T5 during the charge transfer operation. At time _T5 , in response to another rising clock edge, the PFM_BOOST signal transitions from a logic "high" to a logic "low" level, thereby driving switch node SW2 to a logic " low” level while maintaining switch node SW1 at a logic “high” level at a non-zero inductor current level. The inductor current increases from a non-zero level from time _T5 to time _T6 . In response to another current limit signal at time _T6 , the PFM_BOOST signal will transition from a logic "high" level to a logic "low" level, terminating the charge storage operation of the inductor. This also drives switch node SW2 "high" by turning on transistor 110 and turning off transistor 112 . The inductor current then decreases from time _T6 to time _T7 , _which occurs before the next clock edge.

At time T ₇ , the voltage limit signal transitions from a logic "low" level to a logic "high" level, so that the PFM_BOOST signal transitions to a logic "high" level before the next clock edge occurs. When the voltage limit signal goes "high" or when switch node SW2 126 remains "high" (which turns off transistor 106 and turns on transistor 108 ), this drives switch node SW1 122 to "low." The inductor current then decreases from time _T7 to time _T8 . Thus, the buck-boost PFM mode of operation in the circuit of FIG. 1 includes a charge phase 202 in the first mode of operation and a discharge phase 204 in the third mode of operation. However, these charge phases 202 and discharge phases 204 are separated by a pass phase 206 in the second mode of operation, which eliminates the four-switch switching state. As can be seen for switch node SW1 122 and switch node SW2 126 , which switch current throughout the PFM, a four-switch switching state does not occur.

The implementation of Figure 8 allows the pass phase to continue until the next clock signal is received at the input side of the SR latch 148 and the inductor current _IL falls below the PFM peak current limit or the voltage limit reaches a value 1.5% above the target value until. If the clock edge occurs and the inductor current is below the PFM peak current limit, the pass phase will follow the charge phase, as shown at time _T3 and time _T5 . If the voltage limit is reached during the pass phase, the discharge phase is allowed to discharge the inductor current to zero and end PFM operation, as shown at time _T7 .

Referring now to FIG. 10 , a state diagram illustrating the operation of the disclosed embodiment of FIGS. 8 and 9 is shown. In this embodiment, as previously described, the charging operation is sequenced through state [1] and state [2] until a voltage limit is reached, which characterizes the target voltage, at which point the energy of the inductor 114 is at state [3] is completely transferred during the discharge operation. Thus, boost operation begins at state [1] block 1001 and proceeds along path 1003 to state [2] at block 1005 . Until the voltage limit is reached, state [2] returns to state [1] at block 1001 via path 1007 . This operation will continue until the target voltage has reached V _LIMIT at the output voltage V _OUT . The state diagram then goes from state [2] of block 1015 to state [3] of block 1011 . Once it has been determined that _IL is equal to zero, ie at a zero crossing, the state diagram will flow along path 1013 to the fourth state of block 1015, state [4]. This state is the sleep state, where all switches are open and the system will remain in this state until the voltage V _OUT falls below the target voltage or the required voltage, at which point the state diagram will follow path 1017 back to state [1] of block 1001.

The state diagram of FIG. 10 is shown in the timing diagram of FIG. 11 . In this figure, it can be seen that the states are sequentially passed through state[1] and state[2] until at block 1001 the voltage limit V _LIMIT has occurred. At this point, the state diagram changes from state [2] to state [3] along path 1003 . This will increase the discharge rate to point 905, at which point a zero crossing of the inductor current has been detected and state [4] will then be entered. This will happen before the next clock edge. Understand however that if the voltage limit occurs close enough to a clock edge, it is possible that the zero crossing does not occur before the next clock edge, however, since V _LIMIT has been reached, this will be overwritten and switch S1 will remain open and switch S2 will remain closed until the zero crossing occurs, at which point the system will go to state [4].

Referring now to FIG. 12 , FIG. 12 shows an alternative embodiment of a buck-boost converter and control circuit with improved PFM operation in boost mode. Buck-boost converter 302 includes four switching transistors 306 , 308 , 310 and 312 and inductor 314 . An input voltage V _IN is applied at an input voltage node 316 . Current sensor 318 monitors the input current applied through input voltage node 316 and generates a signal _ISNS containing a voltage associated with the input current, and current sensor 319 monitors the output current through transistor 310 to voltage node 328 and generates a signal ISNS containing the voltage associated with The signal I _SNS of the current-correlated voltage is output. Transistor 306 has a source/drain path connected between node 320 and node 322 . Transistor 308 has a drain/source path connected between node 322 and reference node 317, which is connected to a reference voltage such as ground. Inductor 314 is connected between node 322 and node 326 . Transistor 310 has a source/drain path connected between output voltage node V _OUT 328 and node 326 . Transistor 312 has a drain/source path connected between node 326 and node 317 . Capacitor 330 is connected between node 328 and node 317 , and resistor 332 is connected in parallel with capacitor 330 between node 328 and node 317 . The gates of transistors 310, 312 are connected to receive the PFM_BOOST-d and PFM-Boost signals from the control circuit 304, respectively.

Control circuit 304 monitors the output voltage at node 328 using a resistor divider consisting of resistor 334 connected between node 328 and node 336 and resistor 338 connected between node 336 and ground. Node 336 provides the feedback voltage V _FB to the non-inverting input of voltage comparator 340 . The non-inverting input of voltage comparator 340 receives reference voltage V _REF . The output of voltage comparator 340 produces a voltage limited signal, which is provided to a first input of OR gate 342 .

Another input of the OR gate 342 is connected to receive the current limit signal V _iLIMIT from the output of the voltage comparator 344 . Voltage comparator 344 receives the _ISNS voltage signal from current sensor 318 at its non-inverting input and the V _LIMIT voltage limit signal from comparator 340 at its inverting input. The output of OR gate 342 is connected to the R input of SR latch 348 . The output of the OR gate 342 will generate a logic "high" value in response to the voltage limit signal or the current limit signal from the outputs of the comparators 340, 344, respectively, thereby turning to a logic "high" level. When the feedback voltage V _FB exceeds the reference voltage V _REF , the voltage limit signal turns to a logic "high" level. When the _ISNS signal from the current sensor 318 exceeds the Vi _LIMIT voltage, the current limit signal goes to a logic "high" level.

SR latch 348, in addition to receiving the output of OR gate 342 at its R input, also receives a clock signal (CLK) at its S input. In response to the CLK signal and the output of OR gate 342, SR latch 348 is connected to one input of OR gate 1226, the output of which generates the PFM_BOOST signal. The output of latch 348 is also connected to the input of buffer 346 to generate the PFM-BOOST-d signal. The Q output of SR latch 348 is input to the input of fixed rising edge delayer 350 . Fixed rising edge delayer 350 adds a delay to the PFM_BOOST signal and is input to one input of AND gate 1224 to provide a BUCK_LS signal at the output of AND gate 1224 , which is provided to the gate of transistor 308 . The output of delayer 350 is also provided as input to buffer 352 . The output of buffer 352 provides the BUCK_HS signal. The PFM_BOOST-d and PFM-Boost signals are provided to the gates of transistors 310, 312, respectively, while the BUCK HS signal is provided to the gate of transistor 306.

The control circuit 304 inserts a pass-through phase after the charge phase, which will last for a "fixed" period of time, followed by a discharge phase. This approach, although not eliminating four-switch switching states like the implementation of Figure 9, greatly reduces the number of four-switch switching states, which increases the overall efficiency of the buck-boost converter.

Referring further to FIG. 12 , when the current through the inductor 314 is at zero value in state [3], it is necessary to turn off the transistor 308 and the transistor 310 . The comparator 1220 has an inverting input connected to the limit voltage V _zerolimit and a non-inverting input connected to the output of the current sensor 119 . When it is determined that the inductor current has become below the zero limit, the output of comparator 1220 will go low. The output of comparator 1220 is denoted as V _z , which is connected to another input of AND gate 1224 . When _Vz goes low, the output of AND gate 1224 will go low, turning off transistor 308. Likewise, OR gate 1226 has an inverting input V _z connected to the output of comparator 1220 . Therefore, when _Vz falls, the output of OR gate 1226 will be high, which will turn off transistor 310, the P-channel transistor. Therefore, when the zero current limit is exceeded and the voltage limit has been exceeded, the output of comparator 1220 being low and the output of comparator 340 being high will result in a tri-state state of all switches. In addition, exceeding the voltage limit will also keep the SR latch 348 in a low output state, so rising clock edges will not reset on the SR latch 348 .

Referring now to FIG. 13 , FIG. 13 illustrates the operation of the buck-boost converter and control circuit of FIG. 12 including a fixed pass operation phase after each charging phase. In response to the clock edge at time _T1 , the PFM_BOOST and PFM_Boost-d signals transition from a logic "low" level to a logic "high" level, turning off switch 310 and turning on transistor switch 312 . When switch 306 is on and switch 308 is off, this causes the voltage at switch node SW1 (node 322) to go to a logic "high" level, and the voltage at switch node SW2 (node 326) responds to transistor 310 turning off and transistor 312 turns on to a logic "low" level. Inductor current _IL begins to increase from time _T1 to time _T2 . At time _T2 , in response to the logic "high" level of the current limit signal from the output of voltage comparator 344, since switch 310 is on and switch 312 is off, the voltage at switch node SW2 (node 326) changes from a logic "low" to " level to logic "high" level. This initiates a pass cycle from time _T2 to time _T3 when the inductor current _IL decreases and charge is transferred to the load. The period from time T ₂ to time T ₃ is a definite time established by fixed rising edge delayer 350 . After the timeout is determined at time _T3 , the PFM_BOOST signal transitions from a logic "high" to a logic "low" level, which causes the voltage at node SW1 (node 322) to change from logic "High" to a logic "low" level. Inductor current _IL goes through a discharge phase from time _T3 to time _T4 until zero crossing occurs.

At time T ₄ , in response to a rising clock edge, PFM_BOOST transitions from a logic “low” level to a logic “high” level, which turns off switches 308 , 310 and turns on switches 306 , 312 . This causes the voltage at switch node SW1 (node 322) to transition from a logic "low" level to a logic "high" level and the voltage at switch node SW2 (node 326) to transition from a logic "high" to a logic "low" level. This results in four switches switching states. The inductor current goes through another charging phase from time _T4 to time _T5 . At time _T5 , the PFM_BOOST signal transitions from a logic "high" level to a logic "low" level, thereby causing the voltage at switch node SW2 (node 326) to change from a logic "low" when switch 310 is on and switch 312 is off. level to logic "high" level. This initiates the pass-through phase from time _T5 to time _T6 when the inductor current _IL decreases.

The passing phase is based on the output of the fixed rising edge delayer 350 corresponding to the determined time from time _T5 to time _T6 . After a determined time from time _T5 to time _T6 , the voltage at node SW1 will transition from a logic "high" level to a logic "low" level in response to switch 306 being turned off and switch 308 being turned on, thereby at time From _T6 to time _T7 , the discharge phase is initiated. At time _T7 , another rising clock edge transitions the PFM_BOOST signal from a logic "low" level to a logic "high" level, causing transistors 310, 312 to turn off and causing the voltage at switch node SW1 (node 322) to change from a logic "low" level to a logic "high" level. The transition from a low level to a logic "high" level simultaneously causes the voltage at switch node SW2 (node 326 ) to transition from a logic "high" level to a logic "low" level. This initiates the next charge cycle, and the four-switch transition occurs at time T ₇ .

The circuit of FIG. 12 includes a number of charge phases 402 in a first mode of operation, a discharge phase 404 in a third mode of operation, the charge phases 402 and discharge phases 404 are interconnected by a fixed length pass phase 408 in a second mode of operation. separated. As can be seen from the switching signal, a reduced number of four switch switching states occurs at point 410 in the switching cycle of the switching transistor. This improves the efficiency of the circuit operation of the buck-boost converter, although not as much as the example depicted in FIG. 8 .

Referring now to FIG. 14 , there is shown a state diagram describing the operation of FIGS. 12 and 13 and embodiments disclosed herein. The state diagram in Figure 14 begins at state block 1401 in state [1] and then flows along path 1405 to block 1403 in state [2]. However, as previously mentioned, after a predetermined time delay, the state will change along path 1407 from state [2] to state [3] at block 1406 . On the next clock cycle, the state will change along path 1409 from state [3] to state [4] at block 1411 . Status will continue to flow along paths 1405, 1407 and 1409 until the voltage limit is reached. At this point, the state will remain at state [3] of block 1406 until the current to the inductor equals zero value, ie crosses zero. At this point, the state will change from state [3] at 1406, where switch S2 is closed and S1 is open and S3 is closed and S4 is open, until this occurs. At this point, the state diagram will change along path 1413 to state [4] at block 1411 . The system will remain in this state until the voltage falls below the V _LIMIT target value, at which point the state will change along path 1415 to state [1] at block 1401 .

The timing flow of the state diagram of FIG. 14 is shown in FIG. 15 . In this operation, it can be seen that state [2] is maintained for a predetermined amount of time T _D . Thus, a clock edge starts at state [1], and an inductor current I _L equal to the current limit I _LIMIT causes a change from state [1] to state [2]. At the end of the fixed delay, the system changes to state [3]. During operation where the voltage has not yet reached the voltage limit V _LIMIT , the next charge cycle will take place on the next clock cycle, i.e. entering state [1] again. This is flow along paths 1405, 1407 and 1409. However, once V _LIMIT is reached, state [3] is forced to stay in the existing state until the current charging the inductor has decreased to zero value, even if the next clock edge occurs during this time. System mode then transitions to state [4] at point 1501 .

Referring now to FIG. 16, a top level block diagram of buck operation is shown. As described herein, buck-boost controller 105 consists of two operations, a boost operation and a buck operation. Therefore, a control section associated with the boost operation, that is, the boost controller 104 described above for the control of the boost operation is provided. This will also provide a buck controller 1602 operable to control the buck operation. In the step-down operation, the H-bridge 101 is controlled such that the step-down side of the H-bridge 101 is controlled to alternately switch S1 and S2 to the closed or open position according to the step-down operation, and On the pressure side, switch S4 will remain open and switch S3 will remain closed. For standard buck operation, inductor 114 is charged by connecting the buck side of inductor 114 to V _IN through switch S ₁ . Once charged, the charge is transferred by opening switch S1 and closing switch S2 and connecting the buck side of inductor 114 to a reference voltage or ground. Charge operation increases the inductor current to a predetermined current limit and then switches to discharge or charge transfer operation to decrease the inductor current to zero. This is done according to PFM operation.

Referring further to FIG. 16A , a timing diagram of the operation of buck controller 1602 is shown in FIG. 16A . A fixed frequency is provided by the clock circuit 107, where a clock edge will initiate a PFM charging operation to close switch S1 and open switch S2, keep switch S4 open and keep switch S3 closed. This charging operation will continue until a point in time 1610 at which the maximum current limit has been reached. This switches operation to a discharge or transfer mode, where energy is transferred from the inductor 114 to the load. This transfer will continue until the current through the inductor is zero, as determined by buck controller 1602 by sensing the current through transistor 310 with current sensor 119 . At this point, point 1612, switches S1-S4 will be in tri-state mode and all switches will be open. On the next clock edge 1614, the next charge operation will take place. This will continue until it is determined that the voltage limit has been reached, as indicated by voltage limit signal 1616 . At this point, what will happen is that the switch will remain in tri-state mode and the next clock edge will not initiate another charging operation. If the voltage limit signal 1616 occurs before the current through the inductor 114 has been reduced to zero, tri-state mode will be delayed until this occurs, after which all switches will be in tri-state mode.

Referring further to Figure 16, note that a comparator 1618 with hysteresis is provided to compare the input and output voltages. This determines whether the boost mode has moved into the transition buck or boost region, as previously described in connection with FIG. 2A . Hysteresis will allow a determination of whether the input voltage is less than the output voltage by dV ₁ or greater than V _OUT by a value dV ₂ . If so, the boost mode will switch to buck mode, or the buck mode will switch to boost mode. Boost mode will remain until the input voltage is greater than the output voltage by _dV2 , and buck mode will remain in buck mode until _dV1 decreases below the output voltage.

Voltage regulators and associated circuits according to embodiments of the present disclosure may be embodied in many different types of electronic devices and systems, such as computers, cellular phones, personal digital assistants, and industrial systems and devices. More specifically, some applications include, but are not limited to, points of CPU power regulators, chip regulators, load power regulators, and memory regulators. FIG. 17 is a block diagram of an electronic/electrical system or functional device 1702 . A functional device 1702 is a device that requires a regulated voltage at a specific and set voltage, which is defined by the operating parameters of the device 1702 . For purposes of illustration, device 1702 includes certain operational blocks, such as CPU 1712, memory 1716, clock or timing circuit 1714, that work together to provide an integrated specific device. This can be implemented entirely in silicon on an integrated circuit or formed as discrete devices. A data bus 1722 is provided to allow communication between components within the device 1702 .

To provide power to the device, an external voltage V _IN is input to a buck-boost regulator 1701 operating either in buck mode or in low ripple PFM boost mode. The input voltage can operate over a much larger range than the device operating voltage, so that the regulator 1701 must accommodate voltages ranging from voltages below the operating voltage to voltages above the operating voltage. The operating voltage is labeled V _OUT and is shown powering CPU 1712 and clock 1714 . In the figure it also powers the USB driver 1718 which interfaces with the external USB device 1704 . For this operation, power from regulator 1701 is used to power external USB device 1704 . Additionally, other external devices may be interfaced with device 1702, such as input devices 1706, such as keyboards and scanners, and output devices 1708, such as LCD displays. Additionally, external storage 1710 can be in the form of a flash drive, hard drive, DVD, or the like. These external storages 1710 are interfaced with a data bus 1722 . I/O 1720 is provided here to interface between components on device 1702 and input/output devices to provide various drivers and the like. All external devices can interface with USB drive 1718 as long as they are USB-interfaceable devices. Regulator 1701 utilizes the previously described PFM boost circuit for improved efficiency and lower ripple.

Those skilled in the art will understand after reviewing the present disclosure that such a system and method for high efficiency PWM control of a buck-boost converter provides a more efficiently operating buck-boost converter. It should be understood that the drawings and detailed description herein are to be regarded as illustrative rather than restrictive and are not intended to be limited to the particular forms and examples disclosed. On the contrary, any further modifications, changes, rearrangements, substitutions, substitutions, designs apparent to those of ordinary skill in the art are included without departing from the spirit and scope of the present invention as defined by the appended claims Options and Examples. Therefore, it is intended that the appended claims be construed to cover all such further modifications, changes, rearrangements, substitutions, substitutions, design choices, and embodiments.

Claims (24)

1. DC-DC transducer comprises:

Input terminal is used for receiving input voltage from the input voltage source that is arranged on input voltage level;

Lead-out terminal offers the load that is connected in described lead-out terminal for the output voltage that will be in output-voltage levels, and described output-voltage levels is different from described input voltage level;

Charge storage cell is used for receiving and stored charge from the input voltage source on its input side via input terminal, and the electric charge of at least a portion storage is transferred to described load from its outlet side; And

Control system, be used at least three duplication stages controls charge storage being shifted so that output-voltage levels meets the requirements of level from described charge storage cell to described charge storage cell with electric charge, described three phases comprise for will from the charge storage of described input terminal to charge storage stage of described charge storage cell, be used for the only part of stored charge is transferred to the first charge transfer phase of described load and the second charge transfer phase that will basic all electric charges be transferred to described load from described charge storage cell.

2. transducer as claimed in claim 1 is characterized in that, described charge storage cell comprises inductor.

3. transducer as claimed in claim 1, it is characterized in that, also comprise the clock circuit with fixed frequency, and wherein said charge storage stage and described the first charge transfer phase are subjected to described control system to control to occur in the single clock cycle, and the end in described the first charge storage stage occurs in described clock cycle when finishing.

4. transducer as claimed in claim 3 is characterized in that, described the second charge transfer phase is independent of the external status of the described output voltage of clock ground response and occurs.

5. transducer as claimed in claim 4 is characterized in that, described external status determines that by comparator described comparator determines that described output voltage equals or exceed the level that requires of described output voltage.

6. transducer as claimed in claim 4, it is characterized in that, the operation of described control system starts from the described charging stage, within the ensuing clock cycle, be in afterwards the first transition phase, until described external status occurs, therefore when the last end cycle of described clock, in described charge storage cell, there is the non-zero energy level, and the charging stage of described current cycle will charge to described charge storage cell from described non-zero energy level, until described external condition occurs.

7. transducer as claimed in claim 3, it is characterized in that, the described charge storage stage with charge storage in described charge storage cell, until wherein stored the energy of scheduled volume, the time span that reaches thus the energy of scheduled volume will correspondingly change because becoming in the time span of the amount that is stored in initial energy wherein when described charge transfer phase begins and described the first charge transfer phase.

8. transducer as claimed in claim 7, it is characterized in that, described charge storage cell comprises inductor, and the energy of described scheduled volume is limited by the current limit that flows through the electric current of described inductor in the process of described charge storage stage to described inductor charging.

9. transducer as claimed in claim 1 is characterized in that, the level that requires of described output voltage is higher than described input voltage so that the boost DC-DC conversion operations to be provided.

10. transducer as claimed in claim 1 is characterized in that, described charge storage cell comprises inductor, and described control system comprises:

Switch bridge, described switch bridge has the first and second switching nodes, each switching node is connected in the relative both sides of described inductor, it has: one group of first and second input switch is used for described the first switching node is connected in described input terminal and is connected in reference voltage by described the second input switch by described the first input switch; And one group of first and second output switch, be used for described second switch node is connected in described lead-out terminal and is connected in reference voltage by described the second output switch by described the first output switch; And

On-off controller, described on-off controller is controlled described the first and second input switches and the first and second output switchs described inductor is connected between described input terminal and the described reference voltage, and at described the first charge transfer phase described inductor is connected between described input terminal and the lead-out terminal, and at described the second charge transfer phase described inductor is connected between described reference voltage and the described lead-out terminal.

11. a buck-boost DC-DC transducer comprises:

Input terminal, described input terminal is connected in the input voltage source that is operated under the input voltage level;

Lead-out terminal, described lead-out terminal is connected in load;

Datum node, described datum node is arranged on reference voltage level;

The buck-boost change-over circuit comprises:

Inductor,

Step-down switching section is used for electric charge is transferred to described inductor and electric charge is transferred to load on the described lead-out terminal at the step-down conversion operations subsequently, and

Boosted switch section is used for electric charge is transferred to described inductor and electric charge is transferred to load on the described lead-out terminal in the boost conversion operation subsequently; And

The buck-boost controller is used for the described at least boosted switch section of control so that it is operated under pulse frequency modulated (PFM) the boost operations pattern, and described controller comprises:

Operate in the clock under the fixed frequency; And

The stage control device, be used for controlling the charging stage that described the first and second output switchs are initiated to operate in the clock edge place, thereby described inductor is connected between described input terminal and the described reference voltage node so that described inductor is charged to predetermined charging level, and operate in subsequently the first charge transfer phase described inductor is connected between described input terminal and the described lead-out terminal, so from described inductor and described input terminal electric charge is transferred to described lead-out terminal, until next clock edge occurs, wherein said inductor will be in the energy level of non-zero storage.

12. transducer as claimed in claim 11, it is characterized in that, described buck-boost controller comprises comparator, be used for the reference voltage of the voltage level on the described lead-out terminal and requirement is compared, and when the voltage level on the described lead-out terminal equals or exceeds described reference voltage, described stage control device makes described boosted switch section and described step-down switching section operate in the second charge transfer phase so that described inductor is connected between described datum node and the described lead-out terminal, thereby basic all energy that will be stored in the inductor are transferred to described lead-out terminal so that energy wherein is reduced to basic null value.

13. transducer as claimed in claim 12, it is characterized in that described buck-boost controller is controlled described boosted switch section and described step-down switching section when described the second charge transfer phase finishes described inductor is disconnected from described input and output terminal and described datum node.

14. transducer as claimed in claim 11 is characterized in that, described buck-boost controller is controlled described step-down switching section so that it operates under the PFM reduced pressure operation pattern.

15. transducer as claimed in claim 14, it is characterized in that, also comprise pattern comparator, also when two voltages are in the predetermined voltage, between reduced pressure operation pattern and boost operations pattern, switch in order to the voltage level on more described input terminal and the lead-out terminal.

16. transducer as claimed in claim 11, it is characterized in that described buck-boost controller comprises that further the current limitation detector enters the current flowing of described inductor and will stage from the described charging stage change to described the first charge transfer phase when detecting predetermined inductance device electric current in the described charging stage with detection.

17. a boost pressure controller comprises:

Inductor,

Charging circuit is used for from input voltage source described inductor being charged to predetermined current level;

Charge transfer circuit is used for energy is transferred to load from described inductor and voltage source;

Clock is used to charging/transfer operation to limit a fixing repetition period; And

Controller, be used for controlling described charging circuit when period demand begins, described inductor is charged to described predetermined current level from the initial current level, subsequently by controlling described charge transfer circuit so that remaining cycle portions is transferred the energy to less than zero inductance device current level.

18. the method for the operation of a controlled hypotension/boost pressure controller comprises:

Output voltage or the output through regulating in response to the input voltage that receives in input and the generation of a plurality of control signal;

Monitor described output voltage through regulating; And

Respond described output voltage and produce a plurality of control signals, wherein said a plurality of control signals comprise: the first operator scheme, and the charging stage of described the first operator scheme control described falling/boost pressure controller charges to charge storage cell with the input voltage from input; What the second operator scheme, described the second operator scheme were controlled described buck/boost adjuster passes through the stage not only the electric charge of storage was transferred to described output but also electric charge is transferred to described output from described input from described charge storage cell; And the 3rd operator scheme, described the 3rd operator scheme is controlled the discharge regime of described buck/boost adjuster fully the electric charge of storing in the described charge storage cell is transferred to described output;

Wherein said a plurality of control signal is controlled described buck/boost adjuster to eliminate the appearance of four switching over states.

19. method as claimed in claim 18 is characterized in that, described generation also comprises:

Produce pressure limiting signal, the described pressure limiting signal indication when output voltage through adjusting exceeds reference voltage;

Produce the current limliting signal, when described current limliting signal designation input current to described charge storage cell during the charging stage of described buck/boost voltage regulator exceeds a predetermined current limliting reference signal;

Produce the first of a plurality of control signals to control a pair of boosted switch transistor in a plurality of switching transistors, described a pair of boosted switch transistor switched to a side of described charge storage cell reference voltage and passes through the stage and discharge regime switches to output node related with described buck/boost adjuster in the charging stage, and described buck/boost regulator response is in described pressure limiting reference signal, the side with described charge storage cell switches to reference voltage and switches to output node described by stage and discharge regime in the charging stage for current limliting signal and clock signal; And

Produce second portion in a plurality of control signals with a pair of step-down switching transistor in control described a plurality of switching transistors related with described buck/boost adjuster, the described pressure limiting signal of described a pair of step-down switching transient response is connected to the opposite side of described charge storage cell reference voltage or is connected to described input node described by the stage at described discharge regime.

20. method as claimed in claim 17 is characterized in that, also comprises:

Response is at input voltage and the output voltage of a plurality of control signal generation through regulating of described buck/boost adjuster side; And

According to described a plurality of control signals described buck/boost adjuster is operated under a kind of pattern in described first, second or the 3rd operator scheme.

21. method as claimed in claim 19 is characterized in that, described operation also comprises:

A plurality of switching transistors in the described buck/boost adjuster of response clock signal and current limliting signal controlling to be allowing the charging stage under the first operator scheme, thereby inductor is charged to the electric current corresponding with the current limliting signal; And

Respond a plurality of switching transistors in the described buck/boost adjuster of described clock signal and current limliting signal controlling to allow to be in passing through the stage under the second operator scheme, the energy that not only will be stored in the described inductor is transferred to described output node but also electric current is transferred to described output from described input node, thereby makes in the described inductor energy of only part storage be transferred to described output.

22. method as claimed in claim 20, it is characterized in that, described operation comprises that also responding pressure limiting signal controls described a plurality of switching transistor to allow the discharge regime under the 3rd operator scheme, be transferred to described output with the energy that fully will be stored in the described inductor, wherein do not have energy to be transferred to described output from described input node.

23. a system comprises:

The buck/boost voltage regulator is used for response and is exporting the output voltage that produces through regulating in input voltage and drive control signal that the input node receives, and described buck/boost voltage regulator comprises a plurality of switching transistors;

Control circuit, be used for monitoring and produce a plurality of drive control signal through the output voltage of adjusting and in response to this, the operation that wherein said control circuit is controlled described a plurality of switching transistors is to allow charging stage under the first operator scheme so that electric charge is stored to the inductor from described input node, and allow under the second operator scheme pass through the stage will be only the electric charge that is stored in the described inductor of a part be transferred to described output node and electric charge be transferred to described output node from described input node, and allow discharge regime under the 3rd operator scheme, the electric charge in the wherein said inductor to be completely transferred to output node in the described buck/boost voltage regulator to eliminate the appearance of four switching over states; And

Load, described load coupling is to the output of described buck/boost voltage regulator.

24. system as claimed in claim 23 is characterized in that, described load is to select from the group that comprises processor, memory, input equipment, output equipment and memory device.

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