CN102832939B - A kind of ADC transducer - Google Patents

Abstract

The invention discloses an ADC converter, which relates to the technical field of parallel analog-to-digital converters, and includes a resistance voltage divider network, a time domain comparator, a bubble elimination circuit and an encoder. The VN input terminal of the time domain comparator is connected to an external The sampling voltage V _Sample is connected, the VP input terminal of the time domain comparator is connected with the reference voltage V _REF ; the V _bias input terminal of the time domain comparator is connected with the external reference voltage input signal V _BIAS ; the En_Cal input terminal of the time domain comparator is connected with the calibration The enable En_Cal is connected; the comp_out output terminal of the time domain comparator is connected with the input terminal of the bubble elimination circuit and the encoder. The invention adopts the digital adjustment technology to eliminate the direct current offset voltage of the time domain comparator, thus improving the effect of the direct current offset voltage on FLASH? The impact of ADC accuracy further makes up for the shortcomings of traditional DC offset adjustment technology.

Description

An ADC converter

technical field

The invention relates to the technical field of parallel analog-to-digital converters, in particular to an ADC converter using a DC offset voltage time-domain elimination technology comparator.

Background technique

Analog-to-digital converters are a crucial part of mixed-signal circuit systems, and can be divided into various types according to different sampling methods. Parallel ADC (FLASHADC) has the advantages of high speed and simple circuit structure, and has a wide range of applications in the field of high-speed sampling mixed-signal systems, such as high-speed scanning interface circuits, high-performance digital communication systems, measurement and control, and instrumentation.

The existing FLASHADC structure includes a resistor divider network, A comparator (N is the number of ADC digits), a bubble elimination circuit and an encoder. The high-precision sampling circuit has high requirements on the precision of the ADC, and the precision of the FLASHA ADC is determined by the precision of the comparator. The DC offset voltage of the comparator has a great influence on the accuracy of the comparator.

With the advancement of the manufacturing process, the precision of the integrated circuit manufacturing process has also been further improved, but the uncertainty of the manufacturing process still exists. This uncertainty leads to differences in the manufacture of devices that are exactly the same in design. This mismatch Just a mismatch. This adaptation of the same device will generate a DC offset of the device, and when the DC offset reaches a certain level, it will seriously affect the accuracy of the comparator. Loss of accuracy degrades the performance of the ADC, so electrical techniques are used to eliminate this DC offset produced during the manufacturing process when designing the ADC.

At present, the main method of DC offset voltage elimination is the method of sampling and storing DC offset voltage, and the commonly used technology is automatic zero calibration technology. Its working principle is to store the output result of the comparator when the differential input voltage is zero on the capacitor connected in series with the comparator output or to store the DC offset voltage of the comparator when the differential input voltage is zero on the capacitor connected in series with the comparator input .

To sum up, the traditional DC offset cancellation technology has the following disadvantages:

1. N-bit FLASHADC needs If each comparator adopts a capacitor storage method to eliminate the DC offset voltage, the chip area will increase.

2. Traditional DC offset elimination technology The accuracy of offset voltage elimination depends on the parameters of the comparator, and the adjustment accuracy is not as accurate as the digital adjustment method adopted in the present invention.

Contents of the invention

The technical problem to be solved by the present invention is to provide an ADC converter, which uses digital adjustment technology to eliminate the DC offset voltage of the time-domain comparator, thereby improving the impact of the DC offset voltage on the accuracy of the FLASHADC, and further compensating for the traditional DC offset Insufficient adjustment technology.

The present invention is achieved by adopting the following technical solutions:

An ADC converter, comprising a resistor divider network, a time-domain comparator, a bubble elimination circuit and an encoder, is characterized in that: the VN input terminal of the time-domain comparator is connected with an external sampling voltage V _Sample , and the time-domain comparison The VP input terminal of the time domain comparator is connected with the reference voltage V _REF ; the V _bias input terminal of the time domain comparator is connected with the external reference voltage input signal V _BIAS ; the En_Cal input terminal of the time domain comparator is connected with the calibration enable EN_Cal; the time domain comparator The comp_out output terminal is connected with the input terminal of the bubble elimination circuit and the encoder.

The time-domain comparator is composed of 19 PMOS transistors, 4 NMOS transistors, 2 AND gates, 1 NOR gate, 2 latch encoders, 2 multiplexers and 14 delay units; The time-domain comparator processes the sampling voltage V _Sample , the reference voltage V _REF , the sampling signal Strobe, and the calibration enable signal EN_Cal to generate an output signal, which is output from the comp_out output terminal.

The 19 PMOS tubes are respectively MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, MP16, MP17, MP18 and MB; The NMOS tubes are MN1, MN2, MN3 and MN4 respectively; the two AND gates are AND gate AND1 and AND gate AND2 respectively; the two latch encoders are latch encoder DC1 and latch encoder DC2 respectively; two multi-channel The multiplexers are multiplexer MUX1 and multiplexer MUX2; the 14 delay units are DP1, DP2, DP3, DP4, DP5, DP6, DP7, DN1, DN2, DN3, DN4, DN5, DN6 and DN7.

The source of the PMOS transistor MB is connected to the power supply voltage VDD, the gate of the PMOS transistor is connected to the external bias voltage signal V _BIAS , and the drain of the PMOS transistor MB is at the same point as the sources of the PMOS transistors MP1 and MP2; the PMOS transistor MP1 The gate of MP2 is connected through switch S1, the gate of PMOS transistor MP1 is connected with external analog input voltage V _REF , the gate of PMOS transistor MP2 is connected with external analog input voltage VN through switch S0; the drain of PMOS transistor MP1 is connected with the drain of NMOS transistor MN1 The drain, the gate of MN1, and the gate of MN4 are at the same point, and the drain of the PMOS transistor MP2 is at the same point as the drain of the NMOS transistor MN2, the gate of MN2, and the gate of MN3; the NMOS transistors MN1, MN2, MN3, and MN4 The source of MN3 is at the same point and is connected to the power ground VSS; the drain of MN3 is at the same point as the drain of MP3 and the gates of MP3, MP4, MP5, MP6, MP7, MP8, MP9 and MP10; the drain of MN4 is at the same point as that of MP11 The drains and the gates of MP11 , MP12 , MP13 , MP14 , MP15 , MP16 , MP17 and MP18 are in common.

The drains of the PMOS transistors MP4, MP5, MP6, MP7, MP8, MP9 and MP10 are respectively connected to the power terminals of the delay units DP1, DP2, DP3, DP4, DP5, DP6 and DP7, and the PMOS transistors MP12, MP13, MP14, The drains of MP15, MP16, MP17 and MP18 are respectively connected to the power terminals of the delay units DN1, DN2, DN3, DN4, DN5, DN6 and DN7; the delay units DP1, DP2, DP3, DP4, DP5, DP6 and DP7 are connected first to form Delay chain, the input terminal of DP1 is connected to the external digital input signal Strobe to generate the encoded output signal DP[7:1] and connected to the data input terminal of the latch encoder DC1; delay units DN1, DN2, DN3, DN4, DN5, DN6 It is connected with the first bit of DN7 to form a delay chain. The input terminal of DN1 is connected to the sampling signal Strobe to generate the encoded output signal DN[7:1] and connected to the data input terminal of the latch encoder DC2; delay units DP1, DP2, DP3, DP4, The output terminals of DP5, DP6 and DP7 are connected with the signal input terminals of the multiplexer MUX1, and the output terminals of the delay units DN1, DN2, DN3, DN4, DN5, DN6 and DN7 are connected with the signal input terminals of the multiplexer MUX2 Connected; the output signal N1[2:0] of the latch encoder DC1 is connected to the selection terminal of the multiplexer MUX1, and the output signal N2[2:0] of the latch encoder DC2 is connected to the selection terminal of the multiplexer MUX2 Select end connected.

The output signal MUX1_0 of the multiplexer MUX1 is connected to the CLK of the D flip-flop DFF1, the output signal MUX2_0 of the multiplexer MUX2 is connected to the CLK of the D flip-flop DFF2, and the data input terminals D of the D flip-flops DFF1 and DFF2 are connected to The sampling signal Strobe is connected; the output signals Q1 and Q2 of the D flip-flops DFF1 and DFF2 are respectively connected with the calibration enable EN_Cal through the AND gates AND1 and AND2 to generate signals E1 and E2, and are respectively connected with the latch encoder DC1 and the latch encoder DC2 The enable control input is connected; the Q2 signal and the calibration enable EN_Cal pass through the NOR gate to generate the output result of the comparator and output it through the comp_out output.

Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

1, in the present invention, adopt " the VN input terminal of described time domain comparator is connected with sampling voltage V _Sample , the VP input terminal of time domain comparator is connected with reference voltage V _REF ; The V _bias input terminal of time domain comparator is connected with The external reference voltage input signal V _BIAS is connected; the En_Cal input terminal of the time domain comparator is connected with the calibration enable EN_Cal; the comp_out output terminal of the time domain comparator is connected with the input terminal of the bubble elimination circuit and the encoder” such a time domain The comparator, the connection between the time domain comparator and the resistor divider network and the bubble elimination circuit and the encoder has opened up a new DC offset elimination technology, which improves the conversion accuracy of FALSHADC and saves more than the traditional DC offset elimination technology. The area occupied by the capacitor.

2. In the present invention, the "time domain comparator" used consists of 19 PMOS transistors, 4 NMOS transistors, 2 AND gates, 1 NOR gate, 2 latch encoders, and 2 multiplexers It is composed of 14 delay units; sampling voltage V _Sample , reference voltage V _REF and sampling signal Strobe, calibration enable EN_Cal are processed, and an output signal is generated, which is output from the comp_out output terminal. This structure has been verified (see the manual Figure 1 and Figure 2), all-digital encoding can be completed with a mature digital process, making the timing more accurate. The simulation results show that: when the sampling clock clk is 2.5MHz, when the FLASHADC has a 6-bit resolution and the differential input range is 0.64v, the minimum LSB can reach 10mv. When the sampling clock frequency is reduced, the LSB can be reduced to improve the accuracy of the ADC.

Description of drawings

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments of the description, wherein:

Figure 1 is an overall structure diagram of a FLASHADC that uses time domain to eliminate offset voltage.

Figure 2 is a schematic diagram of the overall working timing relationship of FLASHADC.

Figure 3 is a structural diagram of a time-domain comparator.

detailed description

Example 1

As we all know, the comparison result of the time-domain comparator is determined according to the phase relationship between the two output pulses, and the DC offset voltage will affect the phase difference between the two pulse signals. Therefore, we can use digital adjustment technology to correct the phase difference to achieve the purpose of eliminating the offset voltage.

The technical method of digital adjustment is to correct the phase of two pulses by changing the number of delay units. Since the digital adjustment technology is to correct the number of delay units, limited by the correction accuracy, the DC offset voltage cannot be completely eliminated, but the accuracy of the delay unit can be improved to improve the accuracy of DC offset voltage elimination.

To this end, we propose the following better implementation method to eliminate the DC offset voltage and improve the conversion accuracy of the ADC converter:

A kind of ADC converter, comprises resistance divider network, time domain comparator, air bubble elimination circuit and encoder, the VN input end of described time domain comparator is connected with sampling voltage V _Sample , the VP input end of time domain comparator is connected with The reference voltage V _REF is connected; the V _bias input terminal of the time domain comparator is connected with the external reference voltage input signal V _BIAS ; the En_Cal input terminal of the time domain comparator is connected with the calibration enable En_Cal; the comp_out output terminal of the time domain comparator is connected with all The bubble elimination circuit is connected with the input end of the encoder.

The working mode of the DLASHADC involved in the above-mentioned converter is determined by the control signal, and its working steps are divided into two parts: one step is the DC offset voltage elimination stage, and the second step is ADC sampling and encoding. In the first working stage, the DC offset voltage will be stored in the delay unit in the form of time delay information under the action of the differential voltage phase difference conversion circuit and the time domain offset voltage elimination circuit. At this time, other parts of FLASHADC and the comparison result output circuit of the time domain comparator are not working. When the circuit works in the sampling conversion step, it performs analog-to-digital conversion on the sampled analog input voltage and outputs it in the form of binary code. At this time, the pulse used to generate the comparison result of the time-domain comparator has been phase-adjusted, which eliminates the influence of the DC offset voltage on the output result.

Example 2

Below is the best implementation mode of the present invention, detailed description is as follows in conjunction with accompanying drawing of description:

Figure 1 shows the structure diagram of FLASHADC using time-domain elimination offset voltage technology, including time-domain comparator array, bubble elimination circuit and encoder.

Figure 2 shows a schematic diagram of the overall working timing relationship of FLASHADC. When EN_Cal is equal to 1, FLASHADC works in the DC offset voltage elimination stage, and when EN_Cal is equal to 0, FLASHADC works in the sampling encoding stage.

Fig. 3 is the circuit diagram of the time domain comparator. A detailed description will be given below in conjunction with the schematic diagram of the overall timing signal in FIG. 2 .

When EN_Cal is equal to 1, the differential input voltage is 0, the DC offset voltage V _offset is sampled, and the sampling signal Strobe is input at the same time, and the phase adjustment module inside the time domain comparator performs phase adjustment on the Strobe pulse signal. During the period when EN_Cal is equal to 1, the output level of its comp_out remains unchanged. When EN_Cal is equal to 0, the sampling voltage V _Sample is input, and the sampling signal Strobe for generating the comparison result is input at the same time. The comparison result generated by the time domain comparator is output to the bubble elimination and encoder circuit through comp_out for processing.

The relationship between the delay unit delay time Δt and the differential input voltage in the time domain comparator is Δt=N*Δv*Gm*K, N is the number of delay units, G _m is the differential input current gain, and K is the delay Unit gain, where K=△T / △I. Due to the uncertainty of the manufacturing process, this uncertainty leads to differences in the manufacture of devices that are exactly the same in design, so there is a DC offset voltage V _offset between the gates of MP1 and MP2. The existence of the DC offset voltage makes the delay time of the delay unit DN and DP different. After the input sampling signal Strobe, the phase difference of the pulses on the two delay chains represents the magnitude of the DC offset voltage, that is, the DC offset voltage in the time domain is equal to that in the delay chain. Stored in the form of pulse phase difference.

When EN_Cal is equal to 1, the switch S1 is closed, the switch S0 is opened, the gates of the PMOS transistors MP1 and MP2 are short-circuited, that is, the differential input voltage is 0, and there is a DC offset voltage V _offset between the gates of MP1 and MP2. The value of DP[7:1] and DN[7:1] is the original value 0000000, the value of Q1 and Q2 is 1, the input sampling signal Strobe, the existence of the delay unit makes the value of DP[7:1] and DN[7:1] Cycle from 0000000 to 1111111. DP[7:1] and DN[7:1] are coded by latch encoders DC1 and DC2 respectively, N1[2:0] and N2[2:0] change from 000 to 111, and the output of the latch encoder As a result, the multiplexers MUX1 and MUX2 are controlled to select pulses with different phase delays and send them to the clock input terminals of DFF1 and DFF2 through the output terminals MUX1_O and MUX2_O. The pulse signal output by MUX_O is used as a clock signal to sample the Strobe pulse to obtain the values of Q1 and Q2. The MUX_O output terminal outputs a pulse signal with a certain phase delay. At this time, the values of Q1 and Q2 are 1, the signals of E1 and E2 are 1, the values of DP[7:1] and DN[7:1] increase by 1, and the encoder is latched. Continue encoding, the output encoding value N1[2:0], N[2:0] increases by 1, MUX1, MUX2 select a pulse output with a larger phase delay, and send it to DFF as a clock signal to continue sampling Strobe pulses until MUX1, MUX2 The phase of the pulse signal output by MUX2 is the same as the Strobe pulse. At this time, the values of Q1 and Q2 are 0, and the values of E1 and E2 become 0. The latch encoder stops encoding and latches the encoding value. The values of DP[7:1] and DN[7:1] continue to change until they become 0000000 and stop changing, waiting for the arrival of the pulse that generates the output result.

At this time, the code values of DC1 and DC2 of the latch encoder are N1 and N2, △Tα=△N*V _offset *G _m *K, where △Tα is the phase difference, the sign is uncertain, and the positive value represents the phase advance, and the value is Negative means phase lag. △N=N1-N2, which is the difference between the code values of the two latch encoders. △Tα is the manifestation of the phase difference in the time domain of the DC offset voltage, and its numerical change represents the magnitude of the DC offset voltage.

During the period when EN_Cal is equal to 0, the switch S0 is closed, and the switch S1 is opened. At this time, the time domain comparator works in the stage of generating the comparison result. The gates of the PMOS transistors MP1 and MP2 are respectively connected to the reference voltage V _REF and the sampling voltage V _Sample . At this time, the voltage difference between the gates of MP1 and MP2 is △V=VP-VN=(V _REF -V _Sample ）+V _offset . At this time, the sampling signal Strobe used to generate the comparison result is input. At this time, △Tr=△T-△Tα, △T=△N*△V*G _m *K, D flip-flops DFF1, DFF2 according to the positive value of △Tr Negative generation of the comparator comparison result, that is, the output result is generated according to the phase sequence relationship of the output pulses of the multiplexer output MUX1_O and MUX2_O. △Tr is the phase difference after eliminating the influence of the DC offset voltage, so as to eliminate the DC offset voltage in the time domain.

Combined with the timing relationship, as shown in Figure 3, when the input voltage V _Sample > V _REF and △Tr is positive, it means that the phase of the pulse signal output by MUX1_O lags behind the phase of the pulse signal output by MUX2_O. At this time, Q1 of DFF2 changes from 1 to is 0, the Q1 signal sets the D flip-flop DFF2 to 1, EN_Cal is 0, and comp_out is 1. When the input voltage V _Sample < V _REF , and △Tr is negative, it means that the phase of the pulse signal output by MUX2_O lags behind the phase of the pulse signal output by MUX1_O. Set to 1, EN_Cal to 0, comp_out to 0. The above is the working process of the comparator comparison result generation stage. The comparison result eliminates the influence of the DC offset voltage on the comparison result, which increases the comparison accuracy of the comparator.

The comparator converts the DC offset voltage into the form of time-domain phase difference in the offset elimination stage, and adds the phase difference ΔTα caused by the DC offset to the total phase difference ΔT in the stage of generating comparison results to achieve the time-domain elimination of DC The role of offset voltage.

In the sampling encoding stage, the comparator array outputs the temperature code, and the temperature code passes through the bubble elimination circuit. The bubble elimination circuit corrects the error codes of 010 and 101, and obtains the correct output temperature code 000, 111, eliminating the error caused by the comparator sampling. In case of coding errors. The temperature code is sent to the encoder after being corrected by the bubble elimination circuit. The encoder converts the temperature code into BCD code output, and the encoder is written in an all-digital hardware language.

The above-mentioned FLASHADC using the time-domain offset elimination technology provided by the present invention. The DC offset voltage is eliminated in the time domain, which improves the conversion accuracy of the ADC, reduces the influence of the DC offset voltage on the static characteristics of the ADC, and saves the chip area occupied by the capacitor required by the traditional offset elimination technology. The simulation result shows that when the sampling clock clk is 2.5MHz, when the FLASHADC has a resolution of 6 bits and the differential input range is 0.64v, the minimum LSB can reach 10mv. When the sampling clock frequency is reduced, the LSB can be reduced to improve the accuracy of the ADC.

Claims (1)

1. an ADC converter, comprising resistance divider network, time domain comparator, bubble elimination circuit and encoder, is characterized in that: the VN input terminal of described time domain comparator is connected with sampling voltage V _Sample , and time domain compares The VP input terminal of the time domain comparator is connected with the reference voltage V _REF ; the V _bias input terminal of the time domain comparator is connected with the external reference voltage input signal V _BIAS ; the En_Cal input terminal of the time domain comparator is connected with the calibration enable EN_Cal signal; the time domain comparison The Strobe input end of the device is connected with the sampling signal Strobe; the comp_out output end of the time domain comparator is connected with the input end of the described bubble elimination circuit and the encoder; the described time domain comparator is composed of 19 PMOS transistors and 4 NMOS transistors , 2 AND gates, 1 NOR gate, 2 latch encoders, 2 multiplexers and 14 delay units; the time domain comparator controls the sampling voltage V _Sample , the reference voltage V _REF and the sampling signal Strobe and calibration enable the EN_Cal signal to be processed to generate an output signal, which is output from the comp_out output terminal; The 19 PMOS tubes are respectively MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, MP16, MP17, MP18 and MB; The NMOS tubes are MN1, MN2, MN3 and MN4 respectively; the two AND gates are AND gate AND1 and AND gate AND2 respectively; the two latch encoders are latch encoder DC1 and latch encoder DC2 respectively; two multi-channel The multiplexers are multiplexer MUX1 and multiplexer MUX2; the 14 delay units are DP1, DP2, DP3, DP4, DP5, DP6, DP7, DN1, DN2, DN3, DN4, DN5, DN6 and DN7; The source of the PMOS transistor MB is connected to the power supply voltage VDD, the gate of the PMOS transistor MB is connected to the external reference voltage input signal V _BIAS , and the drain of the PMOS transistor MB is at the same point as the sources of the PMOS transistors MP1 and MP2; The gates of MP1 and MP2 are connected through the switch S1, the gate of the PMOS transistor MP1 is connected with the reference voltage V _REF , the gate of the PMOS transistor MP2 is connected with the VN input terminal of the time domain comparator through the switch S0; the drain of the PMOS transistor MP1 is connected with the NMOS transistor The drain of MN1, the gate of MN1, and the gate of MN4 are at the same point, the drain of the PMOS transistor MP2 is at the same point as the drain of the NMOS transistor MN2, the gate of MN2, and the gate of MN3; the NMOS transistors MN1, MN2, and MN3 It is at the same point as the source of MN4 and connected to the power ground VSS; the drain of MN3 is at the same point as the drain of MP3 and the gates of MP3, MP4, MP5, MP6, MP7, MP8, MP9 and MP10; the drain of MN4 is at the same point as The drain of MP11 and the gates of MP11, MP12, MP13, MP14, MP15, MP16, MP17 and MP18 are at the same point; The drains of the PMOS transistors MP4, MP5, MP6, MP7, MP8, MP9 and MP10 are respectively connected to the power terminals of the delay units DP1, DP2, DP3, DP4, DP5, DP6 and DP7, and the PMOS transistors MP12, MP13, MP14, The drains of MP15, MP16, MP17 and MP18 are respectively connected to the power supply terminals of the delay units DN1, DN2, DN3, DN4, DN5, DN6 and DN7; the delay units DP1, DP2, DP3, DP4, DP5, DP6 and DP7 are connected end to end to form Delay chain, the input terminal of DP1 is connected to the sampling signal Strobe, and the encoded output signal DP[7:1] is generated and connected to the data input terminal of the latch encoder DC1; delay units DN1, DN2, DN3, DN4, DN5, DN6 and DN7 The end-to-end connection forms a delay chain. The input end of DN1 is connected to the sampling signal Strobe to generate the encoded output signal DN[7:1] and is connected to the data input end of the latch encoder DC2; delay units DP1, DP2, DP3, DP4, DP5, The output ends of DP6 and DP7 are connected with the signal input end of multiplexer MUX1, and the output ends of delay units DN1, DN2, DN3, DN4, DN5, DN6 and DN7 are connected with the signal input end of multiplexer MUX2; The output signal N1[2:0] of the latch encoder DC1 is connected to the selection terminal of the multiplexer MUX1, and the output signal N2[2:0] of the latch encoder DC2 is connected to the selection terminal of the multiplexer MUX2 connected; The output signal MUX1_0 of the multiplexer MUX1 is connected to the CLK of the D flip-flop DFF1, the output signal MUX2_0 of the multiplexer MUX2 is connected to the CLK of the D flip-flop DFF2, and the data input terminals D of the D flip-flops DFF1 and DFF2 are connected to The sampling signal Strobe is connected; the output signals Q1 and Q2 of the D flip-flops DFF1 and DFF2 are respectively connected with the calibration enable EN_Cal signal through the AND gates AND1 and AND2 to generate signals E1 and E2, and are respectively connected with the latch encoder DC1 and the latch encoder DC2 The enable control input is connected; the Q2 signal and the calibration enable EN_Cal signal pass through the NOR gate to generate the output result of the comparator and output it through the comp_out output.