CN102832162A - Air bridge three-dimensional circuit and manufacturing method thereof - Google Patents
Air bridge three-dimensional circuit and manufacturing method thereof Download PDFInfo
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- CN102832162A CN102832162A CN2011101572409A CN201110157240A CN102832162A CN 102832162 A CN102832162 A CN 102832162A CN 2011101572409 A CN2011101572409 A CN 2011101572409A CN 201110157240 A CN201110157240 A CN 201110157240A CN 102832162 A CN102832162 A CN 102832162A
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Abstract
本发明涉及一种空气桥立体电路及其制作方法，包括：提供半导体衬底和形成在半导体衬底上的至少两个焊垫；在衬底和焊垫表面形成第一光刻胶层，对第一光刻胶层进行曝光以在第一光刻胶层中形成第一待去除区，第一待去除区分别与各焊垫上方的区域对应；在第一光刻胶层上形成第二光刻胶层，对第二光刻胶层曝光以在第二光刻胶层中形成第二待去除区，第二待去除区为包括对应于各第一待去除区上方和相邻第一待去除区之间的区域；去除第一待去除区中的第一光刻胶层和第二待去除区中的第二光刻胶层，以形成空气桥图案；在空气桥图案中填充金属以形成空气桥立体电路；去除剩余的第一光刻胶层和第二光刻胶层。本发明的方法提高了生产效率且降低了生产成本。
The invention relates to an air bridge three-dimensional circuit and a manufacturing method thereof, comprising: providing a semiconductor substrate and at least two welding pads formed on the semiconductor substrate; forming a first photoresist layer on the surfaces of the substrate and the welding pads, and The first photoresist layer is exposed to form a first region to be removed in the first photoresist layer, and the first region to be removed corresponds to the region above each welding pad; a second region is formed on the first photoresist layer. The photoresist layer is exposed to the second photoresist layer to form a second region to be removed in the second photoresist layer. Region between the regions to be removed; remove the first photoresist layer in the first region to be removed and the second photoresist layer in the second region to be removed to form an air bridge pattern; fill the air bridge pattern with metal To form an air bridge three-dimensional circuit; remove the remaining first photoresist layer and second photoresist layer. The method of the invention improves production efficiency and reduces production cost.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of air bridges stereo circuit and preparation method thereof.
Background technology
In the modem semi-conductor devices manufacturing process, along with circuit structure becomes increasingly complex, one time metal connecting line can not meet the demands, and it is interconnected therefore often to adopt repeatedly metal to carry out.But when metal wire intersects each other or be overlapping, will there be parasitic capacitance.Because the dielectric constant of permittivity ratio such as the silicon dioxide of air and traditional inter-level dielectric of silicon nitride is low; The intersection or the overlapping metal wire parasitic capacitance that with the air are medium are lower; Therefore in the manufacture process of microelectronic component, circuit; Some crucial metal wires intersect or overlapping, often adopt air as medium, and this structure is called air bridges.The method of common metal sputter at present or chemical plating is made air bridges.The air bridges body that adopts above-mentioned two kinds of methods to make is thinner relatively, therefore causes rate of finished products and reliability relatively poor, and the protective value of the conductor circuit of formation itself a little less than, the metal of partial design is directly exposed in the air.
Therefore, need a kind of manufacture method of air bridges, to solve the problem that exists in the prior art.
Summary of the invention
In the summary of the invention part, introduced the notion of a series of reduced forms, this will further explain in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to confirm technical scheme required for protection.
In order to solve existing air bridges manufacture craft relative complex, problem such as process controllability and precision are relatively poor the invention provides structure of a kind of air bridges stereo circuit and preparation method thereof:
A kind of manufacture method of air bridges stereo circuit is characterized in that comprising:
Step 1 provides Semiconductor substrate and is formed at least two weld pads on the said Semiconductor substrate;
Step 2 forms first photoresist layer at said substrate and said weld pad surface, to said first
Photoresist layer makes public and waits to remove the district in said first photoresist layer, to form first, and said first waits to remove district regional corresponding with each said weld pad top respectively;
Step 3 forms second photoresist layer, to said second photoetching on said first photoresist layer
Glue-line exposure waits to remove the district in said second photoresist layer, to form second, and said second waits to remove the district comprises corresponding to each said first waiting to remove the zone that top, district and adjacent said first waits to remove between the district;
Step 4 is removed said first first photoresist layer and said second waiting to remove in the district and is waited to remove
Said second photoresist layer in the district is to form the air bridges pattern;
Step 5 is filled metal to form the air bridges stereo circuit in said air bridges pattern;
Step 6 is removed remaining said first photoresist layer and said second photoresist layer.
Also be included in the zone that is not coated with said weld pad on edge and the said Semiconductor substrate of said weld pad between said step 1 and the step 2 and form the step of first passivation layer.
Also be included in the step that forms ubm layer on said first passivation layer and the said weld pad surface, and removal does not cover the said ubm layer on the said weld pad in said step 6.
Each said first waits that the edge of removing the district is positioned on said first passivation layer that covers said weld pad edge.
Also comprise the step of cleaning the weld pad surface between said step 1 and the said step 2.
Said first photoresist layer adopts negative photoresist, and said second photoresist layer adopts negative photoresist.
Said first photoresist layer adopts positive photoresist, and said second photoresist layer adopts negative photoresist.
Said metal is a copper.
The method of said filling metal is for electroplating.
The material of said weld pad is an aluminium.
Also be included in the step that forms second passivation layer on the said air bridges stereo circuit surface, and the position of corresponding at least one said weld pad forms opening in said second passivation layer, in said opening, forms salient point.
Also be included on the said salient point and form conductive layer, the material of said conductive layer is tin or copper.
The method of removing first photoresist layer and second photoresist layer in the said step 4 is for developing and ashing.
A kind of air bridges stereo circuit is characterized in that: said air bridges stereo circuit comprises:
-Semiconductor substrate;
-weld pad, the quantity of said weld pad is at least two, and said pad-shaped is formed on the said Semiconductor substrate;
-bridge pier, said bridge pier are formed on each said weld pad; With
-bridge floor, said bridge floor are formed at each said bridge pier top and interconnect, and wherein adopt electric plating method to form said bridge pier and bridge floor.
The zone that is not coated with said weld pad on the edge of said weld pad and the said Semiconductor substrate is formed with first passivation layer.
Be formed with ubm layer between said weld pad and the said bridge pier.
Be formed with second passivation layer on the said bridge floor, and the position of corresponding at least one said weld pad is formed with opening in said second passivation layer, is formed with salient point in the said opening.
Be formed with conductive layer on the said salient point, the material of said conductive layer is tin or copper.
The material of said air bridges stereo circuit is a copper.
The thickness range of said bridge pier is 3 ~ 20 microns.
The thickness range of said bridge floor is 1 ~ 15 micron.
The manufacture method of air bridges stereo circuit of the present invention has been utilized the difference of the positive and negative property of multilayer light-sensitive material, carries out multiexposure, multiple exposure, once develop, and the figure that formation needs, work simplification has improved production efficiency and has reduced production cost.The air bridges stereo circuit of processing according to method provided by the invention has the overhead viaduct type structure, and Stability Analysis of Structures, reliability are higher, and the below of air bridges stereo circuit is an air, can effectively improve the electrical property under electrical property, the especially high frequency condition of device.And the air bridges stereo circuit is coated with insulating barrier on the surface, has increased the protective value of circuit.
Description of drawings
Attached drawings of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Fig. 1 K is the method flow sketch map according to the making air bridges circuit of the embodiment of the invention one;
Fig. 2 A to Fig. 2 K is the method flow sketch map according to the making air bridges circuit of the embodiment of the invention two.
Embodiment
In the description hereinafter, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and be able to enforcement.In other example,, describe for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed so that explanation the present invention be how to the light-sensitive material exposure of different attribute, develop that existing air-bridge process is complicated, the relatively poor problem of controllability to solve.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Embodiment one
At first, shown in Figure 1A, Semiconductor substrate 100 is provided and is formed at least two weld pads 101 on the Semiconductor substrate 100, the zone that on the edge of weld pad 101 and Semiconductor substrate 100, is not coated with weld pad 101 forms first passivation layer 102.First passivation layer 102 that covers weld pad 101 edges is higher than first passivation layer 102 that is formed on the substrate 100.The device architecture that again above-mentioned steps is obtained cleans, and removes the oxide layer of self-sow on device architecture through cleaning and removing, it will be appreciated by persons skilled in the art that said cleaning can adopt cleaning agents such as hydrofluoric acid.
Wherein, substrate 100 can be silicon or silicon-on-insulator (SOI).In substrate 100, can be formed with isolation structure, said isolation structure is that shallow trench isolation leaves (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Also be formed with the channel layer of various traps (well) structure and substrate surface in the substrate 100.In general, the ion doping conduction type that forms trap (well) structure is identical with channel layer ion doping conduction type, but concentration is low than gate channel layer, and the depth bounds that ion injects is wider, need reach the degree of depth greater than isolation structure simultaneously.In order to simplify, here only with a blanket substrates 100 diagrams.
Can comprise as the illustrative examples that contains the Si semi-conducting material of substrate 100: SiGe (SGOI) on Si, SiGe, SiC, SiGeC, silicon-on-insulator (SOI) or the insulator, but be not limited thereto.According to the device of manufacturing, substrate 100 can be unadulterated or mix.
Shown in Figure 1B; Utilize physical vapour deposition (PVD) (Physical Vapor Deposition PVD) on above-mentioned substrate 100, to form ubm layer 103 (Under Bump Metal UBM); It will be understood by those skilled in the art that; The structure of ubm layer 103 comprise adhesion layer be formed on the Seed Layer on the said adhesion layer, the material of said adhesion layer can be Titanium (Ti), thallium (Ta) or its alloy, said Seed Layer can be copper (Cu) or copper alloy.
Shown in Fig. 1 C, on ubm layer 103, form first photoresist layer, 104, the first photoresist layers 104 and adopt positive photoresist.
Shown in Fig. 1 D; First photoresist layer 104 made public wait to remove the district 104a and the first reserved area 104b in first photoresist layer 104, to form first; First waits to remove district 104a needs removed zone behind the process subsequent technique; The first reserved area 104b is the zone through still being retained behind the subsequent technique, and first waits to remove the zone of district 104a corresponding to each weld pad 101 tops, and first waits that the edge of removing district 104a is positioned on first passivation layer 102 around weld pad 101 edges.First photoresist layer 104 adopts positive photoresist in the present embodiment, then waits to remove district 104a to first and makes public, and the first reserved area 104b does not make public.
Shown in Fig. 1 E, on first photoresist layer 104, form second photoresist layer, 105, the second photoresist layers 105 and adopt negative photoresist.
Shown in Fig. 1 F; Second photoresist layer 105 made public wait to remove district 105a in second photoresist layer 105, to form second; Remaining zone is the second reserved area 105b in second photoresist layer 105, and second waits to remove district 105a comprises corresponding to each first waiting to remove 104a top, district and adjacent first and waiting to remove the zone between the district 104a.Promptly second wait to remove the zone of district 105a for dash area in second photoresist layer 105 shown in Fig. 1 F.Second photoresist layer 105 adopts negative photoresist in the present embodiment, therefore the second reserved area 105b is made public, and second waits to remove district 105a does not make public.
Shown in Fig. 1 G, first photoresist layer 104 and second photoresist layer 105 are developed and ashing, in first photoresist layer 104 and second photoresist layer 105, to form air bridges pattern 106.Remove first in first photoresist layer 104 and second photoresist layer 105 respectively through development, ashing and treat that removal district 104a and second waits to remove district 105a part.Wherein, the method for said ashing is that using plasma is removed.In first photoresist layer of removing 104 first waited to remove the bridge pier part that district 104a forms air bridges pattern 106, and second waits to remove the bridge floor part in the district 105a formation air bridges pattern 106 in second photoresist layer 105 of removal.
Shown in Fig. 1 H, plated metal in air bridges pattern 106, said metal can be copper, in air bridges pattern 106, to form air bridges stereo circuit 107.Air bridges stereo circuit 107 comprises bridge pier part 107a and bridge floor part 107b, and bridge floor part 107b is positioned at the top of bridge pier part 107a and adjacent bridge pier part 107a is coupled together.
Shown in Fig. 1 I, remove remaining first photoresist layer 104 and second photoresist layer 105 and remove and do not cover the ubm layer 103 on the weld pad 101.It will be appreciated by persons skilled in the art that remove first photoresist layer 104, second photoresist layer 105 can adopt the common method in this area, for example peel off.Remove part ubm layer 103 and can adopt wet etching.When ubm layer 103 is carried out etching; Be higher than first passivation layer 102 that is formed on the Semiconductor substrate 100 owing to cover the height of first passivation layer 102 at weld pad 101 edges; Therefore the 102 pairs of ubm layers 103 of first passivation layer that are formed on the weld pad 101 have protective effect, and then avoid being positioned at the removal that is etched of ubm layer 103 on the weld pad 101.
Shown in Fig. 1 J; On the bridge floor part 107b of air bridges stereo circuit 107, form second passivation layer 108; The position of corresponding at least one weld pad 101 forms opening 109 in second passivation layer 108; In opening 109, form salient point 110 again, salient point 110 links to each other with the bridge pier part 107a of air bridges stereo circuit 107.The size of pairs of openings 109 of the present invention does not limit, and a plurality of openings 109 can be set according to the design requirement of side circuit.The material of salient point 110 is a copper, its role is to the air bridges circuit is connected to external circuit.The effect of second passivation layer 108 is to avoid air bridges stereo circuit 107 to receive humid air corrosion or oxidation.
Preferably, shown in Fig. 1 K, be easy to more and being connected of external circuit in order to make the air bridges circuit, on salient point 110, form conductive layer 111, the material of said conductive layer 111 can be tin or copper.
Embodiment two
At first, shown in Fig. 2 A, substrate 200 is provided and is formed at least two weld pads 201 on the substrate 200, be formed with first passivation layer 202 around the edge of weld pad 201 and the weld pad 201.First passivation layer 202 at weld pad 201 edges is higher than first passivation layer 202 that is formed on the substrate 200.The device architecture that again above-mentioned steps is obtained cleans, and removes the oxide layer on the self-sow device architecture through cleaning and removing, it will be appreciated by persons skilled in the art that said cleaning can adopt cleaning agents such as hydrofluoric acid.
Wherein, substrate 200 can be silicon or silicon-on-insulator (SOI).In substrate 200, can be formed with isolation structure, said isolation structure is that shallow trench isolation leaves (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Also be formed with the channel layer of various traps (well) structure and substrate surface in the substrate 200.In general, the ion doping conduction type that forms trap (well) structure is identical with channel layer ion doping conduction type, but concentration is low than gate channel layer, and the depth bounds that ion injects is wider, need reach the degree of depth greater than isolation structure simultaneously.In order to simplify, here only with a blanket substrates 200 diagrams.
Can comprise as the illustrative examples that contains the Si semi-conducting material of substrate 200: SiGe (SGOI) on Si, SiGe, SiC, SiGeC, silicon-on-insulator (SOI) or the insulator, but be not limited thereto.According to the device of manufacturing, substrate 200 can be unadulterated or mix.
Shown in Fig. 2 B; Utilize physical vapour deposition (PVD) (Physical Vapor Deposition PVD) on substrate 200, to form ubm layer 203 (Under Bump Metal UBM); It will be understood by those skilled in the art that; The structure of ubm layer 203 comprise adhesion layer be formed on the Seed Layer on the said adhesion layer, the material of said adhesion layer can be Titanium (Ti), thallium (Ta) or its alloy, said Seed Layer can be copper (Cu) or copper alloy.
Shown in Fig. 2 C, on ubm layer 203, form first photoresist layer, 204, the first photoresist layers 204 and adopt negative photoresist.
Shown in Fig. 2 D; First photoresist layer 204 makes public and waits to remove the district 204a and the first reserved area 204b in first photoresist layer 204, to form first; First waits to remove district 204a needs removed zone behind the process subsequent technique; The first reserved area 204b is the zone through still being retained behind the subsequent technique; First waits to remove the zone of district 204a corresponding to each weld pad 201 tops, and first wait to remove the zone of district 204a corresponding to each weld pad 201 tops, and first waits that the edge of removing district 204a is positioned on first passivation layer 202 around weld pad 201 edges.First photoresist layer 204 adopts negative photoresist in the present embodiment, then the first reserved area 204b is made public, and first waits to remove district 204a does not make public.
Shown in Fig. 2 E, on first photoresist layer 204, form second photoresist layer, 205, the second photoresist layers 205 and adopt negative photoresist.
Shown in Fig. 2 F; Second photoresist layer 205 made public wait to remove district 205a in second photoresist layer 205, to form second; Remaining zone is the second reserved area 205b, and second waits to remove district 205a comprises corresponding to each first waiting to remove 204a top, district and adjacent first and waiting to remove the zone between the district 204a.Promptly second wait to remove the zone of district 205b for dash area in second photoresist layer 205 shown in Fig. 2 F.Second photoresist layer 205 adopts negative photoresist in the present embodiment, therefore the second reserved area 205b is made public, and second waits to remove district 205a does not make public.
Shown in Fig. 2 G, first photoresist layer 204 and second photoresist layer 205 are developed and ashing, in first photoresist layer 204 and second photoresist layer 205, to form air bridges pattern 206.Remove first in first photoresist layer 204 and second photoresist layer 205 respectively through development, ashing and treat that removal district 204a and second waits to remove district 205a part.Wherein, the method for said ashing is that using plasma is removed.In first photoresist layer of removing 204 first waited to remove the bridge pier part that district 204a forms air bridges pattern 206, and second waits to remove the bridge floor part in the district 205a formation air bridges pattern 206 in second photoresist layer 205 of removal.
Shown in Fig. 2 H, plated metal in air bridges pattern 206, said metal can be copper, in air bridges pattern 206, to form air bridges stereo circuit 207.Air bridges stereo circuit 207 comprises bridge pier part 207a and bridge floor part 207b, and bridge floor part 207b is positioned at the top of bridge pier part 207a and adjacent bridge pier part 207a is coupled together.
Shown in Fig. 2 I, remove remaining first photoresist layer 204 and second photoresist layer 205 and remove and do not cover the ubm layer 203 on the weld pad 201.It will be appreciated by persons skilled in the art that remove first photoresist layer 204, second photoresist layer 205 can adopt the common method in this area, for example peel off.Remove part ubm layer 203 and can adopt wet etching.When ubm layer 203 is carried out etching; Be higher than first passivation layer 202 that is formed on the Semiconductor substrate 200 owing to cover first passivation layer 202 at the edge of weld pad 201; Therefore the 202 pairs of ubm layers 203 of first passivation layer that are formed on the weld pad 201 have protective effect, and then avoid being positioned at the removal that is etched of ubm layer 203 on the weld pad 201.
Shown in Fig. 2 J; On the bridge floor part 207b of air bridges stereo circuit 207, form second passivation layer 208; The position of corresponding at least one weld pad 201 forms opening 209 in second passivation layer 208; In opening 209, form salient point 210 again, salient point 210 links to each other with the bridge pier part 207a of air bridges stereo circuit 207.The size of pairs of openings 209 of the present invention does not limit, and a plurality of openings 209 can be set according to the design requirement of side circuit.The material of salient point 210 is a copper, its role is to the air bridges circuit is connected to external circuit.The effect of second passivation layer 208 is to avoid air bridges stereo circuit 207 to receive humid air corrosion or oxidation.
Preferably, shown in Fig. 2 K, be easy to more and being connected of external circuit in order to make the air bridges circuit, on salient point 210, form conductive layer 211, the material of said conductive layer 211 can be tin or copper.
It will be appreciated by persons skilled in the art that in above-mentioned two embodiment, said exposure can realize through the photoresist layer that the masked plate of ultraviolet irradiation blocks.
Bridge floor thickness partly according to the foregoing description one and the air bridges stereo circuit of embodiment two making is 1 ~ 15 micron, and the thickness range of bridge pier is 3 ~ 20 microns.Therefore higher and reliability is better according to the rate of finished products of air bridges stereo circuit structure of the present invention.
The manufacture method of air bridges stereo circuit of the present invention has been utilized the difference of the positive and negative property of multilayer light-sensitive material, carries out multiexposure, multiple exposure, once develop, and the figure that formation needs, this method has work simplification, production efficiency height and the lower characteristics of production cost.The air bridges stereo circuit of processing according to method provided by the invention has the overhead viaduct type structure, and Stability Analysis of Structures, reliability are higher, and the below of air bridges stereo circuit is an air, can effectively improve the electrical property under electrical property, the especially high frequency condition of device.Be coated with insulating barrier on the air bridges stereo circuit surface that forms, increased the protective value of circuit.
The present invention is illustrated through the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by appended claims book and equivalent scope thereof.
Claims (21)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106744655A (en) * | 2016-11-30 | 2017-05-31 | 合肥工业大学 | A kind of method for preparing microdischarge cavities metal structure on a silicon substrate |
| CN109860147A (en) * | 2019-02-22 | 2019-06-07 | 福建省福联集成电路有限公司 | A kind of stacked capacitor manufacturing method and semiconductor devices |
| CN115700217A (en) * | 2021-07-21 | 2023-02-07 | 合肥本源量子计算科技有限责任公司 | A preparation method of an air bridge and a superconducting quantum device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020140007A1 (en) * | 2001-03-30 | 2002-10-03 | Fujitsu Quantum Devices Limited | Semiconductor device and method for fabricating the same |
| CN1446377A (en) * | 2000-07-12 | 2003-10-01 | 摩托罗拉公司 | Electronic component and method of manufacture |
| CN101154604A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Bump making method |
| CN101561628A (en) * | 2008-04-16 | 2009-10-21 | 中国科学院微电子研究所 | Method for manufacturing air bridge |
| US20100003623A1 (en) * | 2008-07-03 | 2010-01-07 | United Microelectronics Corp. | Method of patterning multiple photosensitive layers |
-
2011
- 2011-06-13 CN CN2011101572409A patent/CN102832162A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1446377A (en) * | 2000-07-12 | 2003-10-01 | 摩托罗拉公司 | Electronic component and method of manufacture |
| US20020140007A1 (en) * | 2001-03-30 | 2002-10-03 | Fujitsu Quantum Devices Limited | Semiconductor device and method for fabricating the same |
| CN101154604A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Bump making method |
| CN101561628A (en) * | 2008-04-16 | 2009-10-21 | 中国科学院微电子研究所 | Method for manufacturing air bridge |
| US20100003623A1 (en) * | 2008-07-03 | 2010-01-07 | United Microelectronics Corp. | Method of patterning multiple photosensitive layers |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106744655A (en) * | 2016-11-30 | 2017-05-31 | 合肥工业大学 | A kind of method for preparing microdischarge cavities metal structure on a silicon substrate |
| CN109860147A (en) * | 2019-02-22 | 2019-06-07 | 福建省福联集成电路有限公司 | A kind of stacked capacitor manufacturing method and semiconductor devices |
| CN115700217A (en) * | 2021-07-21 | 2023-02-07 | 合肥本源量子计算科技有限责任公司 | A preparation method of an air bridge and a superconducting quantum device |
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